| T827 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.1605521256 |
|
|
Feb 09 02:22:58 PM UTC 25 |
Feb 09 02:23:03 PM UTC 25 |
615313460 ps |
| T828 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.2160590662 |
|
|
Feb 09 02:22:31 PM UTC 25 |
Feb 09 02:23:05 PM UTC 25 |
5301243423 ps |
| T829 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_errors.597603727 |
|
|
Feb 09 02:22:44 PM UTC 25 |
Feb 09 02:23:06 PM UTC 25 |
383735936 ps |
| T830 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.3086867747 |
|
|
Feb 09 02:22:57 PM UTC 25 |
Feb 09 02:23:09 PM UTC 25 |
664811254 ps |
| T159 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2622819619 |
|
|
Feb 09 02:16:21 PM UTC 25 |
Feb 09 02:23:11 PM UTC 25 |
22230841707 ps |
| T831 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.4028686664 |
|
|
Feb 09 02:22:40 PM UTC 25 |
Feb 09 02:23:11 PM UTC 25 |
187842412 ps |
| T832 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.1737837960 |
|
|
Feb 09 02:22:47 PM UTC 25 |
Feb 09 02:23:12 PM UTC 25 |
1214696403 ps |
| T833 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_errors.2324535619 |
|
|
Feb 09 02:23:00 PM UTC 25 |
Feb 09 02:23:14 PM UTC 25 |
669021997 ps |
| T834 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.1747738739 |
|
|
Feb 09 02:23:13 PM UTC 25 |
Feb 09 02:23:15 PM UTC 25 |
27761907 ps |
| T835 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2826520064 |
|
|
Feb 09 02:23:14 PM UTC 25 |
Feb 09 02:23:16 PM UTC 25 |
29645420 ps |
| T836 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.420137630 |
|
|
Feb 09 02:23:13 PM UTC 25 |
Feb 09 02:23:17 PM UTC 25 |
186932510 ps |
| T837 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.1878628624 |
|
|
Feb 09 02:23:06 PM UTC 25 |
Feb 09 02:23:19 PM UTC 25 |
1451883724 ps |
| T838 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.3053145527 |
|
|
Feb 09 02:23:04 PM UTC 25 |
Feb 09 02:23:21 PM UTC 25 |
475162705 ps |
| T839 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.797003347 |
|
|
Feb 09 02:23:03 PM UTC 25 |
Feb 09 02:23:22 PM UTC 25 |
2102542093 ps |
| T840 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.4269146144 |
|
|
Feb 09 02:23:03 PM UTC 25 |
Feb 09 02:23:22 PM UTC 25 |
1019660347 ps |
| T841 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.961997186 |
|
|
Feb 09 02:21:19 PM UTC 25 |
Feb 09 02:23:22 PM UTC 25 |
5725436956 ps |
| T842 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.2069863078 |
|
|
Feb 09 02:23:17 PM UTC 25 |
Feb 09 02:23:23 PM UTC 25 |
290451258 ps |
| T843 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.2410913796 |
|
|
Feb 09 02:23:01 PM UTC 25 |
Feb 09 02:23:28 PM UTC 25 |
1244988087 ps |
| T844 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.3322737310 |
|
|
Feb 09 02:23:16 PM UTC 25 |
Feb 09 02:23:28 PM UTC 25 |
267525421 ps |
| T845 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.2820243156 |
|
|
Feb 09 02:23:19 PM UTC 25 |
Feb 09 02:23:28 PM UTC 25 |
431907957 ps |
| T846 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.903035225 |
|
|
Feb 09 02:23:29 PM UTC 25 |
Feb 09 02:23:32 PM UTC 25 |
77282591 ps |
| T847 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.3944599702 |
|
|
Feb 09 02:22:56 PM UTC 25 |
Feb 09 02:23:33 PM UTC 25 |
146223650 ps |
| T848 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.1335501492 |
|
|
Feb 09 02:23:29 PM UTC 25 |
Feb 09 02:23:35 PM UTC 25 |
45826823 ps |
| T849 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.566875532 |
|
|
Feb 09 02:23:32 PM UTC 25 |
Feb 09 02:23:35 PM UTC 25 |
95685838 ps |
| T850 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_errors.4154976141 |
|
|
Feb 09 02:23:18 PM UTC 25 |
Feb 09 02:23:35 PM UTC 25 |
1440262689 ps |
| T851 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.296859193 |
|
|
Feb 09 02:22:35 PM UTC 25 |
Feb 09 02:23:38 PM UTC 25 |
1729470180 ps |
| T852 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.420646981 |
|
|
Feb 09 02:23:21 PM UTC 25 |
Feb 09 02:23:38 PM UTC 25 |
5786886374 ps |
| T853 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.303550806 |
|
|
Feb 09 02:23:24 PM UTC 25 |
Feb 09 02:23:40 PM UTC 25 |
918422670 ps |
| T854 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.510410763 |
|
|
Feb 09 02:23:23 PM UTC 25 |
Feb 09 02:23:42 PM UTC 25 |
372130645 ps |
| T855 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.1295273692 |
|
|
Feb 09 02:23:36 PM UTC 25 |
Feb 09 02:23:42 PM UTC 25 |
284845701 ps |
| T856 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.969913445 |
|
|
Feb 09 02:23:23 PM UTC 25 |
Feb 09 02:23:45 PM UTC 25 |
632052227 ps |
| T857 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.2409901063 |
|
|
Feb 09 02:23:36 PM UTC 25 |
Feb 09 02:23:47 PM UTC 25 |
896960686 ps |
| T858 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.3962509749 |
|
|
Feb 09 02:23:39 PM UTC 25 |
Feb 09 02:23:48 PM UTC 25 |
365714421 ps |
| T859 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.619698708 |
|
|
Feb 09 02:23:39 PM UTC 25 |
Feb 09 02:23:51 PM UTC 25 |
230584143 ps |
| T860 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.3974312388 |
|
|
Feb 09 02:23:49 PM UTC 25 |
Feb 09 02:23:52 PM UTC 25 |
24364031 ps |
| T861 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.2095745747 |
|
|
Feb 09 02:23:43 PM UTC 25 |
Feb 09 02:23:58 PM UTC 25 |
996413385 ps |
| T862 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.9985643 |
|
|
Feb 09 02:23:15 PM UTC 25 |
Feb 09 02:24:00 PM UTC 25 |
1030036515 ps |
| T863 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.2199417201 |
|
|
Feb 09 02:21:31 PM UTC 25 |
Feb 09 02:24:02 PM UTC 25 |
25023785778 ps |
| T63 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.1580649117 |
|
|
Feb 09 02:23:37 PM UTC 25 |
Feb 09 02:24:02 PM UTC 25 |
2609003100 ps |
| T864 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.1334700033 |
|
|
Feb 09 02:23:43 PM UTC 25 |
Feb 09 02:24:03 PM UTC 25 |
662540033 ps |
| T865 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.3964573025 |
|
|
Feb 09 02:23:41 PM UTC 25 |
Feb 09 02:24:03 PM UTC 25 |
1302548479 ps |
| T160 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1986092164 |
|
|
Feb 09 02:09:11 PM UTC 25 |
Feb 09 02:24:11 PM UTC 25 |
130833445466 ps |
| T866 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.1102632058 |
|
|
Feb 09 02:23:34 PM UTC 25 |
Feb 09 02:24:18 PM UTC 25 |
418342786 ps |
| T867 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.3876222284 |
|
|
Feb 09 02:22:47 PM UTC 25 |
Feb 09 02:24:30 PM UTC 25 |
10340248567 ps |
| T868 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.316744853 |
|
|
Feb 09 02:20:55 PM UTC 25 |
Feb 09 02:24:42 PM UTC 25 |
23686057242 ps |
| T869 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.594229310 |
|
|
Feb 09 02:23:07 PM UTC 25 |
Feb 09 02:25:10 PM UTC 25 |
15757456490 ps |
| T870 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2328879082 |
|
|
Feb 09 02:15:07 PM UTC 25 |
Feb 09 02:25:18 PM UTC 25 |
114481169958 ps |
| T871 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.2401386614 |
|
|
Feb 09 02:22:18 PM UTC 25 |
Feb 09 02:25:30 PM UTC 25 |
8962291114 ps |
| T82 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.2400367312 |
|
|
Feb 09 02:23:24 PM UTC 25 |
Feb 09 02:25:40 PM UTC 25 |
11904531662 ps |
| T161 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3661230776 |
|
|
Feb 09 02:11:15 PM UTC 25 |
Feb 09 02:25:53 PM UTC 25 |
34215177087 ps |
| T122 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.2178334143 |
|
|
Feb 09 02:14:19 PM UTC 25 |
Feb 09 02:26:05 PM UTC 25 |
29239710419 ps |
| T162 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.2231526884 |
|
|
Feb 09 02:20:09 PM UTC 25 |
Feb 09 02:26:48 PM UTC 25 |
64550716272 ps |
| T187 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.1252502096 |
|
|
Feb 09 02:22:02 PM UTC 25 |
Feb 09 02:27:03 PM UTC 25 |
37094376681 ps |
| T188 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.3841736235 |
|
|
Feb 09 02:23:46 PM UTC 25 |
Feb 09 02:27:59 PM UTC 25 |
11161975951 ps |
| T163 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3257387511 |
|
|
Feb 09 02:17:10 PM UTC 25 |
Feb 09 02:28:19 PM UTC 25 |
37724242228 ps |
| T89 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2380535192 |
|
|
Feb 09 02:18:59 PM UTC 25 |
Feb 09 02:28:45 PM UTC 25 |
16319110136 ps |
| T189 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.362545684 |
|
|
Feb 09 02:17:38 PM UTC 25 |
Feb 09 02:29:28 PM UTC 25 |
17657985252 ps |
| T172 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1389099602 |
|
|
Feb 09 02:15:55 PM UTC 25 |
Feb 09 02:30:19 PM UTC 25 |
66634087708 ps |
| T173 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.46709826 |
|
|
Feb 09 02:17:59 PM UTC 25 |
Feb 09 02:31:11 PM UTC 25 |
134962143654 ps |
| T123 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.480926684 |
|
|
Feb 09 02:18:45 PM UTC 25 |
Feb 09 02:31:21 PM UTC 25 |
124381635869 ps |
| T174 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.3582383131 |
|
|
Feb 09 02:15:18 PM UTC 25 |
Feb 09 02:31:23 PM UTC 25 |
87987567935 ps |
| T90 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1420436053 |
|
|
Feb 09 02:19:00 PM UTC 25 |
Feb 09 02:33:59 PM UTC 25 |
47079197494 ps |
| T872 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3474649330 |
|
|
Feb 09 02:18:21 PM UTC 25 |
Feb 09 02:34:31 PM UTC 25 |
103424760663 ps |
| T186 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3922167082 |
|
|
Feb 09 02:10:38 PM UTC 25 |
Feb 09 02:34:52 PM UTC 25 |
35633797838 ps |
| T873 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1593357987 |
|
|
Feb 09 02:19:25 PM UTC 25 |
Feb 09 02:36:19 PM UTC 25 |
212250999633 ps |
| T874 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.154599197 |
|
|
Feb 09 02:23:48 PM UTC 25 |
Feb 09 02:37:08 PM UTC 25 |
48935965410 ps |
| T875 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2278508343 |
|
|
Feb 09 02:19:41 PM UTC 25 |
Feb 09 02:38:42 PM UTC 25 |
30600984315 ps |
| T876 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.3221427523 |
|
|
Feb 09 02:21:20 PM UTC 25 |
Feb 09 02:40:00 PM UTC 25 |
303540096070 ps |
| T877 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2689730742 |
|
|
Feb 09 02:22:37 PM UTC 25 |
Feb 09 02:42:02 PM UTC 25 |
60192448155 ps |
| T128 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.667710212 |
|
|
Feb 09 02:23:52 PM UTC 25 |
Feb 09 02:23:57 PM UTC 25 |
64199909 ps |
| T135 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1690816597 |
|
|
Feb 09 02:23:52 PM UTC 25 |
Feb 09 02:24:00 PM UTC 25 |
354189079 ps |
| T136 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1050452282 |
|
|
Feb 09 02:24:00 PM UTC 25 |
Feb 09 02:24:03 PM UTC 25 |
39394707 ps |
| T129 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1616170497 |
|
|
Feb 09 02:23:59 PM UTC 25 |
Feb 09 02:24:05 PM UTC 25 |
265708364 ps |
| T878 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2852111061 |
|
|
Feb 09 02:24:02 PM UTC 25 |
Feb 09 02:24:06 PM UTC 25 |
85077523 ps |
| T156 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2066957287 |
|
|
Feb 09 02:24:04 PM UTC 25 |
Feb 09 02:24:06 PM UTC 25 |
14322580 ps |
| T157 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1573529238 |
|
|
Feb 09 02:24:04 PM UTC 25 |
Feb 09 02:24:06 PM UTC 25 |
31592749 ps |
| T124 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.128929772 |
|
|
Feb 09 02:24:00 PM UTC 25 |
Feb 09 02:24:07 PM UTC 25 |
278244894 ps |
| T211 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1242976804 |
|
|
Feb 09 02:24:05 PM UTC 25 |
Feb 09 02:24:07 PM UTC 25 |
21757125 ps |
| T879 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.4234300935 |
|
|
Feb 09 02:24:06 PM UTC 25 |
Feb 09 02:24:08 PM UTC 25 |
180611908 ps |
| T119 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3746437779 |
|
|
Feb 09 02:24:04 PM UTC 25 |
Feb 09 02:24:09 PM UTC 25 |
139706518 ps |
| T203 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1008290266 |
|
|
Feb 09 02:24:07 PM UTC 25 |
Feb 09 02:24:10 PM UTC 25 |
106945964 ps |
| T130 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3030946474 |
|
|
Feb 09 02:24:07 PM UTC 25 |
Feb 09 02:24:10 PM UTC 25 |
42322133 ps |
| T880 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.507566816 |
|
|
Feb 09 02:24:07 PM UTC 25 |
Feb 09 02:24:11 PM UTC 25 |
95256486 ps |
| T881 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.573498574 |
|
|
Feb 09 02:24:08 PM UTC 25 |
Feb 09 02:24:11 PM UTC 25 |
141587135 ps |
| T155 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.4053340577 |
|
|
Feb 09 02:24:09 PM UTC 25 |
Feb 09 02:24:12 PM UTC 25 |
21136279 ps |
| T120 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2304540018 |
|
|
Feb 09 02:24:04 PM UTC 25 |
Feb 09 02:24:12 PM UTC 25 |
625977223 ps |
| T882 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2037592133 |
|
|
Feb 09 02:24:10 PM UTC 25 |
Feb 09 02:24:13 PM UTC 25 |
59139932 ps |
| T132 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3062896707 |
|
|
Feb 09 02:24:10 PM UTC 25 |
Feb 09 02:24:15 PM UTC 25 |
328765071 ps |
| T121 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4185917988 |
|
|
Feb 09 02:24:11 PM UTC 25 |
Feb 09 02:24:15 PM UTC 25 |
261547681 ps |
| T204 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2990751021 |
|
|
Feb 09 02:24:14 PM UTC 25 |
Feb 09 02:24:16 PM UTC 25 |
14347783 ps |
| T175 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.925278308 |
|
|
Feb 09 02:24:14 PM UTC 25 |
Feb 09 02:24:16 PM UTC 25 |
73755077 ps |
| T194 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3080419382 |
|
|
Feb 09 02:24:15 PM UTC 25 |
Feb 09 02:24:18 PM UTC 25 |
70279239 ps |
| T883 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2426591112 |
|
|
Feb 09 02:24:14 PM UTC 25 |
Feb 09 02:24:18 PM UTC 25 |
27819813 ps |
| T884 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.738537096 |
|
|
Feb 09 02:24:08 PM UTC 25 |
Feb 09 02:24:18 PM UTC 25 |
2953860605 ps |
| T176 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1206122466 |
|
|
Feb 09 02:24:16 PM UTC 25 |
Feb 09 02:24:19 PM UTC 25 |
19290348 ps |
| T125 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.576152204 |
|
|
Feb 09 02:24:14 PM UTC 25 |
Feb 09 02:24:19 PM UTC 25 |
92124303 ps |
| T205 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.799985471 |
|
|
Feb 09 02:24:16 PM UTC 25 |
Feb 09 02:24:19 PM UTC 25 |
49357749 ps |
| T885 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1854292489 |
|
|
Feb 09 02:24:17 PM UTC 25 |
Feb 09 02:24:20 PM UTC 25 |
136790248 ps |
| T206 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3762232152 |
|
|
Feb 09 02:24:18 PM UTC 25 |
Feb 09 02:24:22 PM UTC 25 |
51600184 ps |
| T158 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3487082261 |
|
|
Feb 09 02:24:17 PM UTC 25 |
Feb 09 02:24:23 PM UTC 25 |
1673656729 ps |
| T886 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2785636034 |
|
|
Feb 09 02:24:21 PM UTC 25 |
Feb 09 02:24:23 PM UTC 25 |
49663215 ps |
| T887 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.192546699 |
|
|
Feb 09 02:24:20 PM UTC 25 |
Feb 09 02:24:24 PM UTC 25 |
54778222 ps |
| T127 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2665384156 |
|
|
Feb 09 02:24:20 PM UTC 25 |
Feb 09 02:24:24 PM UTC 25 |
230836097 ps |
| T126 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.4090278008 |
|
|
Feb 09 02:24:20 PM UTC 25 |
Feb 09 02:24:24 PM UTC 25 |
51799343 ps |
| T888 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.620234902 |
|
|
Feb 09 02:24:19 PM UTC 25 |
Feb 09 02:24:25 PM UTC 25 |
206757422 ps |
| T207 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1796992095 |
|
|
Feb 09 02:24:23 PM UTC 25 |
Feb 09 02:24:25 PM UTC 25 |
45043277 ps |
| T195 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.274800098 |
|
|
Feb 09 02:24:24 PM UTC 25 |
Feb 09 02:24:27 PM UTC 25 |
114938897 ps |
| T889 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2440749862 |
|
|
Feb 09 02:24:18 PM UTC 25 |
Feb 09 02:24:27 PM UTC 25 |
519366780 ps |
| T890 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2742424793 |
|
|
Feb 09 02:24:25 PM UTC 25 |
Feb 09 02:24:28 PM UTC 25 |
23158102 ps |
| T208 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1013658171 |
|
|
Feb 09 02:24:25 PM UTC 25 |
Feb 09 02:24:28 PM UTC 25 |
339533370 ps |
| T891 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1706590881 |
|
|
Feb 09 02:23:57 PM UTC 25 |
Feb 09 02:24:28 PM UTC 25 |
968451234 ps |
| T892 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3156998889 |
|
|
Feb 09 02:24:24 PM UTC 25 |
Feb 09 02:24:29 PM UTC 25 |
63083328 ps |
| T893 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1705159476 |
|
|
Feb 09 02:24:25 PM UTC 25 |
Feb 09 02:24:29 PM UTC 25 |
424969626 ps |
| T894 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1003004608 |
|
|
Feb 09 02:24:37 PM UTC 25 |
Feb 09 02:24:41 PM UTC 25 |
222798560 ps |
| T895 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2228870202 |
|
|
Feb 09 02:24:26 PM UTC 25 |
Feb 09 02:24:30 PM UTC 25 |
117051753 ps |
| T209 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.895389091 |
|
|
Feb 09 02:24:28 PM UTC 25 |
Feb 09 02:24:31 PM UTC 25 |
29907280 ps |
| T896 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2720028446 |
|
|
Feb 09 02:24:09 PM UTC 25 |
Feb 09 02:24:32 PM UTC 25 |
2721539881 ps |
| T897 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.293547578 |
|
|
Feb 09 02:24:29 PM UTC 25 |
Feb 09 02:24:32 PM UTC 25 |
91107236 ps |
| T898 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2772865528 |
|
|
Feb 09 02:24:31 PM UTC 25 |
Feb 09 02:24:33 PM UTC 25 |
50127245 ps |
| T196 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3586501807 |
|
|
Feb 09 02:24:31 PM UTC 25 |
Feb 09 02:24:33 PM UTC 25 |
32607300 ps |
| T214 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1271841346 |
|
|
Feb 09 02:24:29 PM UTC 25 |
Feb 09 02:24:34 PM UTC 25 |
211476843 ps |
| T144 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2182302604 |
|
|
Feb 09 02:24:28 PM UTC 25 |
Feb 09 02:24:34 PM UTC 25 |
201923453 ps |
| T197 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3701419921 |
|
|
Feb 09 02:24:32 PM UTC 25 |
Feb 09 02:24:35 PM UTC 25 |
171745785 ps |
| T138 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.903506998 |
|
|
Feb 09 02:24:29 PM UTC 25 |
Feb 09 02:24:35 PM UTC 25 |
63028268 ps |
| T899 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1953789120 |
|
|
Feb 09 02:24:31 PM UTC 25 |
Feb 09 02:24:36 PM UTC 25 |
81776716 ps |
| T900 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1953895054 |
|
|
Feb 09 02:24:26 PM UTC 25 |
Feb 09 02:24:36 PM UTC 25 |
3553432803 ps |
| T210 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1829580752 |
|
|
Feb 09 02:24:33 PM UTC 25 |
Feb 09 02:24:36 PM UTC 25 |
34168124 ps |
| T134 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2518582641 |
|
|
Feb 09 02:24:33 PM UTC 25 |
Feb 09 02:24:37 PM UTC 25 |
31462013 ps |
| T901 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.702310768 |
|
|
Feb 09 02:24:34 PM UTC 25 |
Feb 09 02:24:37 PM UTC 25 |
34290049 ps |
| T902 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.659610846 |
|
|
Feb 09 02:24:18 PM UTC 25 |
Feb 09 02:24:40 PM UTC 25 |
3871842852 ps |
| T198 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2738686641 |
|
|
Feb 09 02:24:51 PM UTC 25 |
Feb 09 02:24:54 PM UTC 25 |
14697683 ps |
| T903 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4165753160 |
|
|
Feb 09 02:24:34 PM UTC 25 |
Feb 09 02:24:39 PM UTC 25 |
317337488 ps |
| T904 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3422836693 |
|
|
Feb 09 02:24:36 PM UTC 25 |
Feb 09 02:24:39 PM UTC 25 |
40476353 ps |
| T905 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4194786825 |
|
|
Feb 09 02:24:38 PM UTC 25 |
Feb 09 02:24:41 PM UTC 25 |
45752817 ps |
| T906 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1596981558 |
|
|
Feb 09 02:24:38 PM UTC 25 |
Feb 09 02:24:41 PM UTC 25 |
15905961 ps |
| T907 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2572522308 |
|
|
Feb 09 02:24:35 PM UTC 25 |
Feb 09 02:24:42 PM UTC 25 |
192482028 ps |
| T145 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.239400908 |
|
|
Feb 09 02:24:37 PM UTC 25 |
Feb 09 02:24:42 PM UTC 25 |
239033008 ps |
| T137 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3093930449 |
|
|
Feb 09 02:24:37 PM UTC 25 |
Feb 09 02:24:42 PM UTC 25 |
403345753 ps |
| T908 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1167591210 |
|
|
Feb 09 02:24:36 PM UTC 25 |
Feb 09 02:24:43 PM UTC 25 |
133558246 ps |
| T909 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1676918343 |
|
|
Feb 09 02:24:41 PM UTC 25 |
Feb 09 02:24:43 PM UTC 25 |
73341480 ps |
| T910 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2219442194 |
|
|
Feb 09 02:24:41 PM UTC 25 |
Feb 09 02:24:43 PM UTC 25 |
48612733 ps |
| T911 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.112550941 |
|
|
Feb 09 02:24:28 PM UTC 25 |
Feb 09 02:24:44 PM UTC 25 |
1707036416 ps |
| T912 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1446535925 |
|
|
Feb 09 02:24:39 PM UTC 25 |
Feb 09 02:24:44 PM UTC 25 |
66029363 ps |
| T147 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.288096210 |
|
|
Feb 09 02:24:41 PM UTC 25 |
Feb 09 02:24:44 PM UTC 25 |
21813609 ps |
| T913 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1295930171 |
|
|
Feb 09 02:24:45 PM UTC 25 |
Feb 09 02:24:48 PM UTC 25 |
14095664 ps |
| T914 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3820753671 |
|
|
Feb 09 02:24:42 PM UTC 25 |
Feb 09 02:24:45 PM UTC 25 |
44263744 ps |
| T915 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2105327237 |
|
|
Feb 09 02:24:42 PM UTC 25 |
Feb 09 02:24:46 PM UTC 25 |
113075037 ps |
| T916 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3402429682 |
|
|
Feb 09 02:24:44 PM UTC 25 |
Feb 09 02:24:47 PM UTC 25 |
134743241 ps |
| T917 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.318491299 |
|
|
Feb 09 02:24:45 PM UTC 25 |
Feb 09 02:24:48 PM UTC 25 |
19915066 ps |
| T918 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3242358214 |
|
|
Feb 09 02:24:44 PM UTC 25 |
Feb 09 02:24:49 PM UTC 25 |
554564686 ps |
| T919 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1155200065 |
|
|
Feb 09 02:24:44 PM UTC 25 |
Feb 09 02:24:49 PM UTC 25 |
359663412 ps |
| T920 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.553347922 |
|
|
Feb 09 02:24:45 PM UTC 25 |
Feb 09 02:24:49 PM UTC 25 |
123431799 ps |
| T149 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3115456205 |
|
|
Feb 09 02:24:45 PM UTC 25 |
Feb 09 02:24:50 PM UTC 25 |
241524034 ps |
| T921 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1601705980 |
|
|
Feb 09 02:24:34 PM UTC 25 |
Feb 09 02:24:50 PM UTC 25 |
419431240 ps |
| T922 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3167218720 |
|
|
Feb 09 02:24:45 PM UTC 25 |
Feb 09 02:24:51 PM UTC 25 |
122384894 ps |
| T923 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.563309725 |
|
|
Feb 09 02:25:16 PM UTC 25 |
Feb 09 02:25:21 PM UTC 25 |
1536547482 ps |
| T924 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2736564099 |
|
|
Feb 09 02:24:49 PM UTC 25 |
Feb 09 02:24:52 PM UTC 25 |
169928445 ps |
| T925 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2723179470 |
|
|
Feb 09 02:24:50 PM UTC 25 |
Feb 09 02:24:53 PM UTC 25 |
178388585 ps |
| T926 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2313919786 |
|
|
Feb 09 02:24:47 PM UTC 25 |
Feb 09 02:24:53 PM UTC 25 |
292215908 ps |
| T927 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.800524111 |
|
|
Feb 09 02:24:45 PM UTC 25 |
Feb 09 02:24:53 PM UTC 25 |
263840800 ps |
| T153 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3506033880 |
|
|
Feb 09 02:24:50 PM UTC 25 |
Feb 09 02:24:54 PM UTC 25 |
448899702 ps |
| T928 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2617334092 |
|
|
Feb 09 02:24:51 PM UTC 25 |
Feb 09 02:24:54 PM UTC 25 |
26928503 ps |
| T929 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2206492037 |
|
|
Feb 09 02:24:51 PM UTC 25 |
Feb 09 02:24:54 PM UTC 25 |
23861212 ps |
| T930 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.409837365 |
|
|
Feb 09 02:24:44 PM UTC 25 |
Feb 09 02:24:55 PM UTC 25 |
5757704840 ps |
| T148 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2675349674 |
|
|
Feb 09 02:24:50 PM UTC 25 |
Feb 09 02:24:55 PM UTC 25 |
167916816 ps |
| T931 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.918646907 |
|
|
Feb 09 02:24:53 PM UTC 25 |
Feb 09 02:24:55 PM UTC 25 |
60615055 ps |
| T932 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2520119400 |
|
|
Feb 09 02:24:49 PM UTC 25 |
Feb 09 02:24:56 PM UTC 25 |
723855780 ps |
| T933 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.179640719 |
|
|
Feb 09 02:24:54 PM UTC 25 |
Feb 09 02:24:57 PM UTC 25 |
235125401 ps |
| T934 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.65086558 |
|
|
Feb 09 02:24:48 PM UTC 25 |
Feb 09 02:24:57 PM UTC 25 |
704797229 ps |
| T935 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2103558581 |
|
|
Feb 09 02:24:55 PM UTC 25 |
Feb 09 02:24:58 PM UTC 25 |
93076968 ps |
| T936 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.441718542 |
|
|
Feb 09 02:24:55 PM UTC 25 |
Feb 09 02:24:58 PM UTC 25 |
111443471 ps |
| T937 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3586790943 |
|
|
Feb 09 02:24:57 PM UTC 25 |
Feb 09 02:24:59 PM UTC 25 |
31597852 ps |
| T938 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2832585782 |
|
|
Feb 09 02:24:57 PM UTC 25 |
Feb 09 02:25:00 PM UTC 25 |
110032096 ps |
| T939 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2662269522 |
|
|
Feb 09 02:24:55 PM UTC 25 |
Feb 09 02:25:00 PM UTC 25 |
84808925 ps |
| T940 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.4185154657 |
|
|
Feb 09 02:24:58 PM UTC 25 |
Feb 09 02:25:00 PM UTC 25 |
53043884 ps |
| T941 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2263091206 |
|
|
Feb 09 02:24:58 PM UTC 25 |
Feb 09 02:25:01 PM UTC 25 |
775807404 ps |
| T140 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3266167574 |
|
|
Feb 09 02:24:56 PM UTC 25 |
Feb 09 02:25:01 PM UTC 25 |
247113059 ps |
| T942 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2430419068 |
|
|
Feb 09 02:24:59 PM UTC 25 |
Feb 09 02:25:02 PM UTC 25 |
64826567 ps |
| T943 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.772492653 |
|
|
Feb 09 02:24:55 PM UTC 25 |
Feb 09 02:25:03 PM UTC 25 |
130402120 ps |
| T944 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3867502143 |
|
|
Feb 09 02:25:00 PM UTC 25 |
Feb 09 02:25:03 PM UTC 25 |
27139211 ps |
| T945 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2767405429 |
|
|
Feb 09 02:24:47 PM UTC 25 |
Feb 09 02:25:04 PM UTC 25 |
2438230176 ps |
| T946 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3988657034 |
|
|
Feb 09 02:25:02 PM UTC 25 |
Feb 09 02:25:05 PM UTC 25 |
66210632 ps |
| T947 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1211576366 |
|
|
Feb 09 02:25:01 PM UTC 25 |
Feb 09 02:25:05 PM UTC 25 |
59216547 ps |
| T948 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1600362212 |
|
|
Feb 09 02:24:54 PM UTC 25 |
Feb 09 02:25:05 PM UTC 25 |
3677865755 ps |
| T949 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.465063395 |
|
|
Feb 09 02:25:03 PM UTC 25 |
Feb 09 02:25:05 PM UTC 25 |
14313186 ps |
| T143 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1412723551 |
|
|
Feb 09 02:25:02 PM UTC 25 |
Feb 09 02:25:05 PM UTC 25 |
61497877 ps |
| T950 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2396294139 |
|
|
Feb 09 02:25:03 PM UTC 25 |
Feb 09 02:25:06 PM UTC 25 |
273997043 ps |
| T951 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.200533413 |
|
|
Feb 09 02:25:04 PM UTC 25 |
Feb 09 02:25:08 PM UTC 25 |
49955466 ps |
| T952 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1427353625 |
|
|
Feb 09 02:25:05 PM UTC 25 |
Feb 09 02:25:08 PM UTC 25 |
155125838 ps |
| T953 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1746696947 |
|
|
Feb 09 02:25:04 PM UTC 25 |
Feb 09 02:25:08 PM UTC 25 |
365870113 ps |
| T954 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2972542500 |
|
|
Feb 09 02:25:00 PM UTC 25 |
Feb 09 02:25:09 PM UTC 25 |
967833351 ps |
| T955 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3701571109 |
|
|
Feb 09 02:25:07 PM UTC 25 |
Feb 09 02:25:09 PM UTC 25 |
27411291 ps |
| T956 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1881976144 |
|
|
Feb 09 02:25:07 PM UTC 25 |
Feb 09 02:25:10 PM UTC 25 |
105815591 ps |
| T957 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3584933490 |
|
|
Feb 09 02:25:07 PM UTC 25 |
Feb 09 02:25:11 PM UTC 25 |
77515297 ps |
| T199 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2275197107 |
|
|
Feb 09 02:25:09 PM UTC 25 |
Feb 09 02:25:11 PM UTC 25 |
39175808 ps |
| T958 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1162966450 |
|
|
Feb 09 02:24:42 PM UTC 25 |
Feb 09 02:25:12 PM UTC 25 |
5913528664 ps |
| T959 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3783958369 |
|
|
Feb 09 02:25:09 PM UTC 25 |
Feb 09 02:25:13 PM UTC 25 |
268872729 ps |
| T960 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3389065540 |
|
|
Feb 09 02:25:07 PM UTC 25 |
Feb 09 02:25:13 PM UTC 25 |
406737980 ps |
| T961 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3173635883 |
|
|
Feb 09 02:24:59 PM UTC 25 |
Feb 09 02:25:13 PM UTC 25 |
6148227025 ps |
| T962 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.675740187 |
|
|
Feb 09 02:25:10 PM UTC 25 |
Feb 09 02:25:13 PM UTC 25 |
62594872 ps |
| T963 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3138939399 |
|
|
Feb 09 02:24:54 PM UTC 25 |
Feb 09 02:25:14 PM UTC 25 |
1251250358 ps |
| T146 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3465095533 |
|
|
Feb 09 02:25:09 PM UTC 25 |
Feb 09 02:25:14 PM UTC 25 |
482361402 ps |
| T964 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3677673378 |
|
|
Feb 09 02:25:07 PM UTC 25 |
Feb 09 02:25:14 PM UTC 25 |
946633836 ps |
| T965 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.856506451 |
|
|
Feb 09 02:25:12 PM UTC 25 |
Feb 09 02:25:14 PM UTC 25 |
57771214 ps |
| T151 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.713989662 |
|
|
Feb 09 02:25:10 PM UTC 25 |
Feb 09 02:25:15 PM UTC 25 |
67470524 ps |
| T966 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1259892456 |
|
|
Feb 09 02:25:10 PM UTC 25 |
Feb 09 02:25:15 PM UTC 25 |
73487934 ps |
| T967 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3698488507 |
|
|
Feb 09 02:25:12 PM UTC 25 |
Feb 09 02:25:15 PM UTC 25 |
72028881 ps |
| T968 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1319590466 |
|
|
Feb 09 02:25:12 PM UTC 25 |
Feb 09 02:25:15 PM UTC 25 |
44587144 ps |
| T969 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3828190274 |
|
|
Feb 09 02:25:13 PM UTC 25 |
Feb 09 02:25:15 PM UTC 25 |
18440046 ps |
| T970 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3198922947 |
|
|
Feb 09 02:24:59 PM UTC 25 |
Feb 09 02:25:16 PM UTC 25 |
1609858305 ps |
| T971 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2094290813 |
|
|
Feb 09 02:25:14 PM UTC 25 |
Feb 09 02:25:17 PM UTC 25 |
15268764 ps |
| T972 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.658086434 |
|
|
Feb 09 02:25:14 PM UTC 25 |
Feb 09 02:25:17 PM UTC 25 |
12884850 ps |
| T973 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2215364334 |
|
|
Feb 09 02:25:15 PM UTC 25 |
Feb 09 02:25:18 PM UTC 25 |
111742737 ps |
| T141 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3034333328 |
|
|
Feb 09 02:25:13 PM UTC 25 |
Feb 09 02:25:18 PM UTC 25 |
150197308 ps |
| T200 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.35645841 |
|
|
Feb 09 02:25:16 PM UTC 25 |
Feb 09 02:25:19 PM UTC 25 |
29273845 ps |
| T974 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3203285817 |
|
|
Feb 09 02:25:16 PM UTC 25 |
Feb 09 02:25:19 PM UTC 25 |
13712187 ps |
| T975 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2830049007 |
|
|
Feb 09 02:25:16 PM UTC 25 |
Feb 09 02:25:19 PM UTC 25 |
58658898 ps |
| T976 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.417152577 |
|
|
Feb 09 02:25:16 PM UTC 25 |
Feb 09 02:25:19 PM UTC 25 |
45715534 ps |
| T977 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3144886543 |
|
|
Feb 09 02:25:16 PM UTC 25 |
Feb 09 02:25:20 PM UTC 25 |
50174455 ps |
| T978 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1384856694 |
|
|
Feb 09 02:25:13 PM UTC 25 |
Feb 09 02:25:20 PM UTC 25 |
304300513 ps |
| T979 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2283542546 |
|
|
Feb 09 02:25:17 PM UTC 25 |
Feb 09 02:25:21 PM UTC 25 |
31771149 ps |
| T133 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3750791772 |
|
|
Feb 09 02:25:16 PM UTC 25 |
Feb 09 02:25:21 PM UTC 25 |
164185024 ps |
| T152 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2113206327 |
|
|
Feb 09 02:25:16 PM UTC 25 |
Feb 09 02:25:22 PM UTC 25 |
171858146 ps |
| T980 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.168630325 |
|
|
Feb 09 02:25:17 PM UTC 25 |
Feb 09 02:25:23 PM UTC 25 |
239234460 ps |
| T201 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1361272889 |
|
|
Feb 09 02:25:20 PM UTC 25 |
Feb 09 02:25:23 PM UTC 25 |
14348691 ps |
| T202 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3737473734 |
|
|
Feb 09 02:25:21 PM UTC 25 |
Feb 09 02:25:23 PM UTC 25 |
47515637 ps |
| T981 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3651663906 |
|
|
Feb 09 02:25:20 PM UTC 25 |
Feb 09 02:25:23 PM UTC 25 |
59380813 ps |
| T982 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2091879305 |
|
|
Feb 09 02:25:20 PM UTC 25 |
Feb 09 02:25:23 PM UTC 25 |
72159848 ps |
| T983 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.4141936455 |
|
|
Feb 09 02:25:21 PM UTC 25 |
Feb 09 02:25:23 PM UTC 25 |
95749004 ps |
| T984 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3424626663 |
|
|
Feb 09 02:25:21 PM UTC 25 |
Feb 09 02:25:24 PM UTC 25 |
86351427 ps |
| T985 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.76634284 |
|
|
Feb 09 02:25:20 PM UTC 25 |
Feb 09 02:25:24 PM UTC 25 |
73513933 ps |
| T986 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.365186379 |
|
|
Feb 09 02:25:22 PM UTC 25 |
Feb 09 02:25:24 PM UTC 25 |
11059067 ps |
| T987 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1767726169 |
|
|
Feb 09 02:25:22 PM UTC 25 |
Feb 09 02:25:25 PM UTC 25 |
34920468 ps |
| T150 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3151247100 |
|
|
Feb 09 02:25:20 PM UTC 25 |
Feb 09 02:25:26 PM UTC 25 |
187456276 ps |
| T988 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4269584338 |
|
|
Feb 09 02:25:22 PM UTC 25 |
Feb 09 02:25:26 PM UTC 25 |
24624227 ps |
| T989 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.166333225 |
|
|
Feb 09 02:25:23 PM UTC 25 |
Feb 09 02:25:26 PM UTC 25 |
95072063 ps |
| T142 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1892059558 |
|
|
Feb 09 02:25:21 PM UTC 25 |
Feb 09 02:25:26 PM UTC 25 |
412521940 ps |
| T154 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1859825476 |
|
|
Feb 09 02:25:22 PM UTC 25 |
Feb 09 02:25:27 PM UTC 25 |
314358204 ps |
| T990 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2006919445 |
|
|
Feb 09 02:25:25 PM UTC 25 |
Feb 09 02:25:27 PM UTC 25 |
11521991 ps |
| T991 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.55444451 |
|
|
Feb 09 02:25:25 PM UTC 25 |
Feb 09 02:25:27 PM UTC 25 |
43257992 ps |
| T992 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1654829416 |
|
|
Feb 09 02:25:25 PM UTC 25 |
Feb 09 02:25:28 PM UTC 25 |
278133417 ps |
| T993 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2053202647 |
|
|
Feb 09 02:25:25 PM UTC 25 |
Feb 09 02:25:28 PM UTC 25 |
63013634 ps |
| T994 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.976804401 |
|
|
Feb 09 02:25:26 PM UTC 25 |
Feb 09 02:25:28 PM UTC 25 |
17354925 ps |
| T995 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3781123910 |
|
|
Feb 09 02:25:23 PM UTC 25 |
Feb 09 02:25:29 PM UTC 25 |
1289226305 ps |
| T996 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1553226491 |
|
|
Feb 09 02:25:26 PM UTC 25 |
Feb 09 02:25:29 PM UTC 25 |
25251679 ps |
| T997 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2741910736 |
|
|
Feb 09 02:25:25 PM UTC 25 |
Feb 09 02:25:29 PM UTC 25 |
54817570 ps |
| T998 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1951007096 |
|
|
Feb 09 02:25:26 PM UTC 25 |
Feb 09 02:25:29 PM UTC 25 |
34198426 ps |
| T999 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2742981257 |
|
|
Feb 09 02:25:25 PM UTC 25 |
Feb 09 02:25:29 PM UTC 25 |
330383538 ps |
| T1000 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3759781696 |
|
|
Feb 09 02:25:28 PM UTC 25 |
Feb 09 02:25:31 PM UTC 25 |
61641182 ps |
| T1001 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2313756010 |
|
|
Feb 09 02:25:28 PM UTC 25 |
Feb 09 02:25:31 PM UTC 25 |
17435415 ps |