| T588 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.608759056 |
|
|
Oct 15 04:41:36 AM UTC 24 |
Oct 15 04:41:52 AM UTC 24 |
775190202 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.2764050869 |
|
|
Oct 15 04:41:37 AM UTC 24 |
Oct 15 04:41:53 AM UTC 24 |
1132991948 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.4234064917 |
|
|
Oct 15 04:41:36 AM UTC 24 |
Oct 15 04:41:53 AM UTC 24 |
1252123507 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.2933154903 |
|
|
Oct 15 04:41:19 AM UTC 24 |
Oct 15 04:41:54 AM UTC 24 |
1190420879 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.1163811054 |
|
|
Oct 15 04:41:52 AM UTC 24 |
Oct 15 04:41:57 AM UTC 24 |
1015194404 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2322538363 |
|
|
Oct 15 04:40:21 AM UTC 24 |
Oct 15 04:41:57 AM UTC 24 |
2842390949 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.2151323644 |
|
|
Oct 15 04:41:40 AM UTC 24 |
Oct 15 04:41:58 AM UTC 24 |
274988358 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.143770305 |
|
|
Oct 15 04:41:46 AM UTC 24 |
Oct 15 04:41:58 AM UTC 24 |
111128643 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.3356870826 |
|
|
Oct 15 04:41:38 AM UTC 24 |
Oct 15 04:41:59 AM UTC 24 |
1135661882 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.2345125373 |
|
|
Oct 15 04:41:50 AM UTC 24 |
Oct 15 04:41:59 AM UTC 24 |
1436327936 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1421298000 |
|
|
Oct 15 04:41:59 AM UTC 24 |
Oct 15 04:42:01 AM UTC 24 |
46546966 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.3747678695 |
|
|
Oct 15 04:41:59 AM UTC 24 |
Oct 15 04:42:02 AM UTC 24 |
49633423 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.2094363973 |
|
|
Oct 15 04:41:59 AM UTC 24 |
Oct 15 04:42:04 AM UTC 24 |
106039783 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.2885594771 |
|
|
Oct 15 04:39:45 AM UTC 24 |
Oct 15 04:42:04 AM UTC 24 |
15306161876 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.3098556955 |
|
|
Oct 15 04:41:34 AM UTC 24 |
Oct 15 04:42:06 AM UTC 24 |
732314987 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.697601447 |
|
|
Oct 15 04:42:00 AM UTC 24 |
Oct 15 04:42:08 AM UTC 24 |
681962358 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.2627346421 |
|
|
Oct 15 04:41:54 AM UTC 24 |
Oct 15 04:42:08 AM UTC 24 |
1776169182 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.427440138 |
|
|
Oct 15 04:41:53 AM UTC 24 |
Oct 15 04:42:11 AM UTC 24 |
334935571 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_errors.2335553462 |
|
|
Oct 15 04:41:49 AM UTC 24 |
Oct 15 04:42:13 AM UTC 24 |
367310799 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.2631871163 |
|
|
Oct 15 04:42:33 AM UTC 24 |
Oct 15 04:42:47 AM UTC 24 |
732205931 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.1785516187 |
|
|
Oct 15 04:42:03 AM UTC 24 |
Oct 15 04:42:13 AM UTC 24 |
219349529 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.1438433941 |
|
|
Oct 15 04:42:12 AM UTC 24 |
Oct 15 04:42:14 AM UTC 24 |
17345198 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.3544774553 |
|
|
Oct 15 04:42:00 AM UTC 24 |
Oct 15 04:42:14 AM UTC 24 |
86157632 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.4191315183 |
|
|
Oct 15 04:42:14 AM UTC 24 |
Oct 15 04:42:16 AM UTC 24 |
22275072 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.3985763618 |
|
|
Oct 15 04:42:05 AM UTC 24 |
Oct 15 04:42:16 AM UTC 24 |
273169059 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.64635149 |
|
|
Oct 15 04:42:06 AM UTC 24 |
Oct 15 04:42:17 AM UTC 24 |
717020588 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.46920474 |
|
|
Oct 15 04:41:45 AM UTC 24 |
Oct 15 04:42:17 AM UTC 24 |
2874154429 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.2574071117 |
|
|
Oct 15 04:41:54 AM UTC 24 |
Oct 15 04:42:19 AM UTC 24 |
786559870 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.1080016576 |
|
|
Oct 15 04:42:15 AM UTC 24 |
Oct 15 04:42:20 AM UTC 24 |
40476032 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.1695866315 |
|
|
Oct 15 04:42:15 AM UTC 24 |
Oct 15 04:42:20 AM UTC 24 |
176959526 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.256634393 |
|
|
Oct 15 04:42:13 AM UTC 24 |
Oct 15 04:42:21 AM UTC 24 |
381305800 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.1862397502 |
|
|
Oct 15 04:40:29 AM UTC 24 |
Oct 15 04:42:21 AM UTC 24 |
4244808821 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.3966096441 |
|
|
Oct 15 04:42:07 AM UTC 24 |
Oct 15 04:42:24 AM UTC 24 |
712591523 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.473796553 |
|
|
Oct 15 04:42:17 AM UTC 24 |
Oct 15 04:42:25 AM UTC 24 |
1610904150 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.394151436 |
|
|
Oct 15 04:42:23 AM UTC 24 |
Oct 15 04:42:25 AM UTC 24 |
42190089 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.481204655 |
|
|
Oct 15 04:42:23 AM UTC 24 |
Oct 15 04:42:25 AM UTC 24 |
29547581 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.1460441510 |
|
|
Oct 15 04:42:17 AM UTC 24 |
Oct 15 04:42:26 AM UTC 24 |
725504664 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.116038128 |
|
|
Oct 15 04:42:09 AM UTC 24 |
Oct 15 04:42:26 AM UTC 24 |
728285901 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2266069750 |
|
|
Oct 15 04:42:25 AM UTC 24 |
Oct 15 04:42:27 AM UTC 24 |
20589834 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.3303245025 |
|
|
Oct 15 04:42:20 AM UTC 24 |
Oct 15 04:42:30 AM UTC 24 |
461950572 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.583386058 |
|
|
Oct 15 04:42:26 AM UTC 24 |
Oct 15 04:42:32 AM UTC 24 |
202627291 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.3588878031 |
|
|
Oct 15 04:42:21 AM UTC 24 |
Oct 15 04:42:34 AM UTC 24 |
820002263 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_errors.1554151961 |
|
|
Oct 15 04:42:02 AM UTC 24 |
Oct 15 04:42:35 AM UTC 24 |
1258554831 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.2821295767 |
|
|
Oct 15 04:40:43 AM UTC 24 |
Oct 15 04:42:36 AM UTC 24 |
3274992558 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.1051148621 |
|
|
Oct 15 04:42:19 AM UTC 24 |
Oct 15 04:42:37 AM UTC 24 |
1089152068 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.977618205 |
|
|
Oct 15 04:42:26 AM UTC 24 |
Oct 15 04:42:38 AM UTC 24 |
240042876 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.3576646907 |
|
|
Oct 15 04:41:59 AM UTC 24 |
Oct 15 04:42:38 AM UTC 24 |
490695036 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.3463215248 |
|
|
Oct 15 04:42:27 AM UTC 24 |
Oct 15 04:42:39 AM UTC 24 |
301756857 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.429333232 |
|
|
Oct 15 04:42:37 AM UTC 24 |
Oct 15 04:42:40 AM UTC 24 |
63839696 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.577450474 |
|
|
Oct 15 04:42:39 AM UTC 24 |
Oct 15 04:42:41 AM UTC 24 |
13674174 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_errors.2356373108 |
|
|
Oct 15 04:42:17 AM UTC 24 |
Oct 15 04:42:42 AM UTC 24 |
2198854721 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.3895242326 |
|
|
Oct 15 04:42:27 AM UTC 24 |
Oct 15 04:42:43 AM UTC 24 |
1500238176 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.1874340857 |
|
|
Oct 15 04:42:41 AM UTC 24 |
Oct 15 04:42:47 AM UTC 24 |
61810666 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.315580031 |
|
|
Oct 15 04:42:38 AM UTC 24 |
Oct 15 04:42:43 AM UTC 24 |
76378917 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.2504173044 |
|
|
Oct 15 04:41:15 AM UTC 24 |
Oct 15 04:42:44 AM UTC 24 |
2553277918 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.2692208519 |
|
|
Oct 15 04:42:32 AM UTC 24 |
Oct 15 04:42:46 AM UTC 24 |
257413862 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.951811496 |
|
|
Oct 15 04:42:42 AM UTC 24 |
Oct 15 04:42:46 AM UTC 24 |
587080684 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.1996820021 |
|
|
Oct 15 04:42:14 AM UTC 24 |
Oct 15 04:42:47 AM UTC 24 |
1405548228 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.3929668079 |
|
|
Oct 15 04:42:26 AM UTC 24 |
Oct 15 04:42:48 AM UTC 24 |
955654959 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.3203601760 |
|
|
Oct 15 04:42:44 AM UTC 24 |
Oct 15 04:42:50 AM UTC 24 |
644209406 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.2106119426 |
|
|
Oct 15 04:43:42 AM UTC 24 |
Oct 15 04:43:44 AM UTC 24 |
16048880 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.523703329 |
|
|
Oct 15 04:43:36 AM UTC 24 |
Oct 15 04:43:46 AM UTC 24 |
60930547 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1255769251 |
|
|
Oct 15 04:42:48 AM UTC 24 |
Oct 15 04:42:51 AM UTC 24 |
48152355 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.4067301030 |
|
|
Oct 15 04:42:48 AM UTC 24 |
Oct 15 04:42:51 AM UTC 24 |
26078714 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.1292453493 |
|
|
Oct 15 04:42:48 AM UTC 24 |
Oct 15 04:42:52 AM UTC 24 |
57350207 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.4126605439 |
|
|
Oct 15 04:38:52 AM UTC 24 |
Oct 15 04:42:52 AM UTC 24 |
7355751655 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.704043372 |
|
|
Oct 15 04:42:35 AM UTC 24 |
Oct 15 04:42:53 AM UTC 24 |
501993784 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.200285245 |
|
|
Oct 15 04:42:50 AM UTC 24 |
Oct 15 04:42:54 AM UTC 24 |
425838616 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.436984327 |
|
|
Oct 15 04:42:51 AM UTC 24 |
Oct 15 04:42:54 AM UTC 24 |
111911118 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.415484995 |
|
|
Oct 15 04:41:40 AM UTC 24 |
Oct 15 04:42:55 AM UTC 24 |
9218016631 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.86573029 |
|
|
Oct 15 04:42:43 AM UTC 24 |
Oct 15 04:42:55 AM UTC 24 |
1027379875 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.3828740414 |
|
|
Oct 15 04:42:46 AM UTC 24 |
Oct 15 04:42:57 AM UTC 24 |
537470743 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.120249088 |
|
|
Oct 15 04:42:44 AM UTC 24 |
Oct 15 04:42:57 AM UTC 24 |
295605808 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.458990924 |
|
|
Oct 15 04:42:56 AM UTC 24 |
Oct 15 04:42:59 AM UTC 24 |
14060686 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.457828686 |
|
|
Oct 15 04:42:56 AM UTC 24 |
Oct 15 04:43:00 AM UTC 24 |
336641566 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.2009272094 |
|
|
Oct 15 04:42:44 AM UTC 24 |
Oct 15 04:43:01 AM UTC 24 |
1455751221 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3054070439 |
|
|
Oct 15 04:42:59 AM UTC 24 |
Oct 15 04:43:01 AM UTC 24 |
19409719 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.980141879 |
|
|
Oct 15 04:42:52 AM UTC 24 |
Oct 15 04:43:02 AM UTC 24 |
392108931 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.2330200992 |
|
|
Oct 15 04:39:36 AM UTC 24 |
Oct 15 04:43:02 AM UTC 24 |
44994598492 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2140079238 |
|
|
Oct 15 04:40:43 AM UTC 24 |
Oct 15 04:43:02 AM UTC 24 |
2951219373 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.705570018 |
|
|
Oct 15 04:42:44 AM UTC 24 |
Oct 15 04:43:03 AM UTC 24 |
725743371 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.2806733549 |
|
|
Oct 15 04:42:55 AM UTC 24 |
Oct 15 04:43:06 AM UTC 24 |
193968538 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.1795629863 |
|
|
Oct 15 04:43:01 AM UTC 24 |
Oct 15 04:43:06 AM UTC 24 |
300179136 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_errors.1555367378 |
|
|
Oct 15 04:42:51 AM UTC 24 |
Oct 15 04:43:06 AM UTC 24 |
3379686475 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.3375788590 |
|
|
Oct 15 04:42:52 AM UTC 24 |
Oct 15 04:43:06 AM UTC 24 |
1610232245 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.2621759121 |
|
|
Oct 15 04:42:54 AM UTC 24 |
Oct 15 04:43:07 AM UTC 24 |
565473708 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.925108966 |
|
|
Oct 15 04:43:07 AM UTC 24 |
Oct 15 04:43:09 AM UTC 24 |
72926984 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.986891969 |
|
|
Oct 15 04:43:00 AM UTC 24 |
Oct 15 04:43:11 AM UTC 24 |
638390470 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2537913796 |
|
|
Oct 15 04:43:08 AM UTC 24 |
Oct 15 04:43:11 AM UTC 24 |
14378095 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.2021521597 |
|
|
Oct 15 04:42:52 AM UTC 24 |
Oct 15 04:43:11 AM UTC 24 |
435244142 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.4067788039 |
|
|
Oct 15 04:42:41 AM UTC 24 |
Oct 15 04:43:12 AM UTC 24 |
4971898795 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.1315157021 |
|
|
Oct 15 04:43:09 AM UTC 24 |
Oct 15 04:43:12 AM UTC 24 |
154729271 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.2099257832 |
|
|
Oct 15 04:43:08 AM UTC 24 |
Oct 15 04:43:13 AM UTC 24 |
299245165 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.1286065771 |
|
|
Oct 15 04:43:02 AM UTC 24 |
Oct 15 04:43:14 AM UTC 24 |
1073432971 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.580849402 |
|
|
Oct 15 04:43:04 AM UTC 24 |
Oct 15 04:43:14 AM UTC 24 |
1047957487 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.119517773 |
|
|
Oct 15 04:42:49 AM UTC 24 |
Oct 15 04:43:14 AM UTC 24 |
735120597 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.2897976063 |
|
|
Oct 15 04:43:04 AM UTC 24 |
Oct 15 04:43:15 AM UTC 24 |
221278125 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_errors.932479316 |
|
|
Oct 15 04:43:01 AM UTC 24 |
Oct 15 04:43:17 AM UTC 24 |
289955097 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.314836659 |
|
|
Oct 15 04:43:15 AM UTC 24 |
Oct 15 04:43:18 AM UTC 24 |
36495829 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.998437905 |
|
|
Oct 15 04:43:12 AM UTC 24 |
Oct 15 04:43:18 AM UTC 24 |
199138360 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1866656882 |
|
|
Oct 15 04:43:17 AM UTC 24 |
Oct 15 04:43:20 AM UTC 24 |
15138275 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.2868067979 |
|
|
Oct 15 04:43:08 AM UTC 24 |
Oct 15 04:43:20 AM UTC 24 |
78702898 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.651643550 |
|
|
Oct 15 04:43:02 AM UTC 24 |
Oct 15 04:43:20 AM UTC 24 |
560195939 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.3949617384 |
|
|
Oct 15 04:43:04 AM UTC 24 |
Oct 15 04:43:21 AM UTC 24 |
5413421721 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.1581818325 |
|
|
Oct 15 04:43:15 AM UTC 24 |
Oct 15 04:43:21 AM UTC 24 |
86278659 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.2454228938 |
|
|
Oct 15 04:43:19 AM UTC 24 |
Oct 15 04:43:22 AM UTC 24 |
199181484 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.1790154858 |
|
|
Oct 15 04:43:12 AM UTC 24 |
Oct 15 04:43:22 AM UTC 24 |
791619098 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.1564815261 |
|
|
Oct 15 04:41:03 AM UTC 24 |
Oct 15 04:46:56 AM UTC 24 |
18733947834 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.1153293335 |
|
|
Oct 15 04:43:13 AM UTC 24 |
Oct 15 04:43:23 AM UTC 24 |
172861479 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.4225325525 |
|
|
Oct 15 04:43:17 AM UTC 24 |
Oct 15 04:43:23 AM UTC 24 |
1712830694 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.1002494667 |
|
|
Oct 15 04:43:17 AM UTC 24 |
Oct 15 04:43:25 AM UTC 24 |
92988602 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.3762489940 |
|
|
Oct 15 04:43:13 AM UTC 24 |
Oct 15 04:43:26 AM UTC 24 |
1102718565 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.3665686858 |
|
|
Oct 15 04:43:12 AM UTC 24 |
Oct 15 04:43:26 AM UTC 24 |
1248807358 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.971958862 |
|
|
Oct 15 04:43:23 AM UTC 24 |
Oct 15 04:43:27 AM UTC 24 |
20050222 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.633446774 |
|
|
Oct 15 04:43:24 AM UTC 24 |
Oct 15 04:43:27 AM UTC 24 |
23823450 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.3149496623 |
|
|
Oct 15 04:43:10 AM UTC 24 |
Oct 15 04:43:29 AM UTC 24 |
4612046062 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.300217607 |
|
|
Oct 15 04:43:23 AM UTC 24 |
Oct 15 04:43:29 AM UTC 24 |
158692920 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.528539744 |
|
|
Oct 15 04:42:59 AM UTC 24 |
Oct 15 04:43:30 AM UTC 24 |
244763127 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.1614356876 |
|
|
Oct 15 04:43:27 AM UTC 24 |
Oct 15 04:43:31 AM UTC 24 |
98544177 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.663122388 |
|
|
Oct 15 04:43:21 AM UTC 24 |
Oct 15 04:43:31 AM UTC 24 |
714274167 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.2653865978 |
|
|
Oct 15 04:43:08 AM UTC 24 |
Oct 15 04:43:31 AM UTC 24 |
1026038136 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.556475554 |
|
|
Oct 15 04:43:19 AM UTC 24 |
Oct 15 04:43:32 AM UTC 24 |
370998851 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.908007057 |
|
|
Oct 15 04:43:17 AM UTC 24 |
Oct 15 04:43:43 AM UTC 24 |
1080022503 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.3307946579 |
|
|
Oct 15 04:41:55 AM UTC 24 |
Oct 15 04:43:45 AM UTC 24 |
2666647599 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.1608164449 |
|
|
Oct 15 04:43:32 AM UTC 24 |
Oct 15 04:43:35 AM UTC 24 |
21036934 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.1651775085 |
|
|
Oct 15 04:43:28 AM UTC 24 |
Oct 15 04:43:35 AM UTC 24 |
496321624 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.3502525338 |
|
|
Oct 15 04:43:19 AM UTC 24 |
Oct 15 04:43:35 AM UTC 24 |
1309101583 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.367567104 |
|
|
Oct 15 04:43:33 AM UTC 24 |
Oct 15 04:43:36 AM UTC 24 |
17831572 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.1378113053 |
|
|
Oct 15 04:43:26 AM UTC 24 |
Oct 15 04:43:37 AM UTC 24 |
852448018 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1890168313 |
|
|
Oct 15 04:43:36 AM UTC 24 |
Oct 15 04:43:38 AM UTC 24 |
12120237 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.3527768940 |
|
|
Oct 15 04:43:36 AM UTC 24 |
Oct 15 04:43:40 AM UTC 24 |
80624485 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.1763811464 |
|
|
Oct 15 04:39:22 AM UTC 24 |
Oct 15 04:43:40 AM UTC 24 |
9201911082 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_errors.2525920825 |
|
|
Oct 15 04:43:27 AM UTC 24 |
Oct 15 04:43:41 AM UTC 24 |
894030341 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.845007178 |
|
|
Oct 15 04:43:28 AM UTC 24 |
Oct 15 04:43:41 AM UTC 24 |
1194978813 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.3261063336 |
|
|
Oct 15 04:43:21 AM UTC 24 |
Oct 15 04:43:42 AM UTC 24 |
2307153017 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.1528223538 |
|
|
Oct 15 04:43:21 AM UTC 24 |
Oct 15 04:43:42 AM UTC 24 |
1287011098 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.2854258474 |
|
|
Oct 15 04:43:31 AM UTC 24 |
Oct 15 04:43:45 AM UTC 24 |
1362971378 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.2103277838 |
|
|
Oct 15 04:43:22 AM UTC 24 |
Oct 15 04:47:04 AM UTC 24 |
12987056893 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1443441701 |
|
|
Oct 15 04:43:43 AM UTC 24 |
Oct 15 04:43:46 AM UTC 24 |
42072533 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.2375048780 |
|
|
Oct 15 04:43:43 AM UTC 24 |
Oct 15 04:43:46 AM UTC 24 |
42195038 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.322543134 |
|
|
Oct 15 04:43:31 AM UTC 24 |
Oct 15 04:43:48 AM UTC 24 |
550225495 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.1205796056 |
|
|
Oct 15 04:43:29 AM UTC 24 |
Oct 15 04:43:48 AM UTC 24 |
348348828 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.3864559581 |
|
|
Oct 15 04:44:25 AM UTC 24 |
Oct 15 04:44:39 AM UTC 24 |
549296189 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_errors.3750651460 |
|
|
Oct 15 04:43:37 AM UTC 24 |
Oct 15 04:43:48 AM UTC 24 |
227792884 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.4137498416 |
|
|
Oct 15 04:42:21 AM UTC 24 |
Oct 15 04:43:49 AM UTC 24 |
4946161355 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.3233773809 |
|
|
Oct 15 04:43:46 AM UTC 24 |
Oct 15 04:43:49 AM UTC 24 |
36779735 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.2322582604 |
|
|
Oct 15 04:43:37 AM UTC 24 |
Oct 15 04:43:49 AM UTC 24 |
434730784 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.3608726363 |
|
|
Oct 15 04:43:39 AM UTC 24 |
Oct 15 04:43:50 AM UTC 24 |
655852728 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.3923494795 |
|
|
Oct 15 04:43:51 AM UTC 24 |
Oct 15 04:43:53 AM UTC 24 |
12687066 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3876596389 |
|
|
Oct 15 04:43:51 AM UTC 24 |
Oct 15 04:43:53 AM UTC 24 |
35394003 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.3348325482 |
|
|
Oct 15 04:43:25 AM UTC 24 |
Oct 15 04:43:53 AM UTC 24 |
218721346 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.2811806396 |
|
|
Oct 15 04:43:51 AM UTC 24 |
Oct 15 04:43:55 AM UTC 24 |
217650420 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.3327380715 |
|
|
Oct 15 04:43:38 AM UTC 24 |
Oct 15 04:43:56 AM UTC 24 |
2248903309 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.4240225382 |
|
|
Oct 15 04:43:46 AM UTC 24 |
Oct 15 04:43:57 AM UTC 24 |
311591303 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.422705625 |
|
|
Oct 15 04:43:54 AM UTC 24 |
Oct 15 04:43:58 AM UTC 24 |
191785327 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.2683977159 |
|
|
Oct 15 04:43:04 AM UTC 24 |
Oct 15 04:44:38 AM UTC 24 |
20171318160 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.1921362613 |
|
|
Oct 15 04:43:54 AM UTC 24 |
Oct 15 04:43:59 AM UTC 24 |
60343940 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.3502050955 |
|
|
Oct 15 04:43:46 AM UTC 24 |
Oct 15 04:43:59 AM UTC 24 |
1167238936 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.287378397 |
|
|
Oct 15 04:43:38 AM UTC 24 |
Oct 15 04:44:00 AM UTC 24 |
1136116788 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.185938756 |
|
|
Oct 15 04:43:46 AM UTC 24 |
Oct 15 04:44:01 AM UTC 24 |
1013004597 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.1769631723 |
|
|
Oct 15 04:43:48 AM UTC 24 |
Oct 15 04:44:01 AM UTC 24 |
353621523 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.180577824 |
|
|
Oct 15 04:40:08 AM UTC 24 |
Oct 15 04:44:01 AM UTC 24 |
7104457939 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1609138544 |
|
|
Oct 15 04:43:48 AM UTC 24 |
Oct 15 04:44:01 AM UTC 24 |
1071681715 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.478812911 |
|
|
Oct 15 04:43:40 AM UTC 24 |
Oct 15 04:44:02 AM UTC 24 |
2416507976 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.1299813419 |
|
|
Oct 15 04:44:01 AM UTC 24 |
Oct 15 04:44:03 AM UTC 24 |
45300396 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.506393411 |
|
|
Oct 15 04:43:49 AM UTC 24 |
Oct 15 04:44:03 AM UTC 24 |
644378081 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.3104290394 |
|
|
Oct 15 04:43:57 AM UTC 24 |
Oct 15 04:44:04 AM UTC 24 |
299194762 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1188462100 |
|
|
Oct 15 04:44:03 AM UTC 24 |
Oct 15 04:44:05 AM UTC 24 |
12120592 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.2520324749 |
|
|
Oct 15 04:44:03 AM UTC 24 |
Oct 15 04:44:06 AM UTC 24 |
142874213 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.4180151695 |
|
|
Oct 15 04:44:03 AM UTC 24 |
Oct 15 04:44:06 AM UTC 24 |
29400569 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.1407422061 |
|
|
Oct 15 04:43:46 AM UTC 24 |
Oct 15 04:44:07 AM UTC 24 |
1722691104 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.4026723760 |
|
|
Oct 15 04:43:36 AM UTC 24 |
Oct 15 04:44:07 AM UTC 24 |
319528016 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.3517441396 |
|
|
Oct 15 04:43:56 AM UTC 24 |
Oct 15 04:44:07 AM UTC 24 |
702248192 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.1940129673 |
|
|
Oct 15 04:44:03 AM UTC 24 |
Oct 15 04:44:08 AM UTC 24 |
124139394 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.3295762494 |
|
|
Oct 15 04:44:05 AM UTC 24 |
Oct 15 04:44:09 AM UTC 24 |
102797468 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.1032275136 |
|
|
Oct 15 04:43:58 AM UTC 24 |
Oct 15 04:44:10 AM UTC 24 |
619459796 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_errors.475546196 |
|
|
Oct 15 04:43:54 AM UTC 24 |
Oct 15 04:44:10 AM UTC 24 |
479364644 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.2160214655 |
|
|
Oct 15 04:44:09 AM UTC 24 |
Oct 15 04:44:11 AM UTC 24 |
15170242 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.482585783 |
|
|
Oct 15 04:44:09 AM UTC 24 |
Oct 15 04:44:12 AM UTC 24 |
48989511 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1872875163 |
|
|
Oct 15 04:44:10 AM UTC 24 |
Oct 15 04:44:12 AM UTC 24 |
14710953 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.1680834815 |
|
|
Oct 15 04:43:45 AM UTC 24 |
Oct 15 04:44:12 AM UTC 24 |
1012091979 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.493906923 |
|
|
Oct 15 04:44:00 AM UTC 24 |
Oct 15 04:44:16 AM UTC 24 |
281056611 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.3548023708 |
|
|
Oct 15 04:43:51 AM UTC 24 |
Oct 15 04:44:16 AM UTC 24 |
906324267 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.874196877 |
|
|
Oct 15 04:44:12 AM UTC 24 |
Oct 15 04:44:16 AM UTC 24 |
88500875 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.665189158 |
|
|
Oct 15 04:44:11 AM UTC 24 |
Oct 15 04:44:16 AM UTC 24 |
43787199 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_errors.1580867690 |
|
|
Oct 15 04:44:04 AM UTC 24 |
Oct 15 04:44:17 AM UTC 24 |
233649599 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.3189541483 |
|
|
Oct 15 04:42:47 AM UTC 24 |
Oct 15 04:44:17 AM UTC 24 |
3609575340 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.2890104127 |
|
|
Oct 15 04:44:05 AM UTC 24 |
Oct 15 04:44:17 AM UTC 24 |
1139448172 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.2483844690 |
|
|
Oct 15 04:44:04 AM UTC 24 |
Oct 15 04:44:17 AM UTC 24 |
283911856 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.3812436031 |
|
|
Oct 15 04:44:07 AM UTC 24 |
Oct 15 04:44:20 AM UTC 24 |
748201777 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.1613183220 |
|
|
Oct 15 04:44:23 AM UTC 24 |
Oct 15 04:44:39 AM UTC 24 |
1249243418 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.2663366580 |
|
|
Oct 15 04:44:00 AM UTC 24 |
Oct 15 04:44:20 AM UTC 24 |
1791805874 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.426097237 |
|
|
Oct 15 04:44:19 AM UTC 24 |
Oct 15 04:44:21 AM UTC 24 |
130355829 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1186384968 |
|
|
Oct 15 04:44:19 AM UTC 24 |
Oct 15 04:44:21 AM UTC 24 |
12989554 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.3137311284 |
|
|
Oct 15 04:44:19 AM UTC 24 |
Oct 15 04:44:22 AM UTC 24 |
40523667 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.1781475543 |
|
|
Oct 15 04:44:21 AM UTC 24 |
Oct 15 04:44:24 AM UTC 24 |
29819070 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.2722470456 |
|
|
Oct 15 04:44:14 AM UTC 24 |
Oct 15 04:44:25 AM UTC 24 |
4495122588 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.465123541 |
|
|
Oct 15 04:38:19 AM UTC 24 |
Oct 15 04:44:27 AM UTC 24 |
8008797907 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.3812416308 |
|
|
Oct 15 04:41:14 AM UTC 24 |
Oct 15 04:46:12 AM UTC 24 |
59627156007 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.3033297486 |
|
|
Oct 15 04:44:07 AM UTC 24 |
Oct 15 04:44:27 AM UTC 24 |
570992557 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.4048183923 |
|
|
Oct 15 04:44:21 AM UTC 24 |
Oct 15 04:44:27 AM UTC 24 |
103035658 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.2374026787 |
|
|
Oct 15 04:44:13 AM UTC 24 |
Oct 15 04:44:28 AM UTC 24 |
298815787 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.864886631 |
|
|
Oct 15 04:44:17 AM UTC 24 |
Oct 15 04:44:28 AM UTC 24 |
327351288 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.1293541261 |
|
|
Oct 15 04:44:03 AM UTC 24 |
Oct 15 04:44:29 AM UTC 24 |
232264496 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.1203619292 |
|
|
Oct 15 04:44:17 AM UTC 24 |
Oct 15 04:44:29 AM UTC 24 |
3148487181 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_errors.2329627716 |
|
|
Oct 15 04:44:12 AM UTC 24 |
Oct 15 04:44:30 AM UTC 24 |
994475099 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.1697669965 |
|
|
Oct 15 04:42:09 AM UTC 24 |
Oct 15 04:45:56 AM UTC 24 |
6249596681 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3296225547 |
|
|
Oct 15 04:44:30 AM UTC 24 |
Oct 15 04:44:32 AM UTC 24 |
43835042 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.2580799046 |
|
|
Oct 15 04:44:30 AM UTC 24 |
Oct 15 04:44:32 AM UTC 24 |
44826962 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.2011742807 |
|
|
Oct 15 04:44:17 AM UTC 24 |
Oct 15 04:44:33 AM UTC 24 |
1787948386 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.2274545881 |
|
|
Oct 15 04:44:22 AM UTC 24 |
Oct 15 04:44:34 AM UTC 24 |
1422010563 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.3884809338 |
|
|
Oct 15 04:44:34 AM UTC 24 |
Oct 15 04:44:39 AM UTC 24 |
2313316753 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.891251381 |
|
|
Oct 15 04:44:00 AM UTC 24 |
Oct 15 04:44:34 AM UTC 24 |
6037912533 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.4157584941 |
|
|
Oct 15 04:44:30 AM UTC 24 |
Oct 15 04:44:35 AM UTC 24 |
255617015 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.2296958261 |
|
|
Oct 15 04:44:21 AM UTC 24 |
Oct 15 04:44:35 AM UTC 24 |
617995452 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_errors.3591325050 |
|
|
Oct 15 04:44:22 AM UTC 24 |
Oct 15 04:44:36 AM UTC 24 |
284565568 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.2396237113 |
|
|
Oct 15 04:44:25 AM UTC 24 |
Oct 15 04:44:37 AM UTC 24 |
606236829 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.3180130186 |
|
|
Oct 15 04:44:31 AM UTC 24 |
Oct 15 04:44:37 AM UTC 24 |
60446323 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.1244583086 |
|
|
Oct 15 04:44:38 AM UTC 24 |
Oct 15 04:44:40 AM UTC 24 |
37110502 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1764754604 |
|
|
Oct 15 04:44:38 AM UTC 24 |
Oct 15 04:44:40 AM UTC 24 |
32160642 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.984226330 |
|
|
Oct 15 04:44:30 AM UTC 24 |
Oct 15 04:44:40 AM UTC 24 |
85097863 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.2347048719 |
|
|
Oct 15 04:44:11 AM UTC 24 |
Oct 15 04:44:41 AM UTC 24 |
275286169 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.4221600507 |
|
|
Oct 15 04:44:38 AM UTC 24 |
Oct 15 04:44:42 AM UTC 24 |
192359747 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.1617658252 |
|
|
Oct 15 04:44:33 AM UTC 24 |
Oct 15 04:44:42 AM UTC 24 |
292926506 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.1699650409 |
|
|
Oct 15 04:44:28 AM UTC 24 |
Oct 15 04:44:44 AM UTC 24 |
291597732 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_errors.1666956501 |
|
|
Oct 15 04:44:33 AM UTC 24 |
Oct 15 04:44:45 AM UTC 24 |
464048680 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.3942753405 |
|
|
Oct 15 04:44:40 AM UTC 24 |
Oct 15 04:44:46 AM UTC 24 |
244847078 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.2561934882 |
|
|
Oct 15 04:44:46 AM UTC 24 |
Oct 15 04:44:49 AM UTC 24 |
79392154 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.2832111443 |
|
|
Oct 15 04:44:46 AM UTC 24 |
Oct 15 04:44:50 AM UTC 24 |
36461264 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.1138984155 |
|
|
Oct 15 04:44:35 AM UTC 24 |
Oct 15 04:44:50 AM UTC 24 |
278210860 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1238569075 |
|
|
Oct 15 04:43:49 AM UTC 24 |
Oct 15 04:44:50 AM UTC 24 |
1921276397 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2049112021 |
|
|
Oct 15 04:44:08 AM UTC 24 |
Oct 15 04:44:51 AM UTC 24 |
18533756270 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.1996651121 |
|
|
Oct 15 04:44:35 AM UTC 24 |
Oct 15 04:44:51 AM UTC 24 |
2325859489 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3566335408 |
|
|
Oct 15 04:43:22 AM UTC 24 |
Oct 15 04:44:52 AM UTC 24 |
26808391612 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2196908439 |
|
|
Oct 15 04:42:47 AM UTC 24 |
Oct 15 04:44:52 AM UTC 24 |
17658994977 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.701383953 |
|
|
Oct 15 04:44:42 AM UTC 24 |
Oct 15 04:44:52 AM UTC 24 |
779591380 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2040104047 |
|
|
Oct 15 04:44:50 AM UTC 24 |
Oct 15 04:44:52 AM UTC 24 |
13410459 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.4169262623 |
|
|
Oct 15 04:44:39 AM UTC 24 |
Oct 15 04:44:52 AM UTC 24 |
369691478 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.3643219014 |
|
|
Oct 15 04:44:35 AM UTC 24 |
Oct 15 04:44:52 AM UTC 24 |
913707521 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3523480581 |
|
|
Oct 15 04:44:36 AM UTC 24 |
Oct 15 04:44:53 AM UTC 24 |
530301996 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_errors.2530943854 |
|
|
Oct 15 04:44:40 AM UTC 24 |
Oct 15 04:44:54 AM UTC 24 |
1464099399 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.1075588123 |
|
|
Oct 15 04:44:42 AM UTC 24 |
Oct 15 04:44:54 AM UTC 24 |
983474512 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.1513419069 |
|
|
Oct 15 04:44:42 AM UTC 24 |
Oct 15 04:44:55 AM UTC 24 |
634363502 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.1913655996 |
|
|
Oct 15 04:44:43 AM UTC 24 |
Oct 15 04:44:55 AM UTC 24 |
316392864 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.79012505 |
|
|
Oct 15 04:44:42 AM UTC 24 |
Oct 15 04:44:56 AM UTC 24 |
420592552 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.3784880447 |
|
|
Oct 15 04:44:51 AM UTC 24 |
Oct 15 04:44:56 AM UTC 24 |
43055891 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1299975451 |
|
|
Oct 15 04:44:54 AM UTC 24 |
Oct 15 04:44:57 AM UTC 24 |
51905542 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.119121823 |
|
|
Oct 15 04:44:54 AM UTC 24 |
Oct 15 04:44:57 AM UTC 24 |
128964932 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.2190979985 |
|
|
Oct 15 04:44:54 AM UTC 24 |
Oct 15 04:44:57 AM UTC 24 |
26592997 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.2002383017 |
|
|
Oct 15 04:44:57 AM UTC 24 |
Oct 15 04:45:01 AM UTC 24 |
187566590 ps |