| T604 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.3226365582 |
|
|
Feb 09 02:15:18 PM UTC 25 |
Feb 09 02:17:00 PM UTC 25 |
15684481840 ps |
| T605 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.158768451 |
|
|
Feb 09 02:16:46 PM UTC 25 |
Feb 09 02:17:00 PM UTC 25 |
1644740046 ps |
| T606 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_errors.927820477 |
|
|
Feb 09 02:16:45 PM UTC 25 |
Feb 09 02:17:01 PM UTC 25 |
382562356 ps |
| T607 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.2541273432 |
|
|
Feb 09 02:14:55 PM UTC 25 |
Feb 09 02:17:02 PM UTC 25 |
3609416369 ps |
| T608 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.348577571 |
|
|
Feb 09 02:16:45 PM UTC 25 |
Feb 09 02:17:02 PM UTC 25 |
204195750 ps |
| T609 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.343796758 |
|
|
Feb 09 02:16:49 PM UTC 25 |
Feb 09 02:17:02 PM UTC 25 |
275776130 ps |
| T610 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3865126641 |
|
|
Feb 09 02:17:00 PM UTC 25 |
Feb 09 02:17:03 PM UTC 25 |
14021832 ps |
| T611 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.2765958238 |
|
|
Feb 09 02:17:00 PM UTC 25 |
Feb 09 02:17:03 PM UTC 25 |
21723957 ps |
| T612 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.1982375854 |
|
|
Feb 09 02:17:00 PM UTC 25 |
Feb 09 02:17:04 PM UTC 25 |
25707399 ps |
| T613 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.3200433780 |
|
|
Feb 09 02:16:54 PM UTC 25 |
Feb 09 02:17:05 PM UTC 25 |
369132727 ps |
| T614 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.4076056200 |
|
|
Feb 09 02:16:27 PM UTC 25 |
Feb 09 02:17:05 PM UTC 25 |
2517859633 ps |
| T615 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.2295004901 |
|
|
Feb 09 02:17:03 PM UTC 25 |
Feb 09 02:17:07 PM UTC 25 |
91519267 ps |
| T616 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.2312709057 |
|
|
Feb 09 02:16:47 PM UTC 25 |
Feb 09 02:17:11 PM UTC 25 |
3122513395 ps |
| T80 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.3876532970 |
|
|
Feb 09 02:17:12 PM UTC 25 |
Feb 09 02:17:14 PM UTC 25 |
19074703 ps |
| T617 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.1238964679 |
|
|
Feb 09 02:17:05 PM UTC 25 |
Feb 09 02:17:15 PM UTC 25 |
215092541 ps |
| T618 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.2816156691 |
|
|
Feb 09 02:16:56 PM UTC 25 |
Feb 09 02:17:15 PM UTC 25 |
1535552059 ps |
| T619 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.1733910592 |
|
|
Feb 09 02:15:40 PM UTC 25 |
Feb 09 02:17:17 PM UTC 25 |
5110448746 ps |
| T620 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3684374874 |
|
|
Feb 09 02:17:16 PM UTC 25 |
Feb 09 02:17:18 PM UTC 25 |
20018174 ps |
| T621 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_errors.2383631556 |
|
|
Feb 09 02:17:03 PM UTC 25 |
Feb 09 02:17:18 PM UTC 25 |
1005714149 ps |
| T622 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.2034745265 |
|
|
Feb 09 02:17:03 PM UTC 25 |
Feb 09 02:17:19 PM UTC 25 |
72359286 ps |
| T623 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.2276672080 |
|
|
Feb 09 02:17:05 PM UTC 25 |
Feb 09 02:17:20 PM UTC 25 |
412274625 ps |
| T624 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.587461624 |
|
|
Feb 09 02:17:16 PM UTC 25 |
Feb 09 02:17:21 PM UTC 25 |
96358103 ps |
| T625 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.4217779174 |
|
|
Feb 09 02:17:04 PM UTC 25 |
Feb 09 02:17:22 PM UTC 25 |
278880700 ps |
| T626 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.935574962 |
|
|
Feb 09 02:17:04 PM UTC 25 |
Feb 09 02:17:22 PM UTC 25 |
7994550700 ps |
| T627 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.1903873049 |
|
|
Feb 09 02:17:05 PM UTC 25 |
Feb 09 02:17:23 PM UTC 25 |
303559391 ps |
| T628 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1957941065 |
|
|
Feb 09 02:18:02 PM UTC 25 |
Feb 09 02:18:05 PM UTC 25 |
20540888 ps |
| T629 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.1159052793 |
|
|
Feb 09 02:13:18 PM UTC 25 |
Feb 09 02:17:23 PM UTC 25 |
7584401031 ps |
| T630 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.3510464901 |
|
|
Feb 09 02:17:19 PM UTC 25 |
Feb 09 02:17:24 PM UTC 25 |
193942844 ps |
| T631 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.245887256 |
|
|
Feb 09 02:17:21 PM UTC 25 |
Feb 09 02:17:25 PM UTC 25 |
67376316 ps |
| T632 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.2483964210 |
|
|
Feb 09 02:17:55 PM UTC 25 |
Feb 09 02:18:06 PM UTC 25 |
1195304857 ps |
| T633 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.1454872560 |
|
|
Feb 09 02:13:03 PM UTC 25 |
Feb 09 02:17:25 PM UTC 25 |
5916715924 ps |
| T634 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.3790161882 |
|
|
Feb 09 02:16:45 PM UTC 25 |
Feb 09 02:17:26 PM UTC 25 |
490395712 ps |
| T635 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.852500405 |
|
|
Feb 09 02:17:24 PM UTC 25 |
Feb 09 02:17:27 PM UTC 25 |
36237872 ps |
| T636 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2172649261 |
|
|
Feb 09 02:17:26 PM UTC 25 |
Feb 09 02:17:28 PM UTC 25 |
89855410 ps |
| T637 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.712689584 |
|
|
Feb 09 02:17:18 PM UTC 25 |
Feb 09 02:17:29 PM UTC 25 |
280407291 ps |
| T638 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.3915967549 |
|
|
Feb 09 02:09:55 PM UTC 25 |
Feb 09 02:17:31 PM UTC 25 |
63267141238 ps |
| T639 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.3765824706 |
|
|
Feb 09 02:17:26 PM UTC 25 |
Feb 09 02:17:32 PM UTC 25 |
93739625 ps |
| T640 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_errors.1145707770 |
|
|
Feb 09 02:17:19 PM UTC 25 |
Feb 09 02:17:34 PM UTC 25 |
1284423713 ps |
| T641 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.2890414225 |
|
|
Feb 09 02:17:29 PM UTC 25 |
Feb 09 02:17:35 PM UTC 25 |
57017159 ps |
| T642 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.2308211326 |
|
|
Feb 09 02:17:21 PM UTC 25 |
Feb 09 02:17:35 PM UTC 25 |
338806780 ps |
| T643 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.724684441 |
|
|
Feb 09 02:17:22 PM UTC 25 |
Feb 09 02:17:37 PM UTC 25 |
1343974155 ps |
| T644 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.654324342 |
|
|
Feb 09 02:17:23 PM UTC 25 |
Feb 09 02:17:38 PM UTC 25 |
324362533 ps |
| T645 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.2178093723 |
|
|
Feb 09 02:17:23 PM UTC 25 |
Feb 09 02:17:38 PM UTC 25 |
2595279161 ps |
| T646 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.1978430671 |
|
|
Feb 09 02:17:28 PM UTC 25 |
Feb 09 02:17:39 PM UTC 25 |
67892317 ps |
| T647 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.2605756742 |
|
|
Feb 09 02:17:40 PM UTC 25 |
Feb 09 02:17:43 PM UTC 25 |
18973585 ps |
| T648 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.1518706126 |
|
|
Feb 09 02:17:32 PM UTC 25 |
Feb 09 02:17:44 PM UTC 25 |
690022844 ps |
| T649 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.3803030335 |
|
|
Feb 09 02:17:40 PM UTC 25 |
Feb 09 02:17:45 PM UTC 25 |
67905178 ps |
| T650 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1710001461 |
|
|
Feb 09 02:17:44 PM UTC 25 |
Feb 09 02:17:46 PM UTC 25 |
14925456 ps |
| T651 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.2069412433 |
|
|
Feb 09 02:17:35 PM UTC 25 |
Feb 09 02:17:47 PM UTC 25 |
427359446 ps |
| T652 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.1067019385 |
|
|
Feb 09 02:17:33 PM UTC 25 |
Feb 09 02:17:47 PM UTC 25 |
1537292030 ps |
| T653 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.3783107578 |
|
|
Feb 09 02:17:03 PM UTC 25 |
Feb 09 02:17:50 PM UTC 25 |
800504172 ps |
| T654 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.1069016636 |
|
|
Feb 09 02:17:17 PM UTC 25 |
Feb 09 02:17:51 PM UTC 25 |
224579831 ps |
| T655 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.505230686 |
|
|
Feb 09 02:17:36 PM UTC 25 |
Feb 09 02:17:52 PM UTC 25 |
360987657 ps |
| T656 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.929883030 |
|
|
Feb 09 02:17:47 PM UTC 25 |
Feb 09 02:17:54 PM UTC 25 |
768923461 ps |
| T657 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.451815815 |
|
|
Feb 09 02:17:50 PM UTC 25 |
Feb 09 02:17:55 PM UTC 25 |
544138310 ps |
| T658 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_errors.1820839480 |
|
|
Feb 09 02:17:29 PM UTC 25 |
Feb 09 02:17:58 PM UTC 25 |
751334421 ps |
| T659 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.1645487696 |
|
|
Feb 09 02:17:48 PM UTC 25 |
Feb 09 02:18:00 PM UTC 25 |
623091576 ps |
| T660 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.3241649887 |
|
|
Feb 09 02:17:46 PM UTC 25 |
Feb 09 02:18:02 PM UTC 25 |
64887303 ps |
| T661 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.1588301026 |
|
|
Feb 09 02:17:36 PM UTC 25 |
Feb 09 02:18:02 PM UTC 25 |
5028424447 ps |
| T662 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.4277597042 |
|
|
Feb 09 02:18:01 PM UTC 25 |
Feb 09 02:18:03 PM UTC 25 |
142054740 ps |
| T663 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.259213888 |
|
|
Feb 09 02:17:48 PM UTC 25 |
Feb 09 02:18:07 PM UTC 25 |
353145935 ps |
| T86 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.2424607010 |
|
|
Feb 09 02:18:02 PM UTC 25 |
Feb 09 02:18:07 PM UTC 25 |
31853974 ps |
| T664 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.880461708 |
|
|
Feb 09 02:18:07 PM UTC 25 |
Feb 09 02:18:12 PM UTC 25 |
57031568 ps |
| T665 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.3314378038 |
|
|
Feb 09 02:17:52 PM UTC 25 |
Feb 09 02:18:13 PM UTC 25 |
273963200 ps |
| T666 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.3230198489 |
|
|
Feb 09 02:17:54 PM UTC 25 |
Feb 09 02:18:13 PM UTC 25 |
1166752304 ps |
| T667 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.542934244 |
|
|
Feb 09 02:17:27 PM UTC 25 |
Feb 09 02:18:16 PM UTC 25 |
509310504 ps |
| T668 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.1783076028 |
|
|
Feb 09 02:18:05 PM UTC 25 |
Feb 09 02:18:16 PM UTC 25 |
43035790 ps |
| T669 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.4113359711 |
|
|
Feb 09 02:18:08 PM UTC 25 |
Feb 09 02:18:20 PM UTC 25 |
596258959 ps |
| T670 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.3899489263 |
|
|
Feb 09 02:17:45 PM UTC 25 |
Feb 09 02:18:21 PM UTC 25 |
590823842 ps |
| T671 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_errors.3779193709 |
|
|
Feb 09 02:18:08 PM UTC 25 |
Feb 09 02:18:21 PM UTC 25 |
1016028988 ps |
| T672 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.626822064 |
|
|
Feb 09 02:18:21 PM UTC 25 |
Feb 09 02:18:23 PM UTC 25 |
44369196 ps |
| T673 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2315699764 |
|
|
Feb 09 02:18:22 PM UTC 25 |
Feb 09 02:18:25 PM UTC 25 |
14787025 ps |
| T674 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.673547447 |
|
|
Feb 09 02:18:13 PM UTC 25 |
Feb 09 02:18:28 PM UTC 25 |
7514843872 ps |
| T675 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.2024514662 |
|
|
Feb 09 02:18:25 PM UTC 25 |
Feb 09 02:18:31 PM UTC 25 |
229145993 ps |
| T676 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.1924917093 |
|
|
Feb 09 02:18:14 PM UTC 25 |
Feb 09 02:18:33 PM UTC 25 |
3241411606 ps |
| T87 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.625859278 |
|
|
Feb 09 02:18:22 PM UTC 25 |
Feb 09 02:18:34 PM UTC 25 |
1627092302 ps |
| T677 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.1234472932 |
|
|
Feb 09 02:18:29 PM UTC 25 |
Feb 09 02:18:34 PM UTC 25 |
259191955 ps |
| T678 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.394802888 |
|
|
Feb 09 02:16:21 PM UTC 25 |
Feb 09 02:18:40 PM UTC 25 |
5482575649 ps |
| T679 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.3836302108 |
|
|
Feb 09 02:18:35 PM UTC 25 |
Feb 09 02:18:40 PM UTC 25 |
181982061 ps |
| T680 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.1972162776 |
|
|
Feb 09 02:18:17 PM UTC 25 |
Feb 09 02:18:42 PM UTC 25 |
1736864004 ps |
| T681 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.1653760162 |
|
|
Feb 09 02:15:31 PM UTC 25 |
Feb 09 02:18:44 PM UTC 25 |
49212630024 ps |
| T682 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.485124845 |
|
|
Feb 09 02:15:53 PM UTC 25 |
Feb 09 02:18:45 PM UTC 25 |
19708934946 ps |
| T683 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.1327172528 |
|
|
Feb 09 02:18:04 PM UTC 25 |
Feb 09 02:18:47 PM UTC 25 |
147836600 ps |
| T684 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.4210126110 |
|
|
Feb 09 02:16:35 PM UTC 25 |
Feb 09 02:18:48 PM UTC 25 |
2148503748 ps |
| T81 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.1620726035 |
|
|
Feb 09 02:18:46 PM UTC 25 |
Feb 09 02:18:49 PM UTC 25 |
68767394 ps |
| T685 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.2523188359 |
|
|
Feb 09 02:18:34 PM UTC 25 |
Feb 09 02:18:51 PM UTC 25 |
1733970979 ps |
| T686 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.1781373689 |
|
|
Feb 09 02:18:47 PM UTC 25 |
Feb 09 02:18:51 PM UTC 25 |
55797240 ps |
| T687 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3226942837 |
|
|
Feb 09 02:18:50 PM UTC 25 |
Feb 09 02:18:52 PM UTC 25 |
25533396 ps |
| T688 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.2858411015 |
|
|
Feb 09 02:18:52 PM UTC 25 |
Feb 09 02:18:56 PM UTC 25 |
50743233 ps |
| T689 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.1228297796 |
|
|
Feb 09 02:18:14 PM UTC 25 |
Feb 09 02:18:56 PM UTC 25 |
963693591 ps |
| T690 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_errors.339960883 |
|
|
Feb 09 02:18:32 PM UTC 25 |
Feb 09 02:18:56 PM UTC 25 |
2456326148 ps |
| T691 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.2978175543 |
|
|
Feb 09 02:18:41 PM UTC 25 |
Feb 09 02:18:57 PM UTC 25 |
2103131729 ps |
| T692 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.1321449215 |
|
|
Feb 09 02:18:35 PM UTC 25 |
Feb 09 02:18:57 PM UTC 25 |
671944104 ps |
| T693 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.586400666 |
|
|
Feb 09 02:18:41 PM UTC 25 |
Feb 09 02:18:57 PM UTC 25 |
841413961 ps |
| T694 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.231217352 |
|
|
Feb 09 02:16:07 PM UTC 25 |
Feb 09 02:18:59 PM UTC 25 |
31587096337 ps |
| T695 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.3440054659 |
|
|
Feb 09 02:18:24 PM UTC 25 |
Feb 09 02:19:03 PM UTC 25 |
184842719 ps |
| T696 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.283517472 |
|
|
Feb 09 02:18:57 PM UTC 25 |
Feb 09 02:19:05 PM UTC 25 |
454627129 ps |
| T697 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.573981234 |
|
|
Feb 09 02:19:03 PM UTC 25 |
Feb 09 02:19:06 PM UTC 25 |
99622769 ps |
| T698 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.897429900 |
|
|
Feb 09 02:18:56 PM UTC 25 |
Feb 09 02:19:08 PM UTC 25 |
280068181 ps |
| T699 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.42729435 |
|
|
Feb 09 02:19:06 PM UTC 25 |
Feb 09 02:19:09 PM UTC 25 |
21307160 ps |
| T700 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.2684396533 |
|
|
Feb 09 02:20:02 PM UTC 25 |
Feb 09 02:20:18 PM UTC 25 |
483692933 ps |
| T701 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.4180369766 |
|
|
Feb 09 02:18:52 PM UTC 25 |
Feb 09 02:19:12 PM UTC 25 |
89959124 ps |
| T702 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.3007993042 |
|
|
Feb 09 02:19:05 PM UTC 25 |
Feb 09 02:19:13 PM UTC 25 |
192719250 ps |
| T703 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.4293656623 |
|
|
Feb 09 02:18:58 PM UTC 25 |
Feb 09 02:19:13 PM UTC 25 |
621651719 ps |
| T704 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.860978761 |
|
|
Feb 09 02:19:13 PM UTC 25 |
Feb 09 02:19:18 PM UTC 25 |
176239778 ps |
| T705 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.2779940155 |
|
|
Feb 09 02:18:53 PM UTC 25 |
Feb 09 02:19:19 PM UTC 25 |
1719197765 ps |
| T706 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.1102966030 |
|
|
Feb 09 02:19:10 PM UTC 25 |
Feb 09 02:19:19 PM UTC 25 |
201665063 ps |
| T707 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.1664864049 |
|
|
Feb 09 02:18:57 PM UTC 25 |
Feb 09 02:19:20 PM UTC 25 |
2641773662 ps |
| T708 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.3681718797 |
|
|
Feb 09 02:19:14 PM UTC 25 |
Feb 09 02:19:24 PM UTC 25 |
355534113 ps |
| T709 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.207654167 |
|
|
Feb 09 02:18:59 PM UTC 25 |
Feb 09 02:19:27 PM UTC 25 |
708219675 ps |
| T710 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.764169440 |
|
|
Feb 09 02:19:25 PM UTC 25 |
Feb 09 02:19:28 PM UTC 25 |
22153529 ps |
| T711 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.1712920789 |
|
|
Feb 09 02:19:14 PM UTC 25 |
Feb 09 02:19:29 PM UTC 25 |
1551459728 ps |
| T712 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2967393787 |
|
|
Feb 09 02:19:29 PM UTC 25 |
Feb 09 02:19:31 PM UTC 25 |
38261119 ps |
| T713 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.872521025 |
|
|
Feb 09 02:19:28 PM UTC 25 |
Feb 09 02:19:31 PM UTC 25 |
76771081 ps |
| T714 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.2614126720 |
|
|
Feb 09 02:19:19 PM UTC 25 |
Feb 09 02:19:32 PM UTC 25 |
544038957 ps |
| T715 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.3912349907 |
|
|
Feb 09 02:18:50 PM UTC 25 |
Feb 09 02:19:33 PM UTC 25 |
189855868 ps |
| T716 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.532727184 |
|
|
Feb 09 02:19:20 PM UTC 25 |
Feb 09 02:19:34 PM UTC 25 |
795633285 ps |
| T101 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.3771414317 |
|
|
Feb 09 02:10:54 PM UTC 25 |
Feb 09 02:19:36 PM UTC 25 |
128324002036 ps |
| T102 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3246824933 |
|
|
Feb 09 02:12:41 PM UTC 25 |
Feb 09 02:19:38 PM UTC 25 |
69188362846 ps |
| T164 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.4201947916 |
|
|
Feb 09 02:19:32 PM UTC 25 |
Feb 09 02:19:38 PM UTC 25 |
78495303 ps |
| T165 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.2053357783 |
|
|
Feb 09 02:19:20 PM UTC 25 |
Feb 09 02:19:39 PM UTC 25 |
1242621900 ps |
| T166 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.253379335 |
|
|
Feb 09 02:19:22 PM UTC 25 |
Feb 09 02:19:40 PM UTC 25 |
282028925 ps |
| T167 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.4154139302 |
|
|
Feb 09 02:19:32 PM UTC 25 |
Feb 09 02:19:48 PM UTC 25 |
246743848 ps |
| T168 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.349300944 |
|
|
Feb 09 02:19:35 PM UTC 25 |
Feb 09 02:19:49 PM UTC 25 |
584426337 ps |
| T169 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.3658864287 |
|
|
Feb 09 02:19:50 PM UTC 25 |
Feb 09 02:19:52 PM UTC 25 |
116518575 ps |
| T170 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.452801947 |
|
|
Feb 09 02:19:40 PM UTC 25 |
Feb 09 02:19:54 PM UTC 25 |
221295158 ps |
| T171 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.2845066012 |
|
|
Feb 09 02:19:40 PM UTC 25 |
Feb 09 02:19:55 PM UTC 25 |
195711922 ps |
| T717 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.4152652575 |
|
|
Feb 09 02:19:53 PM UTC 25 |
Feb 09 02:19:55 PM UTC 25 |
13694326 ps |
| T718 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.2673423875 |
|
|
Feb 09 02:19:34 PM UTC 25 |
Feb 09 02:19:56 PM UTC 25 |
1524796528 ps |
| T88 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.2189921840 |
|
|
Feb 09 02:19:50 PM UTC 25 |
Feb 09 02:19:57 PM UTC 25 |
708391160 ps |
| T719 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_errors.1744285023 |
|
|
Feb 09 02:19:33 PM UTC 25 |
Feb 09 02:19:58 PM UTC 25 |
404260681 ps |
| T720 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.2292653074 |
|
|
Feb 09 02:19:09 PM UTC 25 |
Feb 09 02:20:01 PM UTC 25 |
563651135 ps |
| T721 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.2057707719 |
|
|
Feb 09 02:19:56 PM UTC 25 |
Feb 09 02:20:01 PM UTC 25 |
60373609 ps |
| T722 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.3600532533 |
|
|
Feb 09 02:19:56 PM UTC 25 |
Feb 09 02:20:04 PM UTC 25 |
152998255 ps |
| T723 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.3321816041 |
|
|
Feb 09 02:19:57 PM UTC 25 |
Feb 09 02:20:06 PM UTC 25 |
283638205 ps |
| T724 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.4063049943 |
|
|
Feb 09 02:19:38 PM UTC 25 |
Feb 09 02:20:08 PM UTC 25 |
1116016874 ps |
| T725 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_errors.4151126121 |
|
|
Feb 09 02:19:57 PM UTC 25 |
Feb 09 02:20:10 PM UTC 25 |
312581311 ps |
| T726 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.843142433 |
|
|
Feb 09 02:20:10 PM UTC 25 |
Feb 09 02:20:13 PM UTC 25 |
22280654 ps |
| T727 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.2922816445 |
|
|
Feb 09 02:19:58 PM UTC 25 |
Feb 09 02:20:14 PM UTC 25 |
587559747 ps |
| T728 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.833536143 |
|
|
Feb 09 02:20:14 PM UTC 25 |
Feb 09 02:20:17 PM UTC 25 |
18336721 ps |
| T729 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.2567295367 |
|
|
Feb 09 02:20:05 PM UTC 25 |
Feb 09 02:20:19 PM UTC 25 |
237275952 ps |
| T730 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.1683335499 |
|
|
Feb 09 02:22:22 PM UTC 25 |
Feb 09 02:22:28 PM UTC 25 |
178816430 ps |
| T731 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.873918169 |
|
|
Feb 09 02:20:02 PM UTC 25 |
Feb 09 02:20:19 PM UTC 25 |
2483317178 ps |
| T732 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.2865884296 |
|
|
Feb 09 02:20:14 PM UTC 25 |
Feb 09 02:20:20 PM UTC 25 |
421461865 ps |
| T733 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.705591210 |
|
|
Feb 09 02:22:10 PM UTC 25 |
Feb 09 02:22:26 PM UTC 25 |
287381874 ps |
| T734 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.986060739 |
|
|
Feb 09 02:19:30 PM UTC 25 |
Feb 09 02:20:24 PM UTC 25 |
951647201 ps |
| T735 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.4037263100 |
|
|
Feb 09 02:17:24 PM UTC 25 |
Feb 09 02:20:25 PM UTC 25 |
6992471696 ps |
| T736 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.884150509 |
|
|
Feb 09 02:20:19 PM UTC 25 |
Feb 09 02:20:25 PM UTC 25 |
91969287 ps |
| T737 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.1056276057 |
|
|
Feb 09 02:20:20 PM UTC 25 |
Feb 09 02:20:27 PM UTC 25 |
82424416 ps |
| T738 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.1719661392 |
|
|
Feb 09 02:19:55 PM UTC 25 |
Feb 09 02:20:30 PM UTC 25 |
788119265 ps |
| T739 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.1070996122 |
|
|
Feb 09 02:20:26 PM UTC 25 |
Feb 09 02:20:35 PM UTC 25 |
330203583 ps |
| T740 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.855192103 |
|
|
Feb 09 02:20:24 PM UTC 25 |
Feb 09 02:20:35 PM UTC 25 |
250289283 ps |
| T741 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.1719831182 |
|
|
Feb 09 02:20:21 PM UTC 25 |
Feb 09 02:20:37 PM UTC 25 |
1741642000 ps |
| T742 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.1766432372 |
|
|
Feb 09 02:20:20 PM UTC 25 |
Feb 09 02:20:38 PM UTC 25 |
241955987 ps |
| T743 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.1462105745 |
|
|
Feb 09 02:20:36 PM UTC 25 |
Feb 09 02:20:39 PM UTC 25 |
22144163 ps |
| T744 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.3734117513 |
|
|
Feb 09 02:20:36 PM UTC 25 |
Feb 09 02:20:41 PM UTC 25 |
174790102 ps |
| T745 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3466904221 |
|
|
Feb 09 02:20:38 PM UTC 25 |
Feb 09 02:20:41 PM UTC 25 |
14511449 ps |
| T746 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.3628294975 |
|
|
Feb 09 02:20:26 PM UTC 25 |
Feb 09 02:20:41 PM UTC 25 |
1034036872 ps |
| T747 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.3354335387 |
|
|
Feb 09 02:20:42 PM UTC 25 |
Feb 09 02:20:46 PM UTC 25 |
278816672 ps |
| T748 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1542154308 |
|
|
Feb 09 02:20:24 PM UTC 25 |
Feb 09 02:20:47 PM UTC 25 |
4534199237 ps |
| T117 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3204000623 |
|
|
Feb 09 02:14:03 PM UTC 25 |
Feb 09 02:20:51 PM UTC 25 |
147317681298 ps |
| T177 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.685287537 |
|
|
Feb 09 02:19:40 PM UTC 25 |
Feb 09 02:20:52 PM UTC 25 |
3530269552 ps |
| T178 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.1966838981 |
|
|
Feb 09 02:20:40 PM UTC 25 |
Feb 09 02:20:54 PM UTC 25 |
491786761 ps |
| T179 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.3626972435 |
|
|
Feb 09 02:20:43 PM UTC 25 |
Feb 09 02:20:56 PM UTC 25 |
259563020 ps |
| T180 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.1618863854 |
|
|
Feb 09 02:20:47 PM UTC 25 |
Feb 09 02:20:58 PM UTC 25 |
1877252988 ps |
| T181 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_errors.3839283336 |
|
|
Feb 09 02:20:42 PM UTC 25 |
Feb 09 02:20:58 PM UTC 25 |
300936949 ps |
| T182 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.2843440881 |
|
|
Feb 09 02:20:58 PM UTC 25 |
Feb 09 02:21:01 PM UTC 25 |
118451800 ps |
| T183 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3561321476 |
|
|
Feb 09 02:21:00 PM UTC 25 |
Feb 09 02:21:03 PM UTC 25 |
12458584 ps |
| T184 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.2335121162 |
|
|
Feb 09 02:20:58 PM UTC 25 |
Feb 09 02:21:03 PM UTC 25 |
64012785 ps |
| T185 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.2978909169 |
|
|
Feb 09 02:20:48 PM UTC 25 |
Feb 09 02:21:04 PM UTC 25 |
322529389 ps |
| T749 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.4100621081 |
|
|
Feb 09 02:20:52 PM UTC 25 |
Feb 09 02:21:06 PM UTC 25 |
997652039 ps |
| T750 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.3754049766 |
|
|
Feb 09 02:21:05 PM UTC 25 |
Feb 09 02:21:08 PM UTC 25 |
52096716 ps |
| T751 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.2126213673 |
|
|
Feb 09 02:20:53 PM UTC 25 |
Feb 09 02:21:08 PM UTC 25 |
252853041 ps |
| T752 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.1429427453 |
|
|
Feb 09 02:20:17 PM UTC 25 |
Feb 09 02:21:13 PM UTC 25 |
343451118 ps |
| T753 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.2383018506 |
|
|
Feb 09 02:17:07 PM UTC 25 |
Feb 09 02:21:17 PM UTC 25 |
5149923923 ps |
| T754 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.3724082844 |
|
|
Feb 09 02:21:03 PM UTC 25 |
Feb 09 02:21:17 PM UTC 25 |
139629728 ps |
| T755 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.2731199387 |
|
|
Feb 09 02:21:09 PM UTC 25 |
Feb 09 02:21:19 PM UTC 25 |
3431555489 ps |
| T756 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_errors.2422343017 |
|
|
Feb 09 02:21:05 PM UTC 25 |
Feb 09 02:21:19 PM UTC 25 |
209148998 ps |
| T757 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.4121315779 |
|
|
Feb 09 02:21:09 PM UTC 25 |
Feb 09 02:21:19 PM UTC 25 |
875641618 ps |
| T758 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.906257446 |
|
|
Feb 09 02:20:39 PM UTC 25 |
Feb 09 02:21:21 PM UTC 25 |
477862536 ps |
| T759 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.3464350738 |
|
|
Feb 09 02:21:07 PM UTC 25 |
Feb 09 02:21:22 PM UTC 25 |
361583091 ps |
| T760 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.1952935124 |
|
|
Feb 09 02:21:20 PM UTC 25 |
Feb 09 02:21:23 PM UTC 25 |
18165501 ps |
| T761 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.1910462223 |
|
|
Feb 09 02:21:20 PM UTC 25 |
Feb 09 02:21:24 PM UTC 25 |
139212924 ps |
| T762 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.835623706 |
|
|
Feb 09 02:21:22 PM UTC 25 |
Feb 09 02:21:25 PM UTC 25 |
15234987 ps |
| T763 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.198769595 |
|
|
Feb 09 02:21:14 PM UTC 25 |
Feb 09 02:21:27 PM UTC 25 |
256757899 ps |
| T764 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.1125862347 |
|
|
Feb 09 02:17:56 PM UTC 25 |
Feb 09 02:21:28 PM UTC 25 |
6100152026 ps |
| T765 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.3785834650 |
|
|
Feb 09 02:21:25 PM UTC 25 |
Feb 09 02:21:29 PM UTC 25 |
190980332 ps |
| T766 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.3161220997 |
|
|
Feb 09 02:21:23 PM UTC 25 |
Feb 09 02:21:30 PM UTC 25 |
77295862 ps |
| T767 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.1208550920 |
|
|
Feb 09 02:21:02 PM UTC 25 |
Feb 09 02:21:30 PM UTC 25 |
284513005 ps |
| T768 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.2595583067 |
|
|
Feb 09 02:21:19 PM UTC 25 |
Feb 09 02:21:31 PM UTC 25 |
789991155 ps |
| T769 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.4028748413 |
|
|
Feb 09 02:18:17 PM UTC 25 |
Feb 09 02:21:33 PM UTC 25 |
26015639615 ps |
| T770 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.2041526762 |
|
|
Feb 09 02:21:34 PM UTC 25 |
Feb 09 02:21:36 PM UTC 25 |
82404003 ps |
| T771 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.3015739997 |
|
|
Feb 09 02:21:28 PM UTC 25 |
Feb 09 02:21:39 PM UTC 25 |
1877687900 ps |
| T772 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1747200801 |
|
|
Feb 09 02:21:40 PM UTC 25 |
Feb 09 02:21:42 PM UTC 25 |
13706483 ps |
| T773 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_errors.3935367703 |
|
|
Feb 09 02:21:26 PM UTC 25 |
Feb 09 02:21:43 PM UTC 25 |
1363542537 ps |
| T774 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.3654507012 |
|
|
Feb 09 02:21:31 PM UTC 25 |
Feb 09 02:21:45 PM UTC 25 |
528393756 ps |
| T775 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.1109112226 |
|
|
Feb 09 02:21:37 PM UTC 25 |
Feb 09 02:21:46 PM UTC 25 |
374224323 ps |
| T776 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.1390622834 |
|
|
Feb 09 02:21:31 PM UTC 25 |
Feb 09 02:21:46 PM UTC 25 |
538049849 ps |
| T777 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.3690245478 |
|
|
Feb 09 02:21:31 PM UTC 25 |
Feb 09 02:21:46 PM UTC 25 |
201732356 ps |
| T778 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.3079568231 |
|
|
Feb 09 02:21:29 PM UTC 25 |
Feb 09 02:21:50 PM UTC 25 |
1265997515 ps |
| T779 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.422029021 |
|
|
Feb 09 02:21:45 PM UTC 25 |
Feb 09 02:21:50 PM UTC 25 |
46408570 ps |
| T780 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.3103765136 |
|
|
Feb 09 02:16:56 PM UTC 25 |
Feb 09 02:21:51 PM UTC 25 |
16850721299 ps |
| T781 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.202349635 |
|
|
Feb 09 02:21:47 PM UTC 25 |
Feb 09 02:22:02 PM UTC 25 |
1783582189 ps |
| T782 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.745500055 |
|
|
Feb 09 02:21:44 PM UTC 25 |
Feb 09 02:22:03 PM UTC 25 |
370944657 ps |
| T783 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.868022625 |
|
|
Feb 09 02:21:47 PM UTC 25 |
Feb 09 02:22:04 PM UTC 25 |
526524428 ps |
| T784 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.1456493906 |
|
|
Feb 09 02:21:52 PM UTC 25 |
Feb 09 02:22:05 PM UTC 25 |
620745045 ps |
| T62 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.2716003873 |
|
|
Feb 09 02:19:23 PM UTC 25 |
Feb 09 02:22:06 PM UTC 25 |
6416173109 ps |
| T785 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.3122949318 |
|
|
Feb 09 02:22:04 PM UTC 25 |
Feb 09 02:22:07 PM UTC 25 |
64816724 ps |
| T786 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3868278747 |
|
|
Feb 09 02:22:04 PM UTC 25 |
Feb 09 02:22:07 PM UTC 25 |
44941342 ps |
| T787 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_errors.1725726828 |
|
|
Feb 09 02:21:47 PM UTC 25 |
Feb 09 02:22:08 PM UTC 25 |
861398534 ps |
| T788 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.3012027589 |
|
|
Feb 09 02:22:04 PM UTC 25 |
Feb 09 02:22:08 PM UTC 25 |
45647429 ps |
| T789 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.2463396141 |
|
|
Feb 09 02:18:42 PM UTC 25 |
Feb 09 02:22:09 PM UTC 25 |
16512639437 ps |
| T790 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.1785666366 |
|
|
Feb 09 02:21:51 PM UTC 25 |
Feb 09 02:22:11 PM UTC 25 |
594777499 ps |
| T791 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.2983034481 |
|
|
Feb 09 02:22:08 PM UTC 25 |
Feb 09 02:22:14 PM UTC 25 |
324851878 ps |
| T792 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.3094967615 |
|
|
Feb 09 02:22:09 PM UTC 25 |
Feb 09 02:22:17 PM UTC 25 |
595834021 ps |
| T793 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.415122697 |
|
|
Feb 09 02:21:51 PM UTC 25 |
Feb 09 02:22:19 PM UTC 25 |
813685145 ps |
| T794 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.2544136407 |
|
|
Feb 09 02:22:08 PM UTC 25 |
Feb 09 02:22:19 PM UTC 25 |
235082870 ps |
| T795 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.2305274616 |
|
|
Feb 09 02:22:09 PM UTC 25 |
Feb 09 02:22:21 PM UTC 25 |
256660182 ps |
| T796 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.1452041120 |
|
|
Feb 09 02:22:20 PM UTC 25 |
Feb 09 02:22:22 PM UTC 25 |
71330073 ps |
| T797 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.874280298 |
|
|
Feb 09 02:22:12 PM UTC 25 |
Feb 09 02:22:24 PM UTC 25 |
738384072 ps |
| T798 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.1202154250 |
|
|
Feb 09 02:21:23 PM UTC 25 |
Feb 09 02:22:25 PM UTC 25 |
261715760 ps |
| T799 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.317912766 |
|
|
Feb 09 02:22:23 PM UTC 25 |
Feb 09 02:22:25 PM UTC 25 |
19040728 ps |
| T800 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.4076610538 |
|
|
Feb 09 02:22:27 PM UTC 25 |
Feb 09 02:22:30 PM UTC 25 |
59361107 ps |
| T801 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.210264153 |
|
|
Feb 09 02:17:38 PM UTC 25 |
Feb 09 02:22:31 PM UTC 25 |
24032840828 ps |
| T802 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.592592963 |
|
|
Feb 09 02:20:07 PM UTC 25 |
Feb 09 02:22:33 PM UTC 25 |
3756836220 ps |
| T803 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_errors.2617130693 |
|
|
Feb 09 02:22:08 PM UTC 25 |
Feb 09 02:22:33 PM UTC 25 |
4476451364 ps |
| T804 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.727966512 |
|
|
Feb 09 02:22:15 PM UTC 25 |
Feb 09 02:22:34 PM UTC 25 |
418195351 ps |
| T805 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.4119183776 |
|
|
Feb 09 02:22:27 PM UTC 25 |
Feb 09 02:22:36 PM UTC 25 |
58563328 ps |
| T806 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.1923796165 |
|
|
Feb 09 02:21:43 PM UTC 25 |
Feb 09 02:22:37 PM UTC 25 |
1333889196 ps |
| T807 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_errors.3918741359 |
|
|
Feb 09 02:22:28 PM UTC 25 |
Feb 09 02:22:39 PM UTC 25 |
1380725792 ps |
| T808 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.1939116104 |
|
|
Feb 09 02:22:37 PM UTC 25 |
Feb 09 02:22:39 PM UTC 25 |
37976909 ps |
| T809 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.1872862626 |
|
|
Feb 09 02:20:28 PM UTC 25 |
Feb 09 02:22:40 PM UTC 25 |
32485141777 ps |
| T810 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.4031897222 |
|
|
Feb 09 02:22:05 PM UTC 25 |
Feb 09 02:22:41 PM UTC 25 |
2009357609 ps |
| T811 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3447198739 |
|
|
Feb 09 02:22:40 PM UTC 25 |
Feb 09 02:22:42 PM UTC 25 |
43459278 ps |
| T812 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.2005436477 |
|
|
Feb 09 02:22:29 PM UTC 25 |
Feb 09 02:22:42 PM UTC 25 |
260721186 ps |
| T813 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.1642606383 |
|
|
Feb 09 02:22:38 PM UTC 25 |
Feb 09 02:22:44 PM UTC 25 |
276668494 ps |
| T814 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.1892920900 |
|
|
Feb 09 02:22:34 PM UTC 25 |
Feb 09 02:22:44 PM UTC 25 |
178087785 ps |
| T815 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.3697638761 |
|
|
Feb 09 02:22:34 PM UTC 25 |
Feb 09 02:22:45 PM UTC 25 |
315195981 ps |
| T816 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.3622705732 |
|
|
Feb 09 02:22:41 PM UTC 25 |
Feb 09 02:22:46 PM UTC 25 |
39600542 ps |
| T817 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.628000624 |
|
|
Feb 09 02:22:32 PM UTC 25 |
Feb 09 02:22:47 PM UTC 25 |
1278066115 ps |
| T818 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.4199593365 |
|
|
Feb 09 02:22:25 PM UTC 25 |
Feb 09 02:22:53 PM UTC 25 |
297370055 ps |
| T118 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2745725521 |
|
|
Feb 09 02:14:55 PM UTC 25 |
Feb 09 02:22:53 PM UTC 25 |
35733811106 ps |
| T819 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.475361677 |
|
|
Feb 09 02:22:41 PM UTC 25 |
Feb 09 02:22:54 PM UTC 25 |
115826302 ps |
| T820 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.3201663760 |
|
|
Feb 09 02:22:44 PM UTC 25 |
Feb 09 02:22:56 PM UTC 25 |
769130274 ps |
| T821 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.1551956280 |
|
|
Feb 09 02:22:54 PM UTC 25 |
Feb 09 02:22:57 PM UTC 25 |
19273829 ps |
| T822 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3198152533 |
|
|
Feb 09 02:22:55 PM UTC 25 |
Feb 09 02:22:57 PM UTC 25 |
15019397 ps |
| T823 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.3915705397 |
|
|
Feb 09 02:22:54 PM UTC 25 |
Feb 09 02:22:59 PM UTC 25 |
42739015 ps |
| T824 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.403004123 |
|
|
Feb 09 02:22:45 PM UTC 25 |
Feb 09 02:23:01 PM UTC 25 |
207948749 ps |
| T825 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.2944041706 |
|
|
Feb 09 02:22:45 PM UTC 25 |
Feb 09 02:23:01 PM UTC 25 |
670092443 ps |
| T826 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.3387944463 |
|
|
Feb 09 02:22:46 PM UTC 25 |
Feb 09 02:23:02 PM UTC 25 |
1139194114 ps |