LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: b938dde05c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.240s	293.996us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.160s	14.607us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.070s	59.810us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.860s	68.762us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.290s	22.283us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.010s	30.498us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.070s	59.810us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	22.283us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.290s	655.846us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.480s	1.219ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.070s	13.810us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.670s	773.817us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	41.490s	773.387us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.950s	709.939us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	41.490s	773.387us	50	50	100.00
		lc_ctrl_prog_failure	4.670s	773.817us	50	50	100.00
		lc_ctrl_errors	23.950s	709.939us	50	50	100.00
		lc_ctrl_security_escalation	21.420s	642.905us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.761m	4.398ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	12.470s	624.716us	20	20	100.00
		lc_ctrl_jtag_errors	1.797m	7.811ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.990s	990.227us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	25.890s	2.937ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	12.470s	624.716us	20	20	100.00
		lc_ctrl_jtag_errors	1.797m	7.811ms	20	20	100.00
		lc_ctrl_jtag_access	21.920s	10.043ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	30.810s	2.138ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.280s	411.793us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.080s	1.899ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	43.130s	2.013ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	16.100s	16.515ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.850s	164.954us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.730s	462.715us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.640s	81.915us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	19.930s	3.887ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.440s	25.507us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.223m	30.991ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.280s	87.418us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.100s	1.161ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.100s	1.161ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.160s	14.607us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	59.810us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	22.283us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.890s	42.029us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.160s	14.607us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	59.810us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	22.283us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.890s	42.029us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	32.620s	813.809us	5	5	100.00
		lc_ctrl_tl_intg_err	4.450s	129.098us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.450s	129.098us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.480s	1.219ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	41.490s	773.387us	50	50	100.00
		lc_ctrl_sec_cm	32.620s	813.809us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	41.490s	773.387us	50	50	100.00
		lc_ctrl_sec_cm	32.620s	813.809us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	41.490s	773.387us	50	50	100.00
		lc_ctrl_sec_cm	32.620s	813.809us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	41.490s	773.387us	50	50	100.00
		lc_ctrl_sec_cm	32.620s	813.809us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	41.490s	773.387us	50	50	100.00
		lc_ctrl_sec_cm	32.620s	813.809us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	41.490s	773.387us	50	50	100.00
		lc_ctrl_sec_cm	32.620s	813.809us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	41.490s	773.387us	50	50	100.00
		lc_ctrl_sec_cm	32.620s	813.809us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	41.490s	773.387us	50	50	100.00
		lc_ctrl_sec_cm	32.620s	813.809us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	21.420s	642.905us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.290s	655.846us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	25.890s	2.937ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	31.410s	1.244ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	31.410s	1.244ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.870s	1.263ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	24.910s	3.413ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	24.910s	3.413ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.029h	159.461ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1005	1030	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.94	97.89	95.95	93.31	97.67	98.55	98.76	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 16 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.84557755588440799302651376564361402789924623599008292140812745041593702733291
      Line 24220, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22309963271 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 22309963271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.57292785921169231095645218633328368698975424317562626149620218197348858781932
      Line 14823, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 50183663744 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 50183663744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 5 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 5 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.94488073424678703906230400216985751169611976397533769102699488934400489979669
      Line 20650, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 48417652098 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 48417652098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.90782518631276351647448886933443399325533459510565014991875237374831175688393
      Line 13895, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10189623160 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 10189623160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 21.lc_ctrl_stress_all_with_rand_reset.90210198885539719925475129951027041801003604693592531390589726171205193572869
      Line 15354, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 48083066050 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 48083066050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 40.lc_ctrl_stress_all_with_rand_reset.88433542073770062417668011266384176419856206148185123851211047407790179185652
      Line 21420, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 51892532207 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 51892532207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 25.lc_ctrl_stress_all.82386289018721726385293501332990320282602715471706222603674769267850256660535
      Line 10622, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 2983957878 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 2983957878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:753) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 42.lc_ctrl_stress_all_with_rand_reset.90497964303469824239534785611773913297256918726310463786625469629746480595368
      Line 11438, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3124086915 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3124086915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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