Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5870	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36488

1

T1

408

T2

396

T3

190

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8634	1			T1	29		T2	43		T3	21
values[0x0]	16388	1			T1	189		T2	164		T3	82
values[0x1]	17336	1			T1	190		T2	189		T3	87

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3949	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38409

1

T1

408

T2

396

T3

190

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	170	1			T3	2		T7	1		T6	1
valid_sources[0x01]	178	1			T1	4		T4	4		T6	1
valid_sources[0x02]	160	1			T1	4		T6	3		T27	7
valid_sources[0x03]	151	1			T6	1		T27	1		T9	6
valid_sources[0x04]	164	1			T1	6		T4	1		T6	1
valid_sources[0x05]	130	1			T6	2		T27	2		T9	1
valid_sources[0x06]	128	1			T1	3		T2	2		T3	2
valid_sources[0x07]	122	1			T1	4		T9	3		T28	7
valid_sources[0x08]	144	1			T1	1		T3	1		T6	5
valid_sources[0x09]	127	1			T1	1		T3	2		T4	1
valid_sources[0x0a]	148	1			T1	3		T6	2		T9	2
valid_sources[0x0b]	199	1			T1	1		T2	12		T3	7
valid_sources[0x0c]	231	1			T1	5		T4	4		T6	3
valid_sources[0x0d]	91	1			T1	3		T7	1		T6	1
valid_sources[0x0e]	252	1			T7	1		T9	3		T28	3
valid_sources[0x0f]	133	1			T1	1		T6	3		T9	1
valid_sources[0x10]	258	1			T6	8		T9	4		T30	5
valid_sources[0x11]	160	1			T1	1		T4	1		T9	6
valid_sources[0x12]	159	1			T1	3		T2	8		T3	6
valid_sources[0x13]	145	1			T3	3		T6	4		T9	3
valid_sources[0x14]	178	1			T1	1		T3	3		T9	1
valid_sources[0x15]	133	1			T1	2		T6	4		T27	2
valid_sources[0x16]	159	1			T1	3		T6	2		T9	2
valid_sources[0x17]	136	1			T1	4		T6	3		T9	4
valid_sources[0x18]	163	1			T1	1		T6	2		T9	5
valid_sources[0x19]	286	1			T1	2		T3	4		T6	3
valid_sources[0x1a]	173	1			T1	1		T3	3		T4	11
valid_sources[0x1b]	288	1			T1	5		T6	4		T27	4
valid_sources[0x1c]	197	1			T1	1		T3	5		T6	2
valid_sources[0x1d]	155	1			T6	2		T9	1		T30	1
valid_sources[0x1e]	208	1			T1	2		T2	2		T6	4
valid_sources[0x1f]	140	1			T1	1		T3	4		T6	2
valid_sources[0x20]	136	1			T1	2		T4	3		T7	1
valid_sources[0x21]	240	1			T3	2		T6	4		T9	4
valid_sources[0x22]	162	1			T1	1		T2	8		T3	1
valid_sources[0x23]	122	1			T1	1		T4	4		T19	1
valid_sources[0x24]	187	1			T1	3		T6	1		T9	3
valid_sources[0x25]	138	1			T1	3		T4	2		T6	1
valid_sources[0x26]	200	1			T1	4		T3	5		T4	9
valid_sources[0x27]	118	1			T2	5		T6	3		T27	4
valid_sources[0x28]	313	1			T2	7		T6	5		T9	4
valid_sources[0x29]	154	1			T6	3		T9	3		T28	4
valid_sources[0x2a]	125	1			T6	3		T27	2		T9	3
valid_sources[0x2b]	217	1			T1	2		T2	16		T3	1
valid_sources[0x2c]	115	1			T4	1		T6	1		T27	10
valid_sources[0x2d]	120	1			T2	1		T6	3		T27	2
valid_sources[0x2e]	208	1			T9	1		T30	7		T12	1
valid_sources[0x2f]	161	1			T1	7		T2	5		T3	2
valid_sources[0x30]	166	1			T1	5		T4	2		T6	4
valid_sources[0x31]	204	1			T1	5		T4	5		T27	2
valid_sources[0x32]	262	1			T6	5		T5	1		T28	7
valid_sources[0x33]	167	1			T6	3		T27	3		T9	6
valid_sources[0x34]	177	1			T1	2		T7	2		T6	3
valid_sources[0x35]	131	1			T4	1		T6	2		T9	2
valid_sources[0x36]	125	1			T3	1		T6	5		T9	1
valid_sources[0x37]	148	1			T2	2		T6	2		T9	1
valid_sources[0x38]	155	1			T1	1		T6	1		T28	3
valid_sources[0x39]	109	1			T1	1		T7	1		T6	4
valid_sources[0x3a]	177	1			T2	1		T6	5		T27	4
valid_sources[0x3b]	162	1			T1	1		T3	7		T9	3
valid_sources[0x3c]	122	1			T3	4		T6	1		T9	1
valid_sources[0x3d]	349	1			T1	11		T9	6		T28	2
valid_sources[0x3e]	153	1			T1	1		T4	7		T6	3
valid_sources[0x3f]	140	1			T1	1		T7	1		T6	1
valid_sources[0x40]	145	1			T1	2		T2	6		T4	1
valid_sources[0x41]	212	1			T1	3		T3	3		T4	3
valid_sources[0x42]	195	1			T2	24		T4	4		T9	3
valid_sources[0x43]	127	1			T1	1		T6	1		T9	1
valid_sources[0x44]	133	1			T1	2		T6	2		T27	4
valid_sources[0x45]	142	1			T1	2		T2	17		T6	4
valid_sources[0x46]	144	1			T1	3		T7	1		T6	1
valid_sources[0x47]	158	1			T1	4		T6	1		T28	1
valid_sources[0x48]	154	1			T1	5		T6	2		T9	4
valid_sources[0x49]	111	1			T6	2		T9	1		T28	1
valid_sources[0x4a]	123	1			T1	3		T2	3		T6	1
valid_sources[0x4b]	205	1			T1	2		T3	2		T6	1
valid_sources[0x4c]	149	1			T1	2		T2	2		T7	2
valid_sources[0x4d]	162	1			T2	4		T6	4		T9	1
valid_sources[0x4e]	159	1			T1	2		T3	6		T6	3
valid_sources[0x4f]	146	1			T1	1		T6	1		T9	7
valid_sources[0x50]	145	1			T1	1		T3	2		T4	5
valid_sources[0x51]	293	1			T3	1		T6	7		T27	11
valid_sources[0x52]	104	1			T1	1		T3	2		T6	2
valid_sources[0x53]	133	1			T6	2		T28	2		T30	4
valid_sources[0x54]	131	1			T1	2		T6	1		T27	4
valid_sources[0x55]	251	1			T3	2		T9	5		T30	1
valid_sources[0x56]	164	1			T1	1		T6	7		T9	1
valid_sources[0x57]	234	1			T1	4		T2	10		T6	1
valid_sources[0x58]	168	1			T1	2		T2	30		T7	1
valid_sources[0x59]	163	1			T6	4		T9	4		T28	2
valid_sources[0x5a]	119	1			T7	1		T27	5		T30	5
valid_sources[0x5b]	95	1			T1	2		T9	3		T28	3
valid_sources[0x5c]	178	1			T6	5		T27	2		T9	1
valid_sources[0x5d]	185	1			T4	1		T6	11		T27	1
valid_sources[0x5e]	176	1			T1	1		T6	1		T27	2
valid_sources[0x5f]	190	1			T1	4		T3	1		T6	1
valid_sources[0x60]	151	1			T6	4		T9	1		T28	1
valid_sources[0x61]	132	1			T1	1		T2	7		T6	1
valid_sources[0x62]	174	1			T1	2		T6	6		T27	3
valid_sources[0x63]	143	1			T1	1		T7	1		T6	3
valid_sources[0x64]	268	1			T1	4		T4	1		T27	3
valid_sources[0x65]	124	1			T6	2		T9	1		T28	1
valid_sources[0x66]	105	1			T6	1		T9	3		T28	2
valid_sources[0x67]	221	1			T1	2		T3	5		T4	4
valid_sources[0x68]	201	1			T1	10		T6	3		T27	2
valid_sources[0x69]	187	1			T1	4		T3	2		T6	5
valid_sources[0x6a]	171	1			T1	1		T7	1		T9	1
valid_sources[0x6b]	216	1			T6	4		T9	1		T28	1
valid_sources[0x6c]	167	1			T1	4		T4	7		T6	6
valid_sources[0x6d]	200	1			T6	3		T28	4		T30	12
valid_sources[0x6e]	179	1			T1	1		T3	5		T6	2
valid_sources[0x6f]	166	1			T7	1		T6	4		T27	6
valid_sources[0x70]	159	1			T1	1		T6	1		T9	7
valid_sources[0x71]	166	1			T2	13		T6	1		T27	2
valid_sources[0x72]	178	1			T1	1		T2	5		T27	13
valid_sources[0x73]	212	1			T1	6		T7	1		T6	4
valid_sources[0x74]	133	1			T6	4		T27	1		T9	1
valid_sources[0x75]	105	1			T1	2		T7	1		T9	3
valid_sources[0x76]	203	1			T1	4		T7	1		T6	2
valid_sources[0x77]	178	1			T3	5		T6	5		T9	3
valid_sources[0x78]	161	1			T1	1		T2	3		T6	3
valid_sources[0x79]	158	1			T2	8		T4	5		T7	1
valid_sources[0x7a]	137	1			T1	7		T6	1		T27	5
valid_sources[0x7b]	176	1			T1	1		T4	2		T6	7
valid_sources[0x7c]	151	1			T1	2		T6	2		T27	2
valid_sources[0x7d]	172	1			T9	2		T28	6		T36	3
valid_sources[0x7e]	102	1			T7	1		T27	1		T9	7
valid_sources[0x7f]	182	1			T1	1		T2	4		T6	6
valid_sources[0x80]	207	1			T2	1		T6	8		T27	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5980

1

T1

29

T2

43

T3

21

values[0x0]

all_enables

biggest_size

15369

1

T1

189

T2

164

T3

82

values[0x1]

all_enables

biggest_size

15139

1

T1

190

T2

189

T3

87