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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.29 97.99 95.86 93.40 100.00 98.55 98.76 96.47


Total test records in report: 998
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T359 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.1560137525 Aug 23 09:48:34 AM UTC 24 Aug 23 09:49:01 AM UTC 24 227678034 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.1088560050 Aug 23 09:48:49 AM UTC 24 Aug 23 09:49:03 AM UTC 24 2148490852 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.2624408271 Aug 23 09:49:02 AM UTC 24 Aug 23 09:49:04 AM UTC 24 27821574 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.2809694255 Aug 23 09:49:02 AM UTC 24 Aug 23 09:49:05 AM UTC 24 65552057 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.904590438 Aug 23 09:49:04 AM UTC 24 Aug 23 09:49:06 AM UTC 24 41676262 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.798234575 Aug 23 09:48:54 AM UTC 24 Aug 23 09:49:09 AM UTC 24 1386531134 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.2988154657 Aug 23 09:49:07 AM UTC 24 Aug 23 09:49:10 AM UTC 24 97609932 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.3229066076 Aug 23 09:48:15 AM UTC 24 Aug 23 09:49:12 AM UTC 24 2586123487 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.1160515104 Aug 23 09:49:05 AM UTC 24 Aug 23 09:49:12 AM UTC 24 86459605 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.2617530455 Aug 23 09:49:13 AM UTC 24 Aug 23 09:49:20 AM UTC 24 393255524 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.1560467028 Aug 23 09:49:10 AM UTC 24 Aug 23 09:49:21 AM UTC 24 920162242 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.785327659 Aug 23 09:49:05 AM UTC 24 Aug 23 09:49:21 AM UTC 24 731562867 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.665585067 Aug 23 09:49:22 AM UTC 24 Aug 23 09:49:25 AM UTC 24 409647707 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.4095483853 Aug 23 09:49:10 AM UTC 24 Aug 23 09:49:25 AM UTC 24 1920489004 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1002370158 Aug 23 09:47:59 AM UTC 24 Aug 23 09:49:30 AM UTC 24 5715059244 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.133056868 Aug 23 09:49:23 AM UTC 24 Aug 23 09:49:33 AM UTC 24 6372457928 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.3920612743 Aug 23 09:49:22 AM UTC 24 Aug 23 09:49:35 AM UTC 24 1165085480 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.551955151 Aug 23 09:49:26 AM UTC 24 Aug 23 09:49:38 AM UTC 24 423654210 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.3818488107 Aug 23 09:48:45 AM UTC 24 Aug 23 09:49:39 AM UTC 24 4414197327 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.3416483052 Aug 23 09:49:30 AM UTC 24 Aug 23 09:49:41 AM UTC 24 438766188 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.2279697997 Aug 23 09:49:40 AM UTC 24 Aug 23 09:49:42 AM UTC 24 17368860 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.88596879 Aug 23 09:49:25 AM UTC 24 Aug 23 09:49:43 AM UTC 24 469171564 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.265048034 Aug 23 09:49:42 AM UTC 24 Aug 23 09:49:44 AM UTC 24 22796442 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.3818522571 Aug 23 09:49:40 AM UTC 24 Aug 23 09:49:44 AM UTC 24 119222228 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.2071336865 Aug 23 09:49:44 AM UTC 24 Aug 23 09:49:47 AM UTC 24 139412515 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.1793269577 Aug 23 09:46:57 AM UTC 24 Aug 23 09:49:48 AM UTC 24 5031955732 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.1031240990 Aug 23 09:49:44 AM UTC 24 Aug 23 09:49:52 AM UTC 24 71799781 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.3374612173 Aug 23 09:48:58 AM UTC 24 Aug 23 09:49:53 AM UTC 24 5705561336 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.2411841903 Aug 23 09:49:48 AM UTC 24 Aug 23 09:49:54 AM UTC 24 725000803 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_errors.3429461118 Aug 23 09:49:45 AM UTC 24 Aug 23 09:49:56 AM UTC 24 328289533 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.2395057805 Aug 23 09:49:48 AM UTC 24 Aug 23 09:49:59 AM UTC 24 1070306540 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.2801158139 Aug 23 09:48:39 AM UTC 24 Aug 23 09:49:59 AM UTC 24 4989370861 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.1108259960 Aug 23 09:49:55 AM UTC 24 Aug 23 09:50:00 AM UTC 24 263283147 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.302421674 Aug 23 09:48:28 AM UTC 24 Aug 23 09:50:03 AM UTC 24 21429658707 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.79686046 Aug 23 09:49:42 AM UTC 24 Aug 23 09:50:03 AM UTC 24 267361639 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.3796409184 Aug 23 09:49:54 AM UTC 24 Aug 23 09:50:04 AM UTC 24 311267211 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.3469701262 Aug 23 09:50:00 AM UTC 24 Aug 23 09:50:04 AM UTC 24 895387183 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.1500819355 Aug 23 09:49:22 AM UTC 24 Aug 23 09:50:07 AM UTC 24 1736835070 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.2502485159 Aug 23 09:50:06 AM UTC 24 Aug 23 09:50:08 AM UTC 24 43061044 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.2131742691 Aug 23 09:49:33 AM UTC 24 Aug 23 09:50:08 AM UTC 24 2286917487 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.1515166093 Aug 23 09:49:14 AM UTC 24 Aug 23 09:50:08 AM UTC 24 8344167419 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.1833549538 Aug 23 09:50:00 AM UTC 24 Aug 23 09:50:10 AM UTC 24 2115617841 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.392150952 Aug 23 09:50:01 AM UTC 24 Aug 23 09:50:11 AM UTC 24 597642089 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2271726426 Aug 23 09:50:09 AM UTC 24 Aug 23 09:50:11 AM UTC 24 24210503 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.908059673 Aug 23 09:50:08 AM UTC 24 Aug 23 09:50:11 AM UTC 24 73596172 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.2907564498 Aug 23 09:50:03 AM UTC 24 Aug 23 09:50:14 AM UTC 24 329259231 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.4062885922 Aug 23 09:50:11 AM UTC 24 Aug 23 09:50:14 AM UTC 24 303233629 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.214387026 Aug 23 09:48:57 AM UTC 24 Aug 23 09:50:17 AM UTC 24 2277865521 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.2679662964 Aug 23 09:50:09 AM UTC 24 Aug 23 09:50:17 AM UTC 24 231955365 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.1495809207 Aug 23 09:50:12 AM UTC 24 Aug 23 09:50:20 AM UTC 24 629071882 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_errors.922507687 Aug 23 09:50:11 AM UTC 24 Aug 23 09:50:23 AM UTC 24 1683151399 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.74558172 Aug 23 09:50:11 AM UTC 24 Aug 23 09:50:24 AM UTC 24 1170668248 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.2999008068 Aug 23 09:50:21 AM UTC 24 Aug 23 09:50:28 AM UTC 24 741504475 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.2403140352 Aug 23 09:49:57 AM UTC 24 Aug 23 09:50:32 AM UTC 24 2750317780 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.1761167164 Aug 23 09:50:24 AM UTC 24 Aug 23 09:50:32 AM UTC 24 236247522 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.1008303941 Aug 23 09:50:09 AM UTC 24 Aug 23 09:50:32 AM UTC 24 2172541669 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.1510397355 Aug 23 09:50:22 AM UTC 24 Aug 23 09:50:33 AM UTC 24 848416161 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.2187888141 Aug 23 09:50:18 AM UTC 24 Aug 23 09:50:34 AM UTC 24 2154169738 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.325955298 Aug 23 09:50:34 AM UTC 24 Aug 23 09:50:36 AM UTC 24 19939218 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.4111636902 Aug 23 09:50:34 AM UTC 24 Aug 23 09:50:36 AM UTC 24 47894576 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.1145219255 Aug 23 09:50:34 AM UTC 24 Aug 23 09:50:36 AM UTC 24 15181852 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.3949657954 Aug 23 09:50:14 AM UTC 24 Aug 23 09:50:37 AM UTC 24 1239642481 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.1565725164 Aug 23 09:49:53 AM UTC 24 Aug 23 09:50:37 AM UTC 24 7396754004 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.3192865848 Aug 23 09:50:24 AM UTC 24 Aug 23 09:50:38 AM UTC 24 2731333596 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.1136116352 Aug 23 09:50:36 AM UTC 24 Aug 23 09:50:40 AM UTC 24 370362503 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.1366997666 Aug 23 09:50:36 AM UTC 24 Aug 23 09:50:41 AM UTC 24 199393119 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_errors.2278629346 Aug 23 09:50:37 AM UTC 24 Aug 23 09:50:52 AM UTC 24 4255816343 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.596266009 Aug 23 09:50:38 AM UTC 24 Aug 23 09:50:41 AM UTC 24 318924889 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.3126812331 Aug 23 09:50:14 AM UTC 24 Aug 23 09:50:41 AM UTC 24 4306284881 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.1691065314 Aug 23 09:50:43 AM UTC 24 Aug 23 09:50:48 AM UTC 24 327476471 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.247748633 Aug 23 09:49:35 AM UTC 24 Aug 23 09:50:48 AM UTC 24 3395586055 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.610186997 Aug 23 09:52:12 AM UTC 24 Aug 23 09:52:30 AM UTC 24 189091283 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.479664090 Aug 23 09:50:38 AM UTC 24 Aug 23 09:50:52 AM UTC 24 2401461310 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.1762704907 Aug 23 09:50:42 AM UTC 24 Aug 23 09:50:56 AM UTC 24 533548473 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.2707857179 Aug 23 09:50:18 AM UTC 24 Aug 23 09:50:57 AM UTC 24 3033538228 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.2529745451 Aug 23 09:50:50 AM UTC 24 Aug 23 09:50:58 AM UTC 24 471589676 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.2862635546 Aug 23 09:50:56 AM UTC 24 Aug 23 09:50:58 AM UTC 24 59365147 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.378208183 Aug 23 09:50:35 AM UTC 24 Aug 23 09:50:59 AM UTC 24 448934039 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1711946195 Aug 23 09:50:59 AM UTC 24 Aug 23 09:51:00 AM UTC 24 163131675 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.3811773620 Aug 23 09:50:42 AM UTC 24 Aug 23 09:51:02 AM UTC 24 548381350 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.199828309 Aug 23 09:50:49 AM UTC 24 Aug 23 09:51:02 AM UTC 24 259765386 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.2054809166 Aug 23 09:50:52 AM UTC 24 Aug 23 09:51:02 AM UTC 24 949523459 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.1872964887 Aug 23 09:51:01 AM UTC 24 Aug 23 09:51:05 AM UTC 24 223259652 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.3643681416 Aug 23 09:50:57 AM UTC 24 Aug 23 09:51:06 AM UTC 24 925973024 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.1455464463 Aug 23 09:51:00 AM UTC 24 Aug 23 09:51:08 AM UTC 24 370474816 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.2559364639 Aug 23 09:50:42 AM UTC 24 Aug 23 09:51:08 AM UTC 24 2929969135 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.2756586845 Aug 23 09:51:03 AM UTC 24 Aug 23 09:51:10 AM UTC 24 385524975 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_errors.801084354 Aug 23 09:51:03 AM UTC 24 Aug 23 09:51:14 AM UTC 24 940704839 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.3886660238 Aug 23 09:51:07 AM UTC 24 Aug 23 09:51:15 AM UTC 24 507864877 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.514096623 Aug 23 09:51:03 AM UTC 24 Aug 23 09:51:15 AM UTC 24 2405944729 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.748076539 Aug 23 09:51:09 AM UTC 24 Aug 23 09:51:17 AM UTC 24 6378479499 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.2519102760 Aug 23 09:51:18 AM UTC 24 Aug 23 09:51:20 AM UTC 24 23096413 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.3012563388 Aug 23 09:51:06 AM UTC 24 Aug 23 09:51:20 AM UTC 24 614604442 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.1072751306 Aug 23 09:51:00 AM UTC 24 Aug 23 09:51:20 AM UTC 24 758874935 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.3809700975 Aug 23 09:51:13 AM UTC 24 Aug 23 09:51:21 AM UTC 24 252040992 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.1082250171 Aug 23 09:51:11 AM UTC 24 Aug 23 09:51:21 AM UTC 24 329131049 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.2781658388 Aug 23 09:47:59 AM UTC 24 Aug 23 09:51:22 AM UTC 24 51433106798 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.4203682936 Aug 23 09:51:21 AM UTC 24 Aug 23 09:51:23 AM UTC 24 48893261 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.3896643143 Aug 23 09:51:20 AM UTC 24 Aug 23 09:51:24 AM UTC 24 389157916 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.1967195192 Aug 23 09:51:22 AM UTC 24 Aug 23 09:51:25 AM UTC 24 61303276 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.3309803258 Aug 23 09:51:21 AM UTC 24 Aug 23 09:51:26 AM UTC 24 365378129 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.712426441 Aug 23 09:50:38 AM UTC 24 Aug 23 09:51:27 AM UTC 24 2703172991 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.3783819449 Aug 23 09:43:36 AM UTC 24 Aug 23 09:51:30 AM UTC 24 16454965955 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.875131225 Aug 23 09:51:15 AM UTC 24 Aug 23 09:51:30 AM UTC 24 9238120179 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_errors.1474942753 Aug 23 09:51:24 AM UTC 24 Aug 23 09:51:32 AM UTC 24 173081672 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.2696183307 Aug 23 09:51:24 AM UTC 24 Aug 23 09:51:34 AM UTC 24 3844584105 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.1078045558 Aug 23 09:52:31 AM UTC 24 Aug 23 09:52:33 AM UTC 24 58163827 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.2958738409 Aug 23 09:51:25 AM UTC 24 Aug 23 09:51:36 AM UTC 24 429091274 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.586981440 Aug 23 09:51:32 AM UTC 24 Aug 23 09:51:39 AM UTC 24 260176264 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.1630436990 Aug 23 09:51:28 AM UTC 24 Aug 23 09:51:39 AM UTC 24 370042662 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.3745661202 Aug 23 09:51:27 AM UTC 24 Aug 23 09:51:40 AM UTC 24 302533960 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.3962736971 Aug 23 09:51:41 AM UTC 24 Aug 23 09:51:43 AM UTC 24 17231667 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.2541208192 Aug 23 09:51:21 AM UTC 24 Aug 23 09:51:45 AM UTC 24 440305834 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.3098552753 Aug 23 09:51:35 AM UTC 24 Aug 23 09:51:46 AM UTC 24 1326404214 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.1522722405 Aug 23 09:51:43 AM UTC 24 Aug 23 09:51:47 AM UTC 24 38994512 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3458418368 Aug 23 09:51:46 AM UTC 24 Aug 23 09:51:47 AM UTC 24 41243206 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.155368971 Aug 23 09:51:48 AM UTC 24 Aug 23 09:51:52 AM UTC 24 232814149 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.1061135689 Aug 23 09:51:47 AM UTC 24 Aug 23 09:51:52 AM UTC 24 537506118 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.2377773961 Aug 23 09:51:37 AM UTC 24 Aug 23 09:51:52 AM UTC 24 883416270 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.977804095 Aug 23 09:51:33 AM UTC 24 Aug 23 09:51:53 AM UTC 24 516135737 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.3481841293 Aug 23 09:51:53 AM UTC 24 Aug 23 09:51:56 AM UTC 24 103723131 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_errors.481346318 Aug 23 09:51:48 AM UTC 24 Aug 23 09:51:58 AM UTC 24 271649269 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.299501384 Aug 23 09:51:54 AM UTC 24 Aug 23 09:51:58 AM UTC 24 269772018 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.2545154472 Aug 23 09:51:53 AM UTC 24 Aug 23 09:52:01 AM UTC 24 688308314 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.689709599 Aug 23 09:51:08 AM UTC 24 Aug 23 09:52:03 AM UTC 24 9594268555 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.1381354988 Aug 23 09:47:27 AM UTC 24 Aug 23 09:52:07 AM UTC 24 10018761391 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.4228962279 Aug 23 09:51:58 AM UTC 24 Aug 23 09:52:07 AM UTC 24 566708025 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.3473988880 Aug 23 09:51:47 AM UTC 24 Aug 23 09:52:08 AM UTC 24 287995451 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.2525185032 Aug 23 09:50:03 AM UTC 24 Aug 23 09:52:09 AM UTC 24 69421016560 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.1500211248 Aug 23 09:52:02 AM UTC 24 Aug 23 09:52:09 AM UTC 24 1119336064 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.3211797315 Aug 23 09:52:04 AM UTC 24 Aug 23 09:52:11 AM UTC 24 178538908 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.1703115817 Aug 23 09:52:10 AM UTC 24 Aug 23 09:52:11 AM UTC 24 10556283 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3473737148 Aug 23 09:52:10 AM UTC 24 Aug 23 09:52:11 AM UTC 24 25218355 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.2176772365 Aug 23 09:52:09 AM UTC 24 Aug 23 09:52:11 AM UTC 24 51667417 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.1142129501 Aug 23 09:52:18 AM UTC 24 Aug 23 09:52:32 AM UTC 24 3156582892 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.3103176156 Aug 23 09:51:54 AM UTC 24 Aug 23 09:52:12 AM UTC 24 3946694898 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.1276944860 Aug 23 09:51:59 AM UTC 24 Aug 23 09:52:15 AM UTC 24 2123769331 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.1167773829 Aug 23 09:52:13 AM UTC 24 Aug 23 09:52:16 AM UTC 24 327848786 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.3755394701 Aug 23 09:52:13 AM UTC 24 Aug 23 09:52:17 AM UTC 24 142955769 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.3202333030 Aug 23 09:51:16 AM UTC 24 Aug 23 09:52:20 AM UTC 24 3095159168 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.2726628484 Aug 23 09:52:13 AM UTC 24 Aug 23 09:52:21 AM UTC 24 223589983 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.1965833026 Aug 23 09:52:13 AM UTC 24 Aug 23 09:52:23 AM UTC 24 1329494473 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_errors.1281998183 Aug 23 09:52:13 AM UTC 24 Aug 23 09:52:25 AM UTC 24 1592366123 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.3633977812 Aug 23 09:52:22 AM UTC 24 Aug 23 09:52:27 AM UTC 24 5392224765 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.915120426 Aug 23 09:51:31 AM UTC 24 Aug 23 09:52:27 AM UTC 24 4065855403 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.5631340 Aug 23 09:51:57 AM UTC 24 Aug 23 09:52:30 AM UTC 24 1590611245 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.1135982039 Aug 23 09:52:33 AM UTC 24 Aug 23 09:52:36 AM UTC 24 29879890 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.1371394021 Aug 23 09:52:18 AM UTC 24 Aug 23 09:52:32 AM UTC 24 3129455822 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.623551197 Aug 23 09:52:33 AM UTC 24 Aug 23 09:52:35 AM UTC 24 32223978 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.2368898669 Aug 23 09:52:26 AM UTC 24 Aug 23 09:52:37 AM UTC 24 645314952 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.3473455312 Aug 23 09:52:36 AM UTC 24 Aug 23 09:52:39 AM UTC 24 62407843 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.1285241640 Aug 23 09:51:53 AM UTC 24 Aug 23 09:52:40 AM UTC 24 1375454722 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.2744667541 Aug 23 09:52:24 AM UTC 24 Aug 23 09:52:40 AM UTC 24 1464395726 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.811680886 Aug 23 09:52:28 AM UTC 24 Aug 23 09:52:41 AM UTC 24 1819304953 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.3251367761 Aug 23 09:51:05 AM UTC 24 Aug 23 09:52:41 AM UTC 24 17812308631 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.3233887411 Aug 23 09:52:34 AM UTC 24 Aug 23 09:52:42 AM UTC 24 89780907 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.3266833696 Aug 23 09:52:41 AM UTC 24 Aug 23 09:52:44 AM UTC 24 336927836 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.2532641285 Aug 23 09:52:45 AM UTC 24 Aug 23 09:52:46 AM UTC 24 19829562 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.271030555 Aug 23 09:53:59 AM UTC 24 Aug 23 09:54:01 AM UTC 24 14114039 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_errors.1556390564 Aug 23 09:52:37 AM UTC 24 Aug 23 09:52:47 AM UTC 24 237086106 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.1860680987 Aug 23 09:52:38 AM UTC 24 Aug 23 09:52:49 AM UTC 24 4922712370 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.1546585479 Aug 23 09:52:48 AM UTC 24 Aug 23 09:52:50 AM UTC 24 104987049 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.2995631092 Aug 23 09:52:41 AM UTC 24 Aug 23 09:52:50 AM UTC 24 307150073 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.1069537472 Aug 23 09:52:41 AM UTC 24 Aug 23 09:52:50 AM UTC 24 4569240562 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.520503758 Aug 23 09:52:49 AM UTC 24 Aug 23 09:52:51 AM UTC 24 40377171 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.3448710624 Aug 23 09:52:42 AM UTC 24 Aug 23 09:52:53 AM UTC 24 302469725 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.1686396816 Aug 23 09:52:51 AM UTC 24 Aug 23 09:52:53 AM UTC 24 62039047 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.3894694825 Aug 23 09:52:49 AM UTC 24 Aug 23 09:52:53 AM UTC 24 136896582 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.2390627255 Aug 23 09:52:34 AM UTC 24 Aug 23 09:52:56 AM UTC 24 536426755 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_errors.1499741952 Aug 23 09:52:51 AM UTC 24 Aug 23 09:52:58 AM UTC 24 188190872 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.189167208 Aug 23 09:52:52 AM UTC 24 Aug 23 09:52:59 AM UTC 24 220057870 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.1918190357 Aug 23 09:52:17 AM UTC 24 Aug 23 09:53:00 AM UTC 24 2438687429 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.444584676 Aug 23 09:53:00 AM UTC 24 Aug 23 09:53:02 AM UTC 24 48688002 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.2780820487 Aug 23 09:52:54 AM UTC 24 Aug 23 09:53:03 AM UTC 24 1029767673 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.3754674352 Aug 23 09:51:26 AM UTC 24 Aug 23 09:53:04 AM UTC 24 3602782084 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2577740187 Aug 23 09:53:02 AM UTC 24 Aug 23 09:53:04 AM UTC 24 36623392 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.218141376 Aug 23 09:53:01 AM UTC 24 Aug 23 09:53:04 AM UTC 24 48618717 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.3642141489 Aug 23 09:52:52 AM UTC 24 Aug 23 09:53:04 AM UTC 24 551958288 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.154871746 Aug 23 09:51:39 AM UTC 24 Aug 23 09:53:05 AM UTC 24 4179201940 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.2210482018 Aug 23 09:52:54 AM UTC 24 Aug 23 09:53:06 AM UTC 24 607660912 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.987816410 Aug 23 09:52:53 AM UTC 24 Aug 23 09:53:06 AM UTC 24 411436948 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.2672960063 Aug 23 09:50:29 AM UTC 24 Aug 23 09:53:06 AM UTC 24 4896512505 ps
T507 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.3620189061 Aug 23 09:53:05 AM UTC 24 Aug 23 09:53:07 AM UTC 24 20853044 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.1115479265 Aug 23 09:52:49 AM UTC 24 Aug 23 09:53:09 AM UTC 24 163765170 ps
T509 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.2270665862 Aug 23 09:53:05 AM UTC 24 Aug 23 09:53:09 AM UTC 24 164256666 ps
T510 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.1058580991 Aug 23 09:53:09 AM UTC 24 Aug 23 09:53:11 AM UTC 24 22171528 ps
T511 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.1398632726 Aug 23 09:53:06 AM UTC 24 Aug 23 09:53:13 AM UTC 24 486987035 ps
T512 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.269584040 Aug 23 09:53:06 AM UTC 24 Aug 23 09:53:15 AM UTC 24 341297071 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.1294322104 Aug 23 09:53:12 AM UTC 24 Aug 23 09:53:15 AM UTC 24 38946343 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.586684609 Aug 23 09:53:14 AM UTC 24 Aug 23 09:53:15 AM UTC 24 54638647 ps
T515 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.2566613562 Aug 23 09:53:07 AM UTC 24 Aug 23 09:53:16 AM UTC 24 1044190193 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.3281990158 Aug 23 09:53:07 AM UTC 24 Aug 23 09:53:17 AM UTC 24 640893563 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_errors.2810361057 Aug 23 09:53:05 AM UTC 24 Aug 23 09:53:18 AM UTC 24 1336843341 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.174691429 Aug 23 09:53:16 AM UTC 24 Aug 23 09:53:18 AM UTC 24 91847078 ps
T518 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.2938288801 Aug 23 09:53:08 AM UTC 24 Aug 23 09:53:21 AM UTC 24 592784959 ps
T519 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.3885373623 Aug 23 09:53:16 AM UTC 24 Aug 23 09:53:23 AM UTC 24 145085235 ps
T520 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.2678423909 Aug 23 09:53:20 AM UTC 24 Aug 23 09:53:26 AM UTC 24 486393515 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.285580771 Aug 23 09:53:17 AM UTC 24 Aug 23 09:53:27 AM UTC 24 1388310425 ps
T522 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.1878811181 Aug 23 09:53:17 AM UTC 24 Aug 23 09:53:28 AM UTC 24 2808177980 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.3478242082 Aug 23 09:53:21 AM UTC 24 Aug 23 09:53:29 AM UTC 24 498130990 ps
T524 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.170780563 Aug 23 09:53:05 AM UTC 24 Aug 23 09:53:29 AM UTC 24 461314346 ps
T525 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.3534788660 Aug 23 09:53:28 AM UTC 24 Aug 23 09:53:30 AM UTC 24 26154500 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.1306578668 Aug 23 09:53:29 AM UTC 24 Aug 23 09:53:31 AM UTC 24 112105025 ps
T527 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.70915752 Aug 23 09:52:21 AM UTC 24 Aug 23 09:53:32 AM UTC 24 2866302660 ps
T528 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2825426303 Aug 23 09:53:30 AM UTC 24 Aug 23 09:53:32 AM UTC 24 51926008 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3453279579 Aug 23 09:52:31 AM UTC 24 Aug 23 09:53:33 AM UTC 24 12036966601 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.2200063389 Aug 23 09:53:33 AM UTC 24 Aug 23 09:53:35 AM UTC 24 118754505 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.2748958321 Aug 23 09:53:22 AM UTC 24 Aug 23 09:53:36 AM UTC 24 436604862 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.2873341784 Aug 23 09:53:20 AM UTC 24 Aug 23 09:53:37 AM UTC 24 792975984 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.2864636297 Aug 23 09:53:34 AM UTC 24 Aug 23 09:53:38 AM UTC 24 527305556 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.1822763640 Aug 23 09:53:30 AM UTC 24 Aug 23 09:53:39 AM UTC 24 271683775 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.2224834093 Aug 23 09:53:16 AM UTC 24 Aug 23 09:53:41 AM UTC 24 1156004526 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.4141414106 Aug 23 09:53:40 AM UTC 24 Aug 23 09:53:42 AM UTC 24 143216308 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.1600858326 Aug 23 09:53:33 AM UTC 24 Aug 23 09:53:43 AM UTC 24 1756065334 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.1661401325 Aug 23 09:53:33 AM UTC 24 Aug 23 09:53:43 AM UTC 24 295613132 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2015998009 Aug 23 09:53:42 AM UTC 24 Aug 23 09:53:44 AM UTC 24 14907853 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.2640631873 Aug 23 09:53:42 AM UTC 24 Aug 23 09:53:46 AM UTC 24 38850517 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.3191223566 Aug 23 09:53:36 AM UTC 24 Aug 23 09:53:47 AM UTC 24 1557865550 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.4122445805 Aug 23 09:53:45 AM UTC 24 Aug 23 09:53:47 AM UTC 24 84760923 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.1176337136 Aug 23 09:53:48 AM UTC 24 Aug 23 09:53:51 AM UTC 24 276514228 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.3954789662 Aug 23 09:53:44 AM UTC 24 Aug 23 09:53:51 AM UTC 24 455601978 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.1857038105 Aug 23 09:53:35 AM UTC 24 Aug 23 09:53:56 AM UTC 24 1178569151 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.3187378038 Aug 23 09:53:37 AM UTC 24 Aug 23 09:53:56 AM UTC 24 824356882 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_errors.894534038 Aug 23 09:53:47 AM UTC 24 Aug 23 09:53:58 AM UTC 24 288928304 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.2383574946 Aug 23 09:53:30 AM UTC 24 Aug 23 09:53:58 AM UTC 24 249198794 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.55114594 Aug 23 09:53:48 AM UTC 24 Aug 23 09:53:58 AM UTC 24 378136319 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.2266738818 Aug 23 09:53:59 AM UTC 24 Aug 23 09:54:03 AM UTC 24 43558817 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.749617967 Aug 23 09:53:52 AM UTC 24 Aug 23 09:54:04 AM UTC 24 660819162 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1962087205 Aug 23 09:54:03 AM UTC 24 Aug 23 09:54:05 AM UTC 24 29371242 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.2002056643 Aug 23 09:53:57 AM UTC 24 Aug 23 09:54:06 AM UTC 24 219422007 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.1016801833 Aug 23 09:54:06 AM UTC 24 Aug 23 09:54:09 AM UTC 24 35440850 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.2854006047 Aug 23 09:53:52 AM UTC 24 Aug 23 09:54:11 AM UTC 24 1087010800 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.3253182742 Aug 23 09:54:05 AM UTC 24 Aug 23 09:54:12 AM UTC 24 260136944 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.3459406878 Aug 23 09:53:43 AM UTC 24 Aug 23 09:54:12 AM UTC 24 291195651 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3091467782 Aug 23 09:53:39 AM UTC 24 Aug 23 09:54:13 AM UTC 24 1729685401 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.3199390895 Aug 23 09:54:12 AM UTC 24 Aug 23 09:54:14 AM UTC 24 59960118 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.3656494421 Aug 23 09:53:59 AM UTC 24 Aug 23 09:54:15 AM UTC 24 4165519050 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_errors.1824957071 Aug 23 09:54:06 AM UTC 24 Aug 23 09:54:19 AM UTC 24 382941971 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.318231011 Aug 23 09:54:09 AM UTC 24 Aug 23 09:54:19 AM UTC 24 982186001 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.3026734144 Aug 23 09:54:20 AM UTC 24 Aug 23 09:54:21 AM UTC 24 84775091 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.1110548419 Aug 23 09:54:13 AM UTC 24 Aug 23 09:54:22 AM UTC 24 391256482 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.2851277557 Aug 23 09:53:08 AM UTC 24 Aug 23 09:54:22 AM UTC 24 6105793361 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.3667712861 Aug 23 09:54:21 AM UTC 24 Aug 23 09:54:24 AM UTC 24 215238354 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2241869011 Aug 23 09:54:22 AM UTC 24 Aug 23 09:54:24 AM UTC 24 36952914 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.378985744 Aug 23 09:52:08 AM UTC 24 Aug 23 09:54:25 AM UTC 24 19571746799 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.2870196490 Aug 23 09:54:14 AM UTC 24 Aug 23 09:54:26 AM UTC 24 424632393 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.3445580867 Aug 23 09:54:04 AM UTC 24 Aug 23 09:54:26 AM UTC 24 1515751055 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.540482143 Aug 23 09:54:13 AM UTC 24 Aug 23 09:54:26 AM UTC 24 1048024867 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.1152861646 Aug 23 09:55:37 AM UTC 24 Aug 23 09:55:45 AM UTC 24 221530327 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.3512338499 Aug 23 09:54:25 AM UTC 24 Aug 23 09:54:29 AM UTC 24 389803996 ps
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