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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.29 97.99 95.86 93.40 100.00 98.55 98.76 96.47


Total test records in report: 998
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T805 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.1224415757 Aug 23 09:59:02 AM UTC 24 Aug 23 09:59:12 AM UTC 24 1072652846 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.4155519417 Aug 23 09:59:09 AM UTC 24 Aug 23 09:59:13 AM UTC 24 45615700 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.4088387459 Aug 23 09:59:12 AM UTC 24 Aug 23 09:59:15 AM UTC 24 171264560 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.2421396599 Aug 23 09:59:10 AM UTC 24 Aug 23 09:59:17 AM UTC 24 203762928 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.244261034 Aug 23 09:59:09 AM UTC 24 Aug 23 09:59:18 AM UTC 24 84012485 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.2213390136 Aug 23 09:59:10 AM UTC 24 Aug 23 09:59:20 AM UTC 24 2068978238 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.804917051 Aug 23 09:59:19 AM UTC 24 Aug 23 09:59:20 AM UTC 24 40183989 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.3945843176 Aug 23 09:59:13 AM UTC 24 Aug 23 09:59:22 AM UTC 24 249162525 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.1938409456 Aug 23 09:59:13 AM UTC 24 Aug 23 09:59:23 AM UTC 24 1025605830 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2871638389 Aug 23 09:59:21 AM UTC 24 Aug 23 09:59:23 AM UTC 24 48343495 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.1421964630 Aug 23 09:58:58 AM UTC 24 Aug 23 09:59:25 AM UTC 24 323445167 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.1455508429 Aug 23 09:59:21 AM UTC 24 Aug 23 09:59:26 AM UTC 24 545207581 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.2719596588 Aug 23 09:59:24 AM UTC 24 Aug 23 09:59:27 AM UTC 24 59185955 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.1450627027 Aug 23 09:59:13 AM UTC 24 Aug 23 09:59:28 AM UTC 24 386768906 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.1925123187 Aug 23 09:57:58 AM UTC 24 Aug 23 09:59:30 AM UTC 24 3199979315 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.2235572942 Aug 23 09:59:24 AM UTC 24 Aug 23 09:59:31 AM UTC 24 63678629 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.1492009200 Aug 23 09:58:53 AM UTC 24 Aug 23 09:59:32 AM UTC 24 1608631782 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.1807783166 Aug 23 09:59:09 AM UTC 24 Aug 23 09:59:33 AM UTC 24 504743975 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.952703724 Aug 23 09:59:26 AM UTC 24 Aug 23 09:59:34 AM UTC 24 413922131 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.2897724890 Aug 23 09:59:34 AM UTC 24 Aug 23 09:59:35 AM UTC 24 206564627 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.1258018455 Aug 23 09:59:26 AM UTC 24 Aug 23 09:59:36 AM UTC 24 466488485 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.2145955953 Aug 23 09:59:29 AM UTC 24 Aug 23 09:59:37 AM UTC 24 306694155 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.1698779119 Aug 23 09:59:35 AM UTC 24 Aug 23 09:59:38 AM UTC 24 53899264 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.3747606181 Aug 23 09:59:26 AM UTC 24 Aug 23 09:59:38 AM UTC 24 918229844 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2107365458 Aug 23 09:59:36 AM UTC 24 Aug 23 09:59:38 AM UTC 24 144245823 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.225857408 Aug 23 09:59:29 AM UTC 24 Aug 23 09:59:39 AM UTC 24 844433389 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.445717671 Aug 23 09:59:31 AM UTC 24 Aug 23 09:59:39 AM UTC 24 318826463 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.3227177521 Aug 23 09:59:39 AM UTC 24 Aug 23 09:59:42 AM UTC 24 40470720 ps
T832 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.984412989 Aug 23 09:59:06 AM UTC 24 Aug 23 09:59:43 AM UTC 24 5985483556 ps
T833 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.4106296691 Aug 23 09:59:40 AM UTC 24 Aug 23 09:59:43 AM UTC 24 162606053 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.4058109787 Aug 23 09:59:39 AM UTC 24 Aug 23 09:59:48 AM UTC 24 136597520 ps
T835 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.2935580952 Aug 23 09:59:43 AM UTC 24 Aug 23 09:59:49 AM UTC 24 217402488 ps
T836 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.1580641605 Aug 23 09:59:39 AM UTC 24 Aug 23 09:59:49 AM UTC 24 261707282 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.1856287804 Aug 23 09:59:22 AM UTC 24 Aug 23 09:59:49 AM UTC 24 232281503 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.3638454493 Aug 23 09:59:39 AM UTC 24 Aug 23 09:59:51 AM UTC 24 869593959 ps
T839 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.3378484327 Aug 23 09:59:40 AM UTC 24 Aug 23 09:59:51 AM UTC 24 1314901399 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2207160430 Aug 23 09:59:50 AM UTC 24 Aug 23 09:59:52 AM UTC 24 45051492 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.1833843408 Aug 23 09:59:50 AM UTC 24 Aug 23 09:59:52 AM UTC 24 72579695 ps
T842 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.2845564304 Aug 23 09:59:50 AM UTC 24 Aug 23 09:59:52 AM UTC 24 38447928 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.1796036629 Aug 23 09:58:26 AM UTC 24 Aug 23 09:59:53 AM UTC 24 7738960304 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.1466909273 Aug 23 09:59:44 AM UTC 24 Aug 23 09:59:53 AM UTC 24 264184443 ps
T845 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.233137844 Aug 23 09:59:51 AM UTC 24 Aug 23 09:59:55 AM UTC 24 57107000 ps
T846 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.637567465 Aug 23 09:59:51 AM UTC 24 Aug 23 09:59:55 AM UTC 24 53857894 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.462888655 Aug 23 09:59:53 AM UTC 24 Aug 23 10:00:00 AM UTC 24 285840325 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.1047869671 Aug 23 09:59:54 AM UTC 24 Aug 23 10:00:02 AM UTC 24 805800603 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.2523232271 Aug 23 09:59:53 AM UTC 24 Aug 23 10:00:04 AM UTC 24 1341652972 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.3770670895 Aug 23 09:59:56 AM UTC 24 Aug 23 10:00:05 AM UTC 24 1127310222 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.3802686610 Aug 23 09:59:36 AM UTC 24 Aug 23 10:00:06 AM UTC 24 1350264783 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.4150658452 Aug 23 10:00:01 AM UTC 24 Aug 23 10:00:08 AM UTC 24 60582527 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.1499327018 Aug 23 09:59:54 AM UTC 24 Aug 23 10:00:08 AM UTC 24 1375803950 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.2033043902 Aug 23 09:59:51 AM UTC 24 Aug 23 10:00:16 AM UTC 24 1936154056 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1819488456 Aug 23 09:59:48 AM UTC 24 Aug 23 10:00:29 AM UTC 24 4081355762 ps
T856 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.3769118213 Aug 23 09:57:58 AM UTC 24 Aug 23 10:00:37 AM UTC 24 42495671718 ps
T857 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.3454007054 Aug 23 09:59:57 AM UTC 24 Aug 23 10:00:37 AM UTC 24 1433922324 ps
T858 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.687937537 Aug 23 09:59:31 AM UTC 24 Aug 23 10:00:59 AM UTC 24 5175835638 ps
T859 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.1034191260 Aug 23 09:59:04 AM UTC 24 Aug 23 10:01:01 AM UTC 24 11514544124 ps
T860 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.3424319838 Aug 23 09:55:54 AM UTC 24 Aug 23 10:01:37 AM UTC 24 37207450448 ps
T861 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.3725985793 Aug 23 09:59:15 AM UTC 24 Aug 23 10:01:49 AM UTC 24 4941810118 ps
T862 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.882300229 Aug 23 09:56:21 AM UTC 24 Aug 23 10:02:05 AM UTC 24 99394125754 ps
T863 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.4057927550 Aug 23 09:59:44 AM UTC 24 Aug 23 10:02:40 AM UTC 24 9567218111 ps
T864 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.1619282035 Aug 23 09:58:09 AM UTC 24 Aug 23 10:02:55 AM UTC 24 40415209456 ps
T865 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.2501718207 Aug 23 09:57:17 AM UTC 24 Aug 23 10:03:03 AM UTC 24 14756888263 ps
T866 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.1515236846 Aug 23 09:53:39 AM UTC 24 Aug 23 10:03:09 AM UTC 24 120461842294 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.35322328 Aug 23 08:16:56 AM UTC 24 Aug 23 08:16:58 AM UTC 24 505846057 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2948976306 Aug 23 08:16:56 AM UTC 24 Aug 23 08:16:59 AM UTC 24 163518046 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3324430172 Aug 23 08:16:58 AM UTC 24 Aug 23 08:17:01 AM UTC 24 84728744 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3824479694 Aug 23 08:17:00 AM UTC 24 Aug 23 08:17:03 AM UTC 24 354889679 ps
T867 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2171956451 Aug 23 08:17:00 AM UTC 24 Aug 23 08:17:03 AM UTC 24 168442227 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.86156418 Aug 23 08:17:02 AM UTC 24 Aug 23 08:17:04 AM UTC 24 18688584 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1862030787 Aug 23 08:17:00 AM UTC 24 Aug 23 08:17:04 AM UTC 24 98863474 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.497439935 Aug 23 08:17:03 AM UTC 24 Aug 23 08:17:05 AM UTC 24 15977302 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.418314710 Aug 23 08:17:02 AM UTC 24 Aug 23 08:17:05 AM UTC 24 260059527 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.165521604 Aug 23 08:17:04 AM UTC 24 Aug 23 08:17:06 AM UTC 24 38274256 ps
T868 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1783251044 Aug 23 08:17:04 AM UTC 24 Aug 23 08:17:06 AM UTC 24 21541431 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1280758722 Aug 23 08:17:04 AM UTC 24 Aug 23 08:17:07 AM UTC 24 174219037 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3218382906 Aug 23 08:17:04 AM UTC 24 Aug 23 08:17:07 AM UTC 24 34844139 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.378545567 Aug 23 08:16:56 AM UTC 24 Aug 23 08:17:07 AM UTC 24 6493043165 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.557965733 Aug 23 08:17:05 AM UTC 24 Aug 23 08:17:07 AM UTC 24 108075723 ps
T869 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3392050071 Aug 23 08:17:05 AM UTC 24 Aug 23 08:17:08 AM UTC 24 1013391820 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.501656617 Aug 23 08:17:07 AM UTC 24 Aug 23 08:17:10 AM UTC 24 23235433 ps
T870 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1708607002 Aug 23 08:17:08 AM UTC 24 Aug 23 08:17:10 AM UTC 24 180681656 ps
T871 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3284721565 Aug 23 08:17:06 AM UTC 24 Aug 23 08:17:10 AM UTC 24 191831804 ps
T872 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1382461627 Aug 23 08:17:09 AM UTC 24 Aug 23 08:17:11 AM UTC 24 87740913 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2828209106 Aug 23 08:17:09 AM UTC 24 Aug 23 08:17:11 AM UTC 24 31453813 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2284930934 Aug 23 08:17:08 AM UTC 24 Aug 23 08:17:11 AM UTC 24 394513523 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.452866332 Aug 23 08:17:08 AM UTC 24 Aug 23 08:17:12 AM UTC 24 1286436283 ps
T873 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2579485970 Aug 23 08:17:05 AM UTC 24 Aug 23 08:17:13 AM UTC 24 2355030263 ps
T874 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2251551115 Aug 23 08:16:58 AM UTC 24 Aug 23 08:17:13 AM UTC 24 1471239701 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.958478196 Aug 23 08:17:11 AM UTC 24 Aug 23 08:17:13 AM UTC 24 48312137 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2460522449 Aug 23 08:17:11 AM UTC 24 Aug 23 08:17:13 AM UTC 24 59431146 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2676879410 Aug 23 08:17:11 AM UTC 24 Aug 23 08:17:14 AM UTC 24 38278755 ps
T875 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2101987263 Aug 23 08:17:11 AM UTC 24 Aug 23 08:17:14 AM UTC 24 442474599 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.584546652 Aug 23 08:17:09 AM UTC 24 Aug 23 08:17:14 AM UTC 24 207532337 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1466106111 Aug 23 08:17:12 AM UTC 24 Aug 23 08:17:14 AM UTC 24 54237579 ps
T876 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1058459901 Aug 23 08:17:11 AM UTC 24 Aug 23 08:17:15 AM UTC 24 108114208 ps
T877 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3916273797 Aug 23 08:17:14 AM UTC 24 Aug 23 08:17:16 AM UTC 24 17076997 ps
T878 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3712672224 Aug 23 08:17:14 AM UTC 24 Aug 23 08:17:16 AM UTC 24 297179246 ps
T879 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.795854035 Aug 23 08:17:12 AM UTC 24 Aug 23 08:17:16 AM UTC 24 415489103 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3076356329 Aug 23 08:17:14 AM UTC 24 Aug 23 08:17:16 AM UTC 24 25063169 ps
T880 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1398209968 Aug 23 08:17:15 AM UTC 24 Aug 23 08:17:17 AM UTC 24 50444770 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1545985169 Aug 23 08:17:14 AM UTC 24 Aug 23 08:17:17 AM UTC 24 79332174 ps
T881 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1929387540 Aug 23 08:17:15 AM UTC 24 Aug 23 08:17:17 AM UTC 24 17407896 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2728429562 Aug 23 08:17:15 AM UTC 24 Aug 23 08:17:17 AM UTC 24 24757395 ps
T882 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1198508382 Aug 23 08:17:15 AM UTC 24 Aug 23 08:17:17 AM UTC 24 75517479 ps
T883 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2373713205 Aug 23 08:17:12 AM UTC 24 Aug 23 08:17:17 AM UTC 24 158017572 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1036085659 Aug 23 08:17:14 AM UTC 24 Aug 23 08:17:17 AM UTC 24 289786682 ps
T884 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.661096739 Aug 23 08:17:12 AM UTC 24 Aug 23 08:17:18 AM UTC 24 2457860694 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1880398643 Aug 23 08:17:16 AM UTC 24 Aug 23 08:17:18 AM UTC 24 23715287 ps
T885 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1865619349 Aug 23 08:17:16 AM UTC 24 Aug 23 08:17:18 AM UTC 24 52712828 ps
T886 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2397261343 Aug 23 08:17:18 AM UTC 24 Aug 23 08:17:19 AM UTC 24 109268876 ps
T887 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4028547979 Aug 23 08:17:16 AM UTC 24 Aug 23 08:17:20 AM UTC 24 82573505 ps
T888 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2525407045 Aug 23 08:17:18 AM UTC 24 Aug 23 08:17:20 AM UTC 24 29657173 ps
T889 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1431121245 Aug 23 08:17:18 AM UTC 24 Aug 23 08:17:20 AM UTC 24 89897171 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3230127402 Aug 23 08:17:17 AM UTC 24 Aug 23 08:17:20 AM UTC 24 137669897 ps
T890 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3883708961 Aug 23 08:17:18 AM UTC 24 Aug 23 08:17:20 AM UTC 24 38378319 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.718482412 Aug 23 08:17:18 AM UTC 24 Aug 23 08:17:20 AM UTC 24 91068000 ps
T891 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3638303444 Aug 23 08:17:18 AM UTC 24 Aug 23 08:17:20 AM UTC 24 102364093 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.33008093 Aug 23 08:17:18 AM UTC 24 Aug 23 08:17:20 AM UTC 24 229831518 ps
T892 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.109746114 Aug 23 08:17:19 AM UTC 24 Aug 23 08:17:21 AM UTC 24 45476544 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2385496919 Aug 23 08:17:19 AM UTC 24 Aug 23 08:17:21 AM UTC 24 71617424 ps
T893 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1752975882 Aug 23 08:17:19 AM UTC 24 Aug 23 08:17:21 AM UTC 24 96959058 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.327315734 Aug 23 08:17:20 AM UTC 24 Aug 23 08:17:22 AM UTC 24 32330298 ps
T894 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1010033011 Aug 23 08:17:19 AM UTC 24 Aug 23 08:17:22 AM UTC 24 96392273 ps
T895 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1913591142 Aug 23 08:17:17 AM UTC 24 Aug 23 08:17:23 AM UTC 24 365831476 ps
T896 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1748365460 Aug 23 08:17:20 AM UTC 24 Aug 23 08:17:23 AM UTC 24 421047627 ps
T897 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4217225364 Aug 23 08:17:22 AM UTC 24 Aug 23 08:17:24 AM UTC 24 12751755 ps
T898 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2812562128 Aug 23 08:17:22 AM UTC 24 Aug 23 08:17:24 AM UTC 24 73932904 ps
T899 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4097287139 Aug 23 08:17:22 AM UTC 24 Aug 23 08:17:24 AM UTC 24 22294849 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2552318677 Aug 23 08:17:22 AM UTC 24 Aug 23 08:17:24 AM UTC 24 243279714 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2542679578 Aug 23 08:17:22 AM UTC 24 Aug 23 08:17:24 AM UTC 24 64630319 ps
T900 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3094059088 Aug 23 08:17:22 AM UTC 24 Aug 23 08:17:24 AM UTC 24 59116211 ps
T901 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2554891433 Aug 23 08:17:22 AM UTC 24 Aug 23 08:17:24 AM UTC 24 81281861 ps
T902 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3613670114 Aug 23 08:17:22 AM UTC 24 Aug 23 08:17:25 AM UTC 24 184676783 ps
T903 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3147000822 Aug 23 08:17:23 AM UTC 24 Aug 23 08:17:25 AM UTC 24 40556535 ps
T904 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3088841780 Aug 23 08:17:22 AM UTC 24 Aug 23 08:17:25 AM UTC 24 90765635 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2008831948 Aug 23 08:17:22 AM UTC 24 Aug 23 08:17:25 AM UTC 24 393518480 ps
T905 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1470682764 Aug 23 08:17:20 AM UTC 24 Aug 23 08:17:26 AM UTC 24 2302505627 ps
T906 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.149274164 Aug 23 08:17:23 AM UTC 24 Aug 23 08:17:26 AM UTC 24 46596423 ps
T907 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3853170779 Aug 23 08:17:25 AM UTC 24 Aug 23 08:17:27 AM UTC 24 69946829 ps
T908 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3874002366 Aug 23 08:17:16 AM UTC 24 Aug 23 08:17:26 AM UTC 24 1861677322 ps
T909 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3891483042 Aug 23 08:17:20 AM UTC 24 Aug 23 08:17:26 AM UTC 24 489654515 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3872964293 Aug 23 08:17:23 AM UTC 24 Aug 23 08:17:27 AM UTC 24 152699466 ps
T910 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.806497603 Aug 23 08:17:23 AM UTC 24 Aug 23 08:17:27 AM UTC 24 152992770 ps
T911 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2541176954 Aug 23 08:17:25 AM UTC 24 Aug 23 08:17:27 AM UTC 24 157687655 ps
T912 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.66820532 Aug 23 08:17:23 AM UTC 24 Aug 23 08:17:27 AM UTC 24 92085995 ps
T913 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1861597340 Aug 23 08:17:25 AM UTC 24 Aug 23 08:17:27 AM UTC 24 24548584 ps
T914 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.404228463 Aug 23 08:17:25 AM UTC 24 Aug 23 08:17:27 AM UTC 24 25710215 ps
T915 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3439666289 Aug 23 08:17:25 AM UTC 24 Aug 23 08:17:27 AM UTC 24 107979700 ps
T916 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3774359501 Aug 23 08:17:25 AM UTC 24 Aug 23 08:17:28 AM UTC 24 89905320 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.738927862 Aug 23 08:17:26 AM UTC 24 Aug 23 08:17:28 AM UTC 24 20018188 ps
T917 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3589340606 Aug 23 08:17:26 AM UTC 24 Aug 23 08:17:28 AM UTC 24 103653304 ps
T918 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1556876233 Aug 23 08:17:26 AM UTC 24 Aug 23 08:17:28 AM UTC 24 51185635 ps
T919 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.606839753 Aug 23 08:17:26 AM UTC 24 Aug 23 08:17:29 AM UTC 24 23332348 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.926571344 Aug 23 08:17:26 AM UTC 24 Aug 23 08:17:29 AM UTC 24 165727552 ps
T920 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4249084491 Aug 23 08:17:22 AM UTC 24 Aug 23 08:17:29 AM UTC 24 3293209559 ps
T921 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.977576216 Aug 23 08:17:26 AM UTC 24 Aug 23 08:17:29 AM UTC 24 70445003 ps
T922 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1288179934 Aug 23 08:17:27 AM UTC 24 Aug 23 08:17:29 AM UTC 24 61552111 ps
T923 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2306543430 Aug 23 08:17:37 AM UTC 24 Aug 23 08:17:40 AM UTC 24 50416612 ps
T924 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3212597675 Aug 23 08:17:27 AM UTC 24 Aug 23 08:17:30 AM UTC 24 50099370 ps
T925 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2682677630 Aug 23 08:17:26 AM UTC 24 Aug 23 08:17:30 AM UTC 24 509510225 ps
T926 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2070102539 Aug 23 08:17:27 AM UTC 24 Aug 23 08:17:30 AM UTC 24 53583277 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2417564132 Aug 23 08:17:29 AM UTC 24 Aug 23 08:17:30 AM UTC 24 22770424 ps
T927 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1743928277 Aug 23 08:17:26 AM UTC 24 Aug 23 08:17:30 AM UTC 24 511599479 ps
T928 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2914843187 Aug 23 08:17:29 AM UTC 24 Aug 23 08:17:31 AM UTC 24 30267919 ps
T929 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.264579082 Aug 23 08:17:25 AM UTC 24 Aug 23 08:17:31 AM UTC 24 1775959097 ps
T930 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.918257069 Aug 23 08:17:29 AM UTC 24 Aug 23 08:17:31 AM UTC 24 110186211 ps
T931 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.541811724 Aug 23 08:17:28 AM UTC 24 Aug 23 08:17:31 AM UTC 24 132134572 ps
T932 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3945943266 Aug 23 08:17:29 AM UTC 24 Aug 23 08:17:31 AM UTC 24 94267405 ps
T933 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1626270090 Aug 23 08:17:25 AM UTC 24 Aug 23 08:17:31 AM UTC 24 2012183961 ps
T934 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2547659245 Aug 23 08:17:30 AM UTC 24 Aug 23 08:17:32 AM UTC 24 100276806 ps
T935 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3040891330 Aug 23 08:17:29 AM UTC 24 Aug 23 08:17:32 AM UTC 24 80741195 ps
T936 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3106892432 Aug 23 08:17:30 AM UTC 24 Aug 23 08:17:32 AM UTC 24 226787222 ps
T937 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2313952000 Aug 23 08:17:28 AM UTC 24 Aug 23 08:17:32 AM UTC 24 623596691 ps
T938 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4172590646 Aug 23 08:17:27 AM UTC 24 Aug 23 08:17:33 AM UTC 24 633921684 ps
T939 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.171974033 Aug 23 08:17:31 AM UTC 24 Aug 23 08:17:33 AM UTC 24 14968821 ps
T940 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.627996457 Aug 23 08:17:31 AM UTC 24 Aug 23 08:17:33 AM UTC 24 25529157 ps
T941 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1855605502 Aug 23 08:17:31 AM UTC 24 Aug 23 08:17:33 AM UTC 24 58167062 ps
T942 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.941465144 Aug 23 08:17:30 AM UTC 24 Aug 23 08:17:33 AM UTC 24 414526346 ps
T943 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4137719645 Aug 23 08:17:23 AM UTC 24 Aug 23 08:17:34 AM UTC 24 7478145737 ps
T944 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3492938810 Aug 23 08:17:27 AM UTC 24 Aug 23 08:17:34 AM UTC 24 1022765162 ps
T945 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3539251897 Aug 23 08:17:32 AM UTC 24 Aug 23 08:17:35 AM UTC 24 30661879 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2443078660 Aug 23 08:17:31 AM UTC 24 Aug 23 08:17:35 AM UTC 24 95575210 ps
T946 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2169338775 Aug 23 08:17:32 AM UTC 24 Aug 23 08:17:35 AM UTC 24 42949786 ps
T947 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.266892105 Aug 23 08:17:31 AM UTC 24 Aug 23 08:17:35 AM UTC 24 827468060 ps
T948 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2535115171 Aug 23 08:17:34 AM UTC 24 Aug 23 08:17:35 AM UTC 24 152828923 ps
T949 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1361842651 Aug 23 08:17:32 AM UTC 24 Aug 23 08:17:35 AM UTC 24 267246065 ps
T950 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.603713989 Aug 23 08:17:30 AM UTC 24 Aug 23 08:17:35 AM UTC 24 520544607 ps
T951 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3841400629 Aug 23 08:17:32 AM UTC 24 Aug 23 08:17:36 AM UTC 24 777483767 ps
T952 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1948982573 Aug 23 08:17:34 AM UTC 24 Aug 23 08:17:36 AM UTC 24 40623700 ps
T953 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1911634799 Aug 23 08:17:36 AM UTC 24 Aug 23 08:17:40 AM UTC 24 129427170 ps
T954 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3219065423 Aug 23 08:17:37 AM UTC 24 Aug 23 08:17:40 AM UTC 24 27467304 ps
T955 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3742609537 Aug 23 08:17:34 AM UTC 24 Aug 23 08:17:36 AM UTC 24 77734252 ps
T956 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1304625069 Aug 23 08:17:34 AM UTC 24 Aug 23 08:17:36 AM UTC 24 219784398 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3978045502 Aug 23 08:17:33 AM UTC 24 Aug 23 08:17:36 AM UTC 24 156507242 ps
T957 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1473758170 Aug 23 08:17:35 AM UTC 24 Aug 23 08:17:36 AM UTC 24 41992240 ps
T958 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3787672255 Aug 23 08:17:20 AM UTC 24 Aug 23 08:17:37 AM UTC 24 2935375987 ps
T959 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.950226585 Aug 23 08:17:34 AM UTC 24 Aug 23 08:17:37 AM UTC 24 58043562 ps
T960 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2979928866 Aug 23 08:17:35 AM UTC 24 Aug 23 08:17:37 AM UTC 24 48707047 ps
T961 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2840688351 Aug 23 08:17:35 AM UTC 24 Aug 23 08:17:37 AM UTC 24 28965882 ps
T962 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2099808363 Aug 23 08:17:16 AM UTC 24 Aug 23 08:17:37 AM UTC 24 1750907993 ps
T963 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3502264895 Aug 23 08:17:39 AM UTC 24 Aug 23 08:17:40 AM UTC 24 42820400 ps
T964 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2247472023 Aug 23 08:17:33 AM UTC 24 Aug 23 08:17:37 AM UTC 24 389987863 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3999499273 Aug 23 08:17:36 AM UTC 24 Aug 23 08:17:38 AM UTC 24 18927626 ps
T965 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.746928779 Aug 23 08:17:36 AM UTC 24 Aug 23 08:17:38 AM UTC 24 53066122 ps
T966 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3523262123 Aug 23 08:17:35 AM UTC 24 Aug 23 08:17:38 AM UTC 24 146128521 ps
T967 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2982870711 Aug 23 08:17:36 AM UTC 24 Aug 23 08:17:38 AM UTC 24 15018326 ps
T968 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3597748536 Aug 23 08:17:36 AM UTC 24 Aug 23 08:17:38 AM UTC 24 21646075 ps
T969 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3196988288 Aug 23 08:17:36 AM UTC 24 Aug 23 08:17:38 AM UTC 24 53389007 ps
T970 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3463475047 Aug 23 08:17:36 AM UTC 24 Aug 23 08:17:38 AM UTC 24 22135560 ps
T971 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2174743633 Aug 23 08:17:37 AM UTC 24 Aug 23 08:17:39 AM UTC 24 25563930 ps
T972 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3469681937 Aug 23 08:17:37 AM UTC 24 Aug 23 08:17:39 AM UTC 24 161231453 ps
T973 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.147895958 Aug 23 08:17:37 AM UTC 24 Aug 23 08:17:39 AM UTC 24 76798184 ps
T974 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2398051109 Aug 23 08:17:37 AM UTC 24 Aug 23 08:17:39 AM UTC 24 78258579 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2209586386 Aug 23 08:17:36 AM UTC 24 Aug 23 08:17:40 AM UTC 24 299876086 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2468722965 Aug 23 08:17:37 AM UTC 24 Aug 23 08:17:40 AM UTC 24 44638737 ps
T975 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1057546586 Aug 23 08:17:38 AM UTC 24 Aug 23 08:17:40 AM UTC 24 17062247 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3933330172 Aug 23 08:17:36 AM UTC 24 Aug 23 08:17:40 AM UTC 24 80257227 ps
T976 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.157479701 Aug 23 08:17:39 AM UTC 24 Aug 23 08:17:41 AM UTC 24 113394441 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1110546151 Aug 23 08:17:37 AM UTC 24 Aug 23 08:17:41 AM UTC 24 581915341 ps
T977 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3891413448 Aug 23 08:17:39 AM UTC 24 Aug 23 08:17:41 AM UTC 24 49783766 ps
T978 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2613134705 Aug 23 08:17:39 AM UTC 24 Aug 23 08:17:41 AM UTC 24 46947151 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3617846943 Aug 23 08:17:40 AM UTC 24 Aug 23 08:17:42 AM UTC 24 48924508 ps
T979 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2638043595 Aug 23 08:17:37 AM UTC 24 Aug 23 08:17:42 AM UTC 24 297897410 ps
T980 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3509362094 Aug 23 08:17:40 AM UTC 24 Aug 23 08:17:42 AM UTC 24 50714651 ps
T981 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.4196054959 Aug 23 08:17:40 AM UTC 24 Aug 23 08:17:42 AM UTC 24 28760449 ps
T982 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3145480746 Aug 23 08:17:40 AM UTC 24 Aug 23 08:17:42 AM UTC 24 71998377 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.345542110 Aug 23 08:17:39 AM UTC 24 Aug 23 08:17:42 AM UTC 24 731975479 ps
T983 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2086492436 Aug 23 08:17:40 AM UTC 24 Aug 23 08:17:42 AM UTC 24 108908764 ps
T984 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2659590949 Aug 23 08:17:30 AM UTC 24 Aug 23 08:17:42 AM UTC 24 514086274 ps
T985 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.30565011 Aug 23 08:17:39 AM UTC 24 Aug 23 08:17:42 AM UTC 24 43203345 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.172351289 Aug 23 08:17:39 AM UTC 24 Aug 23 08:17:43 AM UTC 24 117751463 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.915678319 Aug 23 08:17:41 AM UTC 24 Aug 23 08:17:43 AM UTC 24 75830489 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.325546666 Aug 23 08:17:40 AM UTC 24 Aug 23 08:17:43 AM UTC 24 48157304 ps
T986 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3536025896 Aug 23 08:17:41 AM UTC 24 Aug 23 08:17:43 AM UTC 24 57457374 ps
T987 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.544475749 Aug 23 08:17:32 AM UTC 24 Aug 23 08:17:43 AM UTC 24 697831276 ps
T988 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.210627805 Aug 23 08:17:41 AM UTC 24 Aug 23 08:17:44 AM UTC 24 65660903 ps
T989 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.834478978 Aug 23 08:17:41 AM UTC 24 Aug 23 08:17:44 AM UTC 24 22756450 ps
T990 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3695787240 Aug 23 08:17:41 AM UTC 24 Aug 23 08:17:44 AM UTC 24 60738823 ps
T991 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2202023247 Aug 23 08:17:40 AM UTC 24 Aug 23 08:17:44 AM UTC 24 51175397 ps
T992 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1829126342 Aug 23 08:17:42 AM UTC 24 Aug 23 08:17:44 AM UTC 24 13272529 ps
T993 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3187813117 Aug 23 08:17:42 AM UTC 24 Aug 23 08:17:44 AM UTC 24 43893141 ps
T994 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3321897559 Aug 23 08:17:42 AM UTC 24 Aug 23 08:17:45 AM UTC 24 16129721 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4054067561 Aug 23 08:17:41 AM UTC 24 Aug 23 08:17:45 AM UTC 24 458504983 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1389269299 Aug 23 08:17:42 AM UTC 24 Aug 23 08:17:45 AM UTC 24 131469684 ps
T995 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1294345704 Aug 23 08:17:42 AM UTC 24 Aug 23 08:17:48 AM UTC 24 151795695 ps
T996 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3067716322 Aug 23 08:17:29 AM UTC 24 Aug 23 08:17:49 AM UTC 24 2082146769 ps
T997 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2515865298 Aug 23 08:17:27 AM UTC 24 Aug 23 08:17:55 AM UTC 24 1652633359 ps
T998 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2411628582 Aug 23 08:17:32 AM UTC 24 Aug 23 08:18:00 AM UTC 24 2687552797 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.414231388
Short name T15
Test name
Test status
Simulation time 579235572 ps
CPU time 9.61 seconds
Started Aug 23 09:41:19 AM UTC 24
Finished Aug 23 09:41:30 AM UTC 24
Peak memory 231888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414231388 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.414231388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.3703621760
Short name T19
Test name
Test status
Simulation time 6342332195 ps
CPU time 41.04 seconds
Started Aug 23 09:41:38 AM UTC 24
Finished Aug 23 09:42:20 AM UTC 24
Peak memory 231952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703621760
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jt
ag_errors.3703621760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.99363444
Short name T23
Test name
Test status
Simulation time 1076876375 ps
CPU time 9 seconds
Started Aug 23 09:41:48 AM UTC 24
Finished Aug 23 09:41:58 AM UTC 24
Peak memory 231992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99363444 -assert nopost
proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.99363444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.2355693193
Short name T45
Test name
Test status
Simulation time 355894797 ps
CPU time 26.85 seconds
Started Aug 23 09:42:09 AM UTC 24
Finished Aug 23 09:42:37 AM UTC 24
Peak memory 260452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355693193 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2355693193
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.1313348864
Short name T74
Test name
Test status
Simulation time 2355690175 ps
CPU time 78.54 seconds
Started Aug 23 09:42:00 AM UTC 24
Finished Aug 23 09:43:20 AM UTC 24
Peak memory 289180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1313348864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 0.lc_ctrl_stress_all.1313348864
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.1560467028
Short name T369
Test name
Test status
Simulation time 920162242 ps
CPU time 9.17 seconds
Started Aug 23 09:49:10 AM UTC 24
Finished Aug 23 09:49:21 AM UTC 24
Peak memory 232028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560467028 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1560467028
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3453279579
Short name T143
Test name
Test status
Simulation time 12036966601 ps
CPU time 60.05 seconds
Started Aug 23 09:52:31 AM UTC 24
Finished Aug 23 09:53:33 AM UTC 24
Peak memory 262764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453279579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_u
nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.3453279579
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.3135525744
Short name T9
Test name
Test status
Simulation time 648344442 ps
CPU time 4.42 seconds
Started Aug 23 09:42:38 AM UTC 24
Finished Aug 23 09:42:44 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135525744 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3135525744
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2541119592
Short name T34
Test name
Test status
Simulation time 37062192 ps
CPU time 0.68 seconds
Started Aug 23 09:42:07 AM UTC 24
Finished Aug 23 09:42:09 AM UTC 24
Peak memory 218972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541119592 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.
lc_ctrl_volatile_unlock_smoke.2541119592
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2043995154
Short name T46
Test name
Test status
Simulation time 1604591234 ps
CPU time 19.65 seconds
Started Aug 23 09:42:03 AM UTC 24
Finished Aug 23 09:42:24 AM UTC 24
Peak memory 290076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043995154 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2043995154
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.452866332
Short name T112
Test name
Test status
Simulation time 1286436283 ps
CPU time 3.79 seconds
Started Aug 23 08:17:08 AM UTC 24
Finished Aug 23 08:17:12 AM UTC 24
Peak memory 230096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452866332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_ena
bled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.452866332
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.418314710
Short name T110
Test name
Test status
Simulation time 260059527 ps
CPU time 1.93 seconds
Started Aug 23 08:17:02 AM UTC 24
Finished Aug 23 08:17:05 AM UTC 24
Peak memory 222440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418314710 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_i
ntg_err.418314710
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.631210481
Short name T24
Test name
Test status
Simulation time 978519327 ps
CPU time 7.88 seconds
Started Aug 23 09:41:54 AM UTC 24
Finished Aug 23 09:42:02 AM UTC 24
Peak memory 231952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631210481 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.631210481
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.1526170344
Short name T155
Test name
Test status
Simulation time 1179466426 ps
CPU time 6.5 seconds
Started Aug 23 09:57:49 AM UTC 24
Finished Aug 23 09:57:57 AM UTC 24
Peak memory 232008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526170344 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1526170344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.4264621344
Short name T59
Test name
Test status
Simulation time 24521995496 ps
CPU time 313.64 seconds
Started Aug 23 09:42:56 AM UTC 24
Finished Aug 23 09:48:14 AM UTC 24
Peak memory 289284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4264621344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 1.lc_ctrl_stress_all.4264621344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.165521604
Short name T193
Test name
Test status
Simulation time 38274256 ps
CPU time 0.91 seconds
Started Aug 23 08:17:04 AM UTC 24
Finished Aug 23 08:17:06 AM UTC 24
Peak memory 218996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165521604 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_ali
asing.165521604
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.661891671
Short name T25
Test name
Test status
Simulation time 19120505 ps
CPU time 0.84 seconds
Started Aug 23 09:42:04 AM UTC 24
Finished Aug 23 09:42:06 AM UTC 24
Peak memory 218760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661891671 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.661891671
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.584546652
Short name T114
Test name
Test status
Simulation time 207532337 ps
CPU time 3.88 seconds
Started Aug 23 08:17:09 AM UTC 24
Finished Aug 23 08:17:14 AM UTC 24
Peak memory 230112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584546652 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_i
ntg_err.584546652
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2446419022
Short name T40
Test name
Test status
Simulation time 1036426915 ps
CPU time 9.76 seconds
Started Aug 23 09:42:16 AM UTC 24
Finished Aug 23 09:42:27 AM UTC 24
Peak memory 231884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446419022 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2446419022
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1453054828
Short name T12
Test name
Test status
Simulation time 196485534 ps
CPU time 19.25 seconds
Started Aug 23 09:41:02 AM UTC 24
Finished Aug 23 09:41:23 AM UTC 24
Peak memory 260460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453054828 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1453054828
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.2705802539
Short name T44
Test name
Test status
Simulation time 844201230 ps
CPU time 10.2 seconds
Started Aug 23 09:42:21 AM UTC 24
Finished Aug 23 09:42:33 AM UTC 24
Peak memory 229700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705802539 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2705802539
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.1084061549
Short name T328
Test name
Test status
Simulation time 1691217027 ps
CPU time 43.61 seconds
Started Aug 23 09:47:13 AM UTC 24
Finished Aug 23 09:47:58 AM UTC 24
Peak memory 285360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084061549
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_jtag_state_failure.1084061549
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1862030787
Short name T109
Test name
Test status
Simulation time 98863474 ps
CPU time 3.62 seconds
Started Aug 23 08:17:00 AM UTC 24
Finished Aug 23 08:17:04 AM UTC 24
Peak memory 229712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862030787 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1862030787
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.3202333030
Short name T49
Test name
Test status
Simulation time 3095159168 ps
CPU time 62.87 seconds
Started Aug 23 09:51:16 AM UTC 24
Finished Aug 23 09:52:20 AM UTC 24
Peak memory 262896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3202333030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 16.lc_ctrl_stress_all.3202333030
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2209586386
Short name T131
Test name
Test status
Simulation time 299876086 ps
CPU time 2.43 seconds
Started Aug 23 08:17:36 AM UTC 24
Finished Aug 23 08:17:40 AM UTC 24
Peak memory 223560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209586386 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl
_intg_err.2209586386
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.1603134533
Short name T105
Test name
Test status
Simulation time 260272916 ps
CPU time 5.77 seconds
Started Aug 23 09:48:10 AM UTC 24
Finished Aug 23 09:48:17 AM UTC 24
Peak memory 260532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603134533 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1603134533
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1110546151
Short name T134
Test name
Test status
Simulation time 581915341 ps
CPU time 2.39 seconds
Started Aug 23 08:17:37 AM UTC 24
Finished Aug 23 08:17:41 AM UTC 24
Peak memory 235856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110546151 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl
_intg_err.1110546151
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.926571344
Short name T120
Test name
Test status
Simulation time 165727552 ps
CPU time 1.58 seconds
Started Aug 23 08:17:26 AM UTC 24
Finished Aug 23 08:17:29 AM UTC 24
Peak memory 222380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926571344 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_i
ntg_err.926571344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3324430172
Short name T117
Test name
Test status
Simulation time 84728744 ps
CPU time 1.22 seconds
Started Aug 23 08:16:58 AM UTC 24
Finished Aug 23 08:17:01 AM UTC 24
Peak memory 220332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3324430172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3324430172
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.4122505322
Short name T100
Test name
Test status
Simulation time 4105965814 ps
CPU time 68.36 seconds
Started Aug 23 09:44:39 AM UTC 24
Finished Aug 23 09:45:49 AM UTC 24
Peak memory 272936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122505322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_u
nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.4122505322
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.2042182986
Short name T14
Test name
Test status
Simulation time 31007944 ps
CPU time 0.75 seconds
Started Aug 23 09:41:27 AM UTC 24
Finished Aug 23 09:41:28 AM UTC 24
Peak memory 217076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042182986 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2042182986
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.325546666
Short name T132
Test name
Test status
Simulation time 48157304 ps
CPU time 2.16 seconds
Started Aug 23 08:17:40 AM UTC 24
Finished Aug 23 08:17:43 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325546666 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_
intg_err.325546666
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4054067561
Short name T126
Test name
Test status
Simulation time 458504983 ps
CPU time 2.65 seconds
Started Aug 23 08:17:41 AM UTC 24
Finished Aug 23 08:17:45 AM UTC 24
Peak memory 223560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054067561 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl
_intg_err.4054067561
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1389269299
Short name T125
Test name
Test status
Simulation time 131469684 ps
CPU time 2.06 seconds
Started Aug 23 08:17:42 AM UTC 24
Finished Aug 23 08:17:45 AM UTC 24
Peak memory 230164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389269299 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl
_intg_err.1389269299
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.1435246368
Short name T64
Test name
Test status
Simulation time 284109333 ps
CPU time 10.37 seconds
Started Aug 23 09:48:13 AM UTC 24
Finished Aug 23 09:48:24 AM UTC 24
Peak memory 231944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435246368 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1435246368
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.2814636094
Short name T213
Test name
Test status
Simulation time 22008321 ps
CPU time 0.8 seconds
Started Aug 23 09:44:03 AM UTC 24
Finished Aug 23 09:44:05 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814636094 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2814636094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.146749574
Short name T146
Test name
Test status
Simulation time 17480210 ps
CPU time 0.74 seconds
Started Aug 23 09:44:59 AM UTC 24
Finished Aug 23 09:45:00 AM UTC 24
Peak memory 218912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146749574 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.146749574
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2593526076
Short name T215
Test name
Test status
Simulation time 12845990 ps
CPU time 0.73 seconds
Started Aug 23 09:47:11 AM UTC 24
Finished Aug 23 09:47:13 AM UTC 24
Peak memory 217076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593526076 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2593526076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3507323521
Short name T212
Test name
Test status
Simulation time 35232885 ps
CPU time 0.68 seconds
Started Aug 23 09:47:43 AM UTC 24
Finished Aug 23 09:47:45 AM UTC 24
Peak memory 218908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507323521 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3507323521
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3933330172
Short name T129
Test name
Test status
Simulation time 80257227 ps
CPU time 3.31 seconds
Started Aug 23 08:17:36 AM UTC 24
Finished Aug 23 08:17:40 AM UTC 24
Peak memory 230092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933330172 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl
_intg_err.3933330172
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2468722965
Short name T133
Test name
Test status
Simulation time 44638737 ps
CPU time 1.91 seconds
Started Aug 23 08:17:37 AM UTC 24
Finished Aug 23 08:17:40 AM UTC 24
Peak memory 232628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468722965 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl
_intg_err.2468722965
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.345542110
Short name T130
Test name
Test status
Simulation time 731975479 ps
CPU time 2.73 seconds
Started Aug 23 08:17:39 AM UTC 24
Finished Aug 23 08:17:42 AM UTC 24
Peak memory 235788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345542110 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_
intg_err.345542110
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.214387026
Short name T61
Test name
Test status
Simulation time 2277865521 ps
CPU time 78.21 seconds
Started Aug 23 09:48:57 AM UTC 24
Finished Aug 23 09:50:17 AM UTC 24
Peak memory 262556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=214387026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 11.lc_ctrl_stress_all.214387026
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.2463576262
Short name T60
Test name
Test status
Simulation time 3586248848 ps
CPU time 84.92 seconds
Started Aug 23 09:46:16 AM UTC 24
Finished Aug 23 09:47:43 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463576262
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jt
ag_errors.2463576262
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.2385972880
Short name T17
Test name
Test status
Simulation time 2511613324 ps
CPU time 4.72 seconds
Started Aug 23 09:41:42 AM UTC 24
Finished Aug 23 09:41:48 AM UTC 24
Peak memory 229676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385972880 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_prior
ity.2385972880
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1783251044
Short name T868
Test name
Test status
Simulation time 21541431 ps
CPU time 1.27 seconds
Started Aug 23 08:17:04 AM UTC 24
Finished Aug 23 08:17:06 AM UTC 24
Peak memory 219000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783251044 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bi
t_bash.1783251044
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.86156418
Short name T136
Test name
Test status
Simulation time 18688584 ps
CPU time 1.11 seconds
Started Aug 23 08:17:02 AM UTC 24
Finished Aug 23 08:17:04 AM UTC 24
Peak memory 220212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86156418 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_r
eset.86156418
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3218382906
Short name T115
Test name
Test status
Simulation time 34844139 ps
CPU time 1.58 seconds
Started Aug 23 08:17:04 AM UTC 24
Finished Aug 23 08:17:07 AM UTC 24
Peak memory 228468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3218382906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3218382906
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.497439935
Short name T137
Test name
Test status
Simulation time 15977302 ps
CPU time 0.83 seconds
Started Aug 23 08:17:03 AM UTC 24
Finished Aug 23 08:17:05 AM UTC 24
Peak memory 218668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497439935 -assert nopost
proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.497439935
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2171956451
Short name T867
Test name
Test status
Simulation time 168442227 ps
CPU time 2.3 seconds
Started Aug 23 08:17:00 AM UTC 24
Finished Aug 23 08:17:03 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=2171956451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2171956451
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2251551115
Short name T874
Test name
Test status
Simulation time 1471239701 ps
CPU time 13.62 seconds
Started Aug 23 08:16:58 AM UTC 24
Finished Aug 23 08:17:13 AM UTC 24
Peak memory 219212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2251551115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2251551115
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.378545567
Short name T211
Test name
Test status
Simulation time 6493043165 ps
CPU time 9.82 seconds
Started Aug 23 08:16:56 AM UTC 24
Finished Aug 23 08:17:07 AM UTC 24
Peak memory 218808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=378545567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.378545567
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2948976306
Short name T119
Test name
Test status
Simulation time 163518046 ps
CPU time 2.1 seconds
Started Aug 23 08:16:56 AM UTC 24
Finished Aug 23 08:16:59 AM UTC 24
Peak memory 221436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2948976306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2948976306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3824479694
Short name T108
Test name
Test status
Simulation time 354889679 ps
CPU time 2.06 seconds
Started Aug 23 08:17:00 AM UTC 24
Finished Aug 23 08:17:03 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824479694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_en
abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3824479694
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.35322328
Short name T116
Test name
Test status
Simulation time 505846057 ps
CPU time 1.33 seconds
Started Aug 23 08:16:56 AM UTC 24
Finished Aug 23 08:16:58 AM UTC 24
Peak memory 219108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma
p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=35322328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.lc_ctrl_jtag_csr_rw.35322328
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1280758722
Short name T153
Test name
Test status
Simulation time 174219037 ps
CPU time 1.33 seconds
Started Aug 23 08:17:04 AM UTC 24
Finished Aug 23 08:17:07 AM UTC 24
Peak memory 220696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128075
8722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc
_ctrl_same_csr_outstanding.1280758722
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2460522449
Short name T195
Test name
Test status
Simulation time 59431146 ps
CPU time 1.15 seconds
Started Aug 23 08:17:11 AM UTC 24
Finished Aug 23 08:17:13 AM UTC 24
Peak memory 218648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460522449 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_al
iasing.2460522449
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2101987263
Short name T875
Test name
Test status
Simulation time 442474599 ps
CPU time 1.81 seconds
Started Aug 23 08:17:11 AM UTC 24
Finished Aug 23 08:17:14 AM UTC 24
Peak memory 218672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101987263 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bi
t_bash.2101987263
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1382461627
Short name T872
Test name
Test status
Simulation time 87740913 ps
CPU time 0.78 seconds
Started Aug 23 08:17:09 AM UTC 24
Finished Aug 23 08:17:11 AM UTC 24
Peak memory 220212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382461627 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw
_reset.1382461627
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2676879410
Short name T118
Test name
Test status
Simulation time 38278755 ps
CPU time 1.61 seconds
Started Aug 23 08:17:11 AM UTC 24
Finished Aug 23 08:17:14 AM UTC 24
Peak memory 236272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2676879410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2676879410
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2828209106
Short name T194
Test name
Test status
Simulation time 31453813 ps
CPU time 0.94 seconds
Started Aug 23 08:17:09 AM UTC 24
Finished Aug 23 08:17:11 AM UTC 24
Peak memory 228464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828209106 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2828209106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1708607002
Short name T870
Test name
Test status
Simulation time 180681656 ps
CPU time 1.16 seconds
Started Aug 23 08:17:08 AM UTC 24
Finished Aug 23 08:17:10 AM UTC 24
Peak memory 218456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=1708607002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1708607002
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3284721565
Short name T871
Test name
Test status
Simulation time 191831804 ps
CPU time 2.82 seconds
Started Aug 23 08:17:06 AM UTC 24
Finished Aug 23 08:17:10 AM UTC 24
Peak memory 219012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3284721565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3284721565
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2579485970
Short name T873
Test name
Test status
Simulation time 2355030263 ps
CPU time 6.22 seconds
Started Aug 23 08:17:05 AM UTC 24
Finished Aug 23 08:17:13 AM UTC 24
Peak memory 219532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2579485970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2579485970
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.557965733
Short name T138
Test name
Test status
Simulation time 108075723 ps
CPU time 1.23 seconds
Started Aug 23 08:17:05 AM UTC 24
Finished Aug 23 08:17:07 AM UTC 24
Peak memory 220640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=557965733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.557965733
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3392050071
Short name T869
Test name
Test status
Simulation time 1013391820 ps
CPU time 1.36 seconds
Started Aug 23 08:17:05 AM UTC 24
Finished Aug 23 08:17:08 AM UTC 24
Peak memory 218160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma
p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3392050071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_rw.3392050071
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.501656617
Short name T202
Test name
Test status
Simulation time 23235433 ps
CPU time 1.11 seconds
Started Aug 23 08:17:07 AM UTC 24
Finished Aug 23 08:17:10 AM UTC 24
Peak memory 220020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=501656617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.501656617
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.958478196
Short name T203
Test name
Test status
Simulation time 48312137 ps
CPU time 1.01 seconds
Started Aug 23 08:17:11 AM UTC 24
Finished Aug 23 08:17:13 AM UTC 24
Peak memory 218724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958478
196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_
ctrl_same_csr_outstanding.958478196
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2284930934
Short name T111
Test name
Test status
Simulation time 394513523 ps
CPU time 2.66 seconds
Started Aug 23 08:17:08 AM UTC 24
Finished Aug 23 08:17:11 AM UTC 24
Peak memory 229840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284930934 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2284930934
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2840688351
Short name T961
Test name
Test status
Simulation time 28965882 ps
CPU time 1.13 seconds
Started Aug 23 08:17:35 AM UTC 24
Finished Aug 23 08:17:37 AM UTC 24
Peak memory 228528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2840688351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2840688351
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1473758170
Short name T957
Test name
Test status
Simulation time 41992240 ps
CPU time 0.8 seconds
Started Aug 23 08:17:35 AM UTC 24
Finished Aug 23 08:17:36 AM UTC 24
Peak memory 218164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473758170 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1473758170
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2979928866
Short name T960
Test name
Test status
Simulation time 48707047 ps
CPU time 0.88 seconds
Started Aug 23 08:17:35 AM UTC 24
Finished Aug 23 08:17:37 AM UTC 24
Peak memory 218768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297992
8866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.l
c_ctrl_same_csr_outstanding.2979928866
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.950226585
Short name T959
Test name
Test status
Simulation time 58043562 ps
CPU time 1.94 seconds
Started Aug 23 08:17:34 AM UTC 24
Finished Aug 23 08:17:37 AM UTC 24
Peak memory 229744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950226585 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.950226585
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1304625069
Short name T956
Test name
Test status
Simulation time 219784398 ps
CPU time 1.68 seconds
Started Aug 23 08:17:34 AM UTC 24
Finished Aug 23 08:17:36 AM UTC 24
Peak memory 232688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304625069 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl
_intg_err.1304625069
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3597748536
Short name T968
Test name
Test status
Simulation time 21646075 ps
CPU time 1.03 seconds
Started Aug 23 08:17:36 AM UTC 24
Finished Aug 23 08:17:38 AM UTC 24
Peak memory 232524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3597748536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3597748536
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3999499273
Short name T199
Test name
Test status
Simulation time 18927626 ps
CPU time 1 seconds
Started Aug 23 08:17:36 AM UTC 24
Finished Aug 23 08:17:38 AM UTC 24
Peak memory 219056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999499273 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3999499273
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3196988288
Short name T969
Test name
Test status
Simulation time 53389007 ps
CPU time 1.25 seconds
Started Aug 23 08:17:36 AM UTC 24
Finished Aug 23 08:17:38 AM UTC 24
Peak memory 218636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319698
8288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.l
c_ctrl_same_csr_outstanding.3196988288
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3523262123
Short name T966
Test name
Test status
Simulation time 146128521 ps
CPU time 2.32 seconds
Started Aug 23 08:17:35 AM UTC 24
Finished Aug 23 08:17:38 AM UTC 24
Peak memory 229708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523262123 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3523262123
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3463475047
Short name T970
Test name
Test status
Simulation time 22135560 ps
CPU time 1.07 seconds
Started Aug 23 08:17:36 AM UTC 24
Finished Aug 23 08:17:38 AM UTC 24
Peak memory 230512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3463475047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3463475047
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.746928779
Short name T965
Test name
Test status
Simulation time 53066122 ps
CPU time 0.91 seconds
Started Aug 23 08:17:36 AM UTC 24
Finished Aug 23 08:17:38 AM UTC 24
Peak memory 218224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746928779 -assert nopost
proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.746928779
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2982870711
Short name T967
Test name
Test status
Simulation time 15018326 ps
CPU time 0.89 seconds
Started Aug 23 08:17:36 AM UTC 24
Finished Aug 23 08:17:38 AM UTC 24
Peak memory 218228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298287
0711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.l
c_ctrl_same_csr_outstanding.2982870711
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1911634799
Short name T953
Test name
Test status
Simulation time 129427170 ps
CPU time 2.38 seconds
Started Aug 23 08:17:36 AM UTC 24
Finished Aug 23 08:17:40 AM UTC 24
Peak memory 229784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911634799 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1911634799
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2306543430
Short name T923
Test name
Test status
Simulation time 50416612 ps
CPU time 1.19 seconds
Started Aug 23 08:17:37 AM UTC 24
Finished Aug 23 08:17:40 AM UTC 24
Peak memory 228468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2306543430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2306543430
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2174743633
Short name T971
Test name
Test status
Simulation time 25563930 ps
CPU time 0.89 seconds
Started Aug 23 08:17:37 AM UTC 24
Finished Aug 23 08:17:39 AM UTC 24
Peak memory 218936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174743633 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2174743633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3469681937
Short name T972
Test name
Test status
Simulation time 161231453 ps
CPU time 0.93 seconds
Started Aug 23 08:17:37 AM UTC 24
Finished Aug 23 08:17:39 AM UTC 24
Peak memory 218704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346968
1937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.l
c_ctrl_same_csr_outstanding.3469681937
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3219065423
Short name T954
Test name
Test status
Simulation time 27467304 ps
CPU time 1.43 seconds
Started Aug 23 08:17:37 AM UTC 24
Finished Aug 23 08:17:40 AM UTC 24
Peak memory 228524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219065423 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3219065423
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1057546586
Short name T975
Test name
Test status
Simulation time 17062247 ps
CPU time 1.08 seconds
Started Aug 23 08:17:38 AM UTC 24
Finished Aug 23 08:17:40 AM UTC 24
Peak memory 228468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1057546586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1057546586
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.147895958
Short name T973
Test name
Test status
Simulation time 76798184 ps
CPU time 0.82 seconds
Started Aug 23 08:17:37 AM UTC 24
Finished Aug 23 08:17:39 AM UTC 24
Peak memory 218224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147895958 -assert nopost
proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.147895958
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2398051109
Short name T974
Test name
Test status
Simulation time 78258579 ps
CPU time 0.93 seconds
Started Aug 23 08:17:37 AM UTC 24
Finished Aug 23 08:17:39 AM UTC 24
Peak memory 218184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239805
1109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.l
c_ctrl_same_csr_outstanding.2398051109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2638043595
Short name T979
Test name
Test status
Simulation time 297897410 ps
CPU time 3.29 seconds
Started Aug 23 08:17:37 AM UTC 24
Finished Aug 23 08:17:42 AM UTC 24
Peak memory 229056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638043595 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2638043595
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.157479701
Short name T976
Test name
Test status
Simulation time 113394441 ps
CPU time 1.12 seconds
Started Aug 23 08:17:39 AM UTC 24
Finished Aug 23 08:17:41 AM UTC 24
Peak memory 228468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=157479701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.157479701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3502264895
Short name T963
Test name
Test status
Simulation time 42820400 ps
CPU time 0.74 seconds
Started Aug 23 08:17:39 AM UTC 24
Finished Aug 23 08:17:40 AM UTC 24
Peak memory 218224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502264895 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3502264895
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2613134705
Short name T978
Test name
Test status
Simulation time 46947151 ps
CPU time 1.79 seconds
Started Aug 23 08:17:39 AM UTC 24
Finished Aug 23 08:17:41 AM UTC 24
Peak memory 218704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261313
4705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.l
c_ctrl_same_csr_outstanding.2613134705
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3891413448
Short name T977
Test name
Test status
Simulation time 49783766 ps
CPU time 1.3 seconds
Started Aug 23 08:17:39 AM UTC 24
Finished Aug 23 08:17:41 AM UTC 24
Peak memory 230580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891413448 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3891413448
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3145480746
Short name T982
Test name
Test status
Simulation time 71998377 ps
CPU time 1.31 seconds
Started Aug 23 08:17:40 AM UTC 24
Finished Aug 23 08:17:42 AM UTC 24
Peak memory 236232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3145480746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3145480746
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3509362094
Short name T980
Test name
Test status
Simulation time 50714651 ps
CPU time 0.99 seconds
Started Aug 23 08:17:40 AM UTC 24
Finished Aug 23 08:17:42 AM UTC 24
Peak memory 218164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509362094 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3509362094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.4196054959
Short name T981
Test name
Test status
Simulation time 28760449 ps
CPU time 1.27 seconds
Started Aug 23 08:17:40 AM UTC 24
Finished Aug 23 08:17:42 AM UTC 24
Peak memory 218732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419605
4959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.l
c_ctrl_same_csr_outstanding.4196054959
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.30565011
Short name T985
Test name
Test status
Simulation time 43203345 ps
CPU time 2.63 seconds
Started Aug 23 08:17:39 AM UTC 24
Finished Aug 23 08:17:42 AM UTC 24
Peak memory 229700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30565011 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.30565011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.172351289
Short name T135
Test name
Test status
Simulation time 117751463 ps
CPU time 2.75 seconds
Started Aug 23 08:17:39 AM UTC 24
Finished Aug 23 08:17:43 AM UTC 24
Peak memory 235852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172351289 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_
intg_err.172351289
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3695787240
Short name T990
Test name
Test status
Simulation time 60738823 ps
CPU time 1.73 seconds
Started Aug 23 08:17:41 AM UTC 24
Finished Aug 23 08:17:44 AM UTC 24
Peak memory 228468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3695787240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3695787240
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3617846943
Short name T200
Test name
Test status
Simulation time 48924508 ps
CPU time 0.78 seconds
Started Aug 23 08:17:40 AM UTC 24
Finished Aug 23 08:17:42 AM UTC 24
Peak memory 218224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617846943 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3617846943
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2086492436
Short name T983
Test name
Test status
Simulation time 108908764 ps
CPU time 1.28 seconds
Started Aug 23 08:17:40 AM UTC 24
Finished Aug 23 08:17:42 AM UTC 24
Peak memory 218644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208649
2436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.l
c_ctrl_same_csr_outstanding.2086492436
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2202023247
Short name T991
Test name
Test status
Simulation time 51175397 ps
CPU time 2.85 seconds
Started Aug 23 08:17:40 AM UTC 24
Finished Aug 23 08:17:44 AM UTC 24
Peak memory 231756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202023247 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2202023247
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.834478978
Short name T989
Test name
Test status
Simulation time 22756450 ps
CPU time 1.51 seconds
Started Aug 23 08:17:41 AM UTC 24
Finished Aug 23 08:17:44 AM UTC 24
Peak memory 228468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=834478978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.834478978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.915678319
Short name T201
Test name
Test status
Simulation time 75830489 ps
CPU time 0.87 seconds
Started Aug 23 08:17:41 AM UTC 24
Finished Aug 23 08:17:43 AM UTC 24
Peak memory 218224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915678319 -assert nopost
proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.915678319
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3536025896
Short name T986
Test name
Test status
Simulation time 57457374 ps
CPU time 0.97 seconds
Started Aug 23 08:17:41 AM UTC 24
Finished Aug 23 08:17:43 AM UTC 24
Peak memory 218288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353602
5896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.l
c_ctrl_same_csr_outstanding.3536025896
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.210627805
Short name T988
Test name
Test status
Simulation time 65660903 ps
CPU time 1.51 seconds
Started Aug 23 08:17:41 AM UTC 24
Finished Aug 23 08:17:44 AM UTC 24
Peak memory 228524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210627805 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.210627805
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3321897559
Short name T994
Test name
Test status
Simulation time 16129721 ps
CPU time 1.21 seconds
Started Aug 23 08:17:42 AM UTC 24
Finished Aug 23 08:17:45 AM UTC 24
Peak memory 230376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3321897559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3321897559
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1829126342
Short name T992
Test name
Test status
Simulation time 13272529 ps
CPU time 0.78 seconds
Started Aug 23 08:17:42 AM UTC 24
Finished Aug 23 08:17:44 AM UTC 24
Peak memory 218136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829126342 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1829126342
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3187813117
Short name T993
Test name
Test status
Simulation time 43893141 ps
CPU time 1.04 seconds
Started Aug 23 08:17:42 AM UTC 24
Finished Aug 23 08:17:44 AM UTC 24
Peak memory 218652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318781
3117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.l
c_ctrl_same_csr_outstanding.3187813117
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1294345704
Short name T995
Test name
Test status
Simulation time 151795695 ps
CPU time 4.27 seconds
Started Aug 23 08:17:42 AM UTC 24
Finished Aug 23 08:17:48 AM UTC 24
Peak memory 230012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294345704 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1294345704
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1929387540
Short name T881
Test name
Test status
Simulation time 17407896 ps
CPU time 0.93 seconds
Started Aug 23 08:17:15 AM UTC 24
Finished Aug 23 08:17:17 AM UTC 24
Peak memory 218228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929387540 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_al
iasing.1929387540
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1198508382
Short name T882
Test name
Test status
Simulation time 75517479 ps
CPU time 1.07 seconds
Started Aug 23 08:17:15 AM UTC 24
Finished Aug 23 08:17:17 AM UTC 24
Peak memory 219000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198508382 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bi
t_bash.1198508382
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3916273797
Short name T877
Test name
Test status
Simulation time 17076997 ps
CPU time 1.05 seconds
Started Aug 23 08:17:14 AM UTC 24
Finished Aug 23 08:17:16 AM UTC 24
Peak memory 220276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916273797 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw
_reset.3916273797
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1880398643
Short name T154
Test name
Test status
Simulation time 23715287 ps
CPU time 1.05 seconds
Started Aug 23 08:17:16 AM UTC 24
Finished Aug 23 08:17:18 AM UTC 24
Peak memory 232564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1880398643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1880398643
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1398209968
Short name T880
Test name
Test status
Simulation time 50444770 ps
CPU time 0.85 seconds
Started Aug 23 08:17:15 AM UTC 24
Finished Aug 23 08:17:17 AM UTC 24
Peak memory 218576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398209968 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1398209968
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3712672224
Short name T878
Test name
Test status
Simulation time 297179246 ps
CPU time 1.32 seconds
Started Aug 23 08:17:14 AM UTC 24
Finished Aug 23 08:17:16 AM UTC 24
Peak memory 218808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=3712672224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3712672224
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.795854035
Short name T879
Test name
Test status
Simulation time 415489103 ps
CPU time 2.68 seconds
Started Aug 23 08:17:12 AM UTC 24
Finished Aug 23 08:17:16 AM UTC 24
Peak memory 219200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=795854035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.795854035
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.661096739
Short name T884
Test name
Test status
Simulation time 2457860694 ps
CPU time 4.29 seconds
Started Aug 23 08:17:12 AM UTC 24
Finished Aug 23 08:17:18 AM UTC 24
Peak memory 219404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=661096739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.661096739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1058459901
Short name T876
Test name
Test status
Simulation time 108114208 ps
CPU time 2.99 seconds
Started Aug 23 08:17:11 AM UTC 24
Finished Aug 23 08:17:15 AM UTC 24
Peak memory 221452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1058459901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1058459901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1545985169
Short name T168
Test name
Test status
Simulation time 79332174 ps
CPU time 2.04 seconds
Started Aug 23 08:17:14 AM UTC 24
Finished Aug 23 08:17:17 AM UTC 24
Peak memory 231896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545985169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_en
abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1545985169
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2373713205
Short name T883
Test name
Test status
Simulation time 158017572 ps
CPU time 3.77 seconds
Started Aug 23 08:17:12 AM UTC 24
Finished Aug 23 08:17:17 AM UTC 24
Peak memory 219388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma
p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2373713205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_rw.2373713205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1466106111
Short name T204
Test name
Test status
Simulation time 54237579 ps
CPU time 0.88 seconds
Started Aug 23 08:17:12 AM UTC 24
Finished Aug 23 08:17:14 AM UTC 24
Peak memory 218284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1466106111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1466106111
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2728429562
Short name T205
Test name
Test status
Simulation time 24757395 ps
CPU time 0.97 seconds
Started Aug 23 08:17:15 AM UTC 24
Finished Aug 23 08:17:17 AM UTC 24
Peak memory 218292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272842
9562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc
_ctrl_same_csr_outstanding.2728429562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3076356329
Short name T122
Test name
Test status
Simulation time 25063169 ps
CPU time 1.67 seconds
Started Aug 23 08:17:14 AM UTC 24
Finished Aug 23 08:17:16 AM UTC 24
Peak memory 228524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076356329 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3076356329
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1036085659
Short name T113
Test name
Test status
Simulation time 289786682 ps
CPU time 2.68 seconds
Started Aug 23 08:17:14 AM UTC 24
Finished Aug 23 08:17:17 AM UTC 24
Peak memory 229900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036085659 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_
intg_err.1036085659
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1431121245
Short name T889
Test name
Test status
Simulation time 89897171 ps
CPU time 1.04 seconds
Started Aug 23 08:17:18 AM UTC 24
Finished Aug 23 08:17:20 AM UTC 24
Peak memory 218892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431121245 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_al
iasing.1431121245
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3638303444
Short name T891
Test name
Test status
Simulation time 102364093 ps
CPU time 1.45 seconds
Started Aug 23 08:17:18 AM UTC 24
Finished Aug 23 08:17:20 AM UTC 24
Peak memory 218836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638303444 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bi
t_bash.3638303444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3883708961
Short name T890
Test name
Test status
Simulation time 38378319 ps
CPU time 1.23 seconds
Started Aug 23 08:17:18 AM UTC 24
Finished Aug 23 08:17:20 AM UTC 24
Peak memory 219904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883708961 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw
_reset.3883708961
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1752975882
Short name T893
Test name
Test status
Simulation time 96959058 ps
CPU time 1.4 seconds
Started Aug 23 08:17:19 AM UTC 24
Finished Aug 23 08:17:21 AM UTC 24
Peak memory 228468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1752975882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1752975882
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2525407045
Short name T888
Test name
Test status
Simulation time 29657173 ps
CPU time 1.01 seconds
Started Aug 23 08:17:18 AM UTC 24
Finished Aug 23 08:17:20 AM UTC 24
Peak memory 228624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525407045 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2525407045
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2397261343
Short name T886
Test name
Test status
Simulation time 109268876 ps
CPU time 0.87 seconds
Started Aug 23 08:17:18 AM UTC 24
Finished Aug 23 08:17:19 AM UTC 24
Peak memory 218784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=2397261343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2397261343
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2099808363
Short name T962
Test name
Test status
Simulation time 1750907993 ps
CPU time 19.44 seconds
Started Aug 23 08:17:16 AM UTC 24
Finished Aug 23 08:17:37 AM UTC 24
Peak memory 219036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2099808363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2099808363
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3874002366
Short name T908
Test name
Test status
Simulation time 1861677322 ps
CPU time 8.75 seconds
Started Aug 23 08:17:16 AM UTC 24
Finished Aug 23 08:17:26 AM UTC 24
Peak memory 219380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3874002366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3874002366
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1865619349
Short name T885
Test name
Test status
Simulation time 52712828 ps
CPU time 1.19 seconds
Started Aug 23 08:17:16 AM UTC 24
Finished Aug 23 08:17:18 AM UTC 24
Peak memory 220568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1865619349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1865619349
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1913591142
Short name T895
Test name
Test status
Simulation time 365831476 ps
CPU time 4.43 seconds
Started Aug 23 08:17:17 AM UTC 24
Finished Aug 23 08:17:23 AM UTC 24
Peak memory 230120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913591142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_en
abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1913591142
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4028547979
Short name T887
Test name
Test status
Simulation time 82573505 ps
CPU time 2.29 seconds
Started Aug 23 08:17:16 AM UTC 24
Finished Aug 23 08:17:20 AM UTC 24
Peak memory 219360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma
p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=4028547979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_rw.4028547979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3230127402
Short name T206
Test name
Test status
Simulation time 137669897 ps
CPU time 1.33 seconds
Started Aug 23 08:17:17 AM UTC 24
Finished Aug 23 08:17:20 AM UTC 24
Peak memory 218808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3230127402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3230127402
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2385496919
Short name T207
Test name
Test status
Simulation time 71617424 ps
CPU time 1.27 seconds
Started Aug 23 08:17:19 AM UTC 24
Finished Aug 23 08:17:21 AM UTC 24
Peak memory 220340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238549
6919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc
_ctrl_same_csr_outstanding.2385496919
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.718482412
Short name T128
Test name
Test status
Simulation time 91068000 ps
CPU time 1.4 seconds
Started Aug 23 08:17:18 AM UTC 24
Finished Aug 23 08:17:20 AM UTC 24
Peak memory 230560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718482412 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.718482412
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.33008093
Short name T216
Test name
Test status
Simulation time 229831518 ps
CPU time 1.75 seconds
Started Aug 23 08:17:18 AM UTC 24
Finished Aug 23 08:17:20 AM UTC 24
Peak memory 232624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33008093 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_in
tg_err.33008093
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2552318677
Short name T196
Test name
Test status
Simulation time 243279714 ps
CPU time 1.03 seconds
Started Aug 23 08:17:22 AM UTC 24
Finished Aug 23 08:17:24 AM UTC 24
Peak memory 218856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552318677 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_al
iasing.2552318677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3613670114
Short name T902
Test name
Test status
Simulation time 184676783 ps
CPU time 1.77 seconds
Started Aug 23 08:17:22 AM UTC 24
Finished Aug 23 08:17:25 AM UTC 24
Peak memory 218940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613670114 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bi
t_bash.3613670114
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4097287139
Short name T899
Test name
Test status
Simulation time 22294849 ps
CPU time 1.16 seconds
Started Aug 23 08:17:22 AM UTC 24
Finished Aug 23 08:17:24 AM UTC 24
Peak memory 220208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097287139 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw
_reset.4097287139
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2812562128
Short name T898
Test name
Test status
Simulation time 73932904 ps
CPU time 0.91 seconds
Started Aug 23 08:17:22 AM UTC 24
Finished Aug 23 08:17:24 AM UTC 24
Peak memory 230512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2812562128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2812562128
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4217225364
Short name T897
Test name
Test status
Simulation time 12751755 ps
CPU time 0.88 seconds
Started Aug 23 08:17:22 AM UTC 24
Finished Aug 23 08:17:24 AM UTC 24
Peak memory 218164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217225364 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.4217225364
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1748365460
Short name T896
Test name
Test status
Simulation time 421047627 ps
CPU time 2.2 seconds
Started Aug 23 08:17:20 AM UTC 24
Finished Aug 23 08:17:23 AM UTC 24
Peak memory 218728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=1748365460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1748365460
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3787672255
Short name T958
Test name
Test status
Simulation time 2935375987 ps
CPU time 15.32 seconds
Started Aug 23 08:17:20 AM UTC 24
Finished Aug 23 08:17:37 AM UTC 24
Peak memory 219352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3787672255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3787672255
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3891483042
Short name T909
Test name
Test status
Simulation time 489654515 ps
CPU time 5.36 seconds
Started Aug 23 08:17:20 AM UTC 24
Finished Aug 23 08:17:26 AM UTC 24
Peak memory 219348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3891483042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3891483042
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.109746114
Short name T892
Test name
Test status
Simulation time 45476544 ps
CPU time 1.22 seconds
Started Aug 23 08:17:19 AM UTC 24
Finished Aug 23 08:17:21 AM UTC 24
Peak memory 220208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=109746114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.109746114
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1470682764
Short name T905
Test name
Test status
Simulation time 2302505627 ps
CPU time 4.49 seconds
Started Aug 23 08:17:20 AM UTC 24
Finished Aug 23 08:17:26 AM UTC 24
Peak memory 235984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470682764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_en
abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1470682764
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1010033011
Short name T894
Test name
Test status
Simulation time 96392273 ps
CPU time 2.49 seconds
Started Aug 23 08:17:19 AM UTC 24
Finished Aug 23 08:17:22 AM UTC 24
Peak memory 219464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma
p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1010033011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_rw.1010033011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.327315734
Short name T208
Test name
Test status
Simulation time 32330298 ps
CPU time 1.2 seconds
Started Aug 23 08:17:20 AM UTC 24
Finished Aug 23 08:17:22 AM UTC 24
Peak memory 218708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=327315734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.327315734
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2542679578
Short name T209
Test name
Test status
Simulation time 64630319 ps
CPU time 0.98 seconds
Started Aug 23 08:17:22 AM UTC 24
Finished Aug 23 08:17:24 AM UTC 24
Peak memory 218708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254267
9578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc
_ctrl_same_csr_outstanding.2542679578
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3088841780
Short name T904
Test name
Test status
Simulation time 90765635 ps
CPU time 2.72 seconds
Started Aug 23 08:17:22 AM UTC 24
Finished Aug 23 08:17:25 AM UTC 24
Peak memory 230012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088841780 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3088841780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2008831948
Short name T124
Test name
Test status
Simulation time 393518480 ps
CPU time 2.72 seconds
Started Aug 23 08:17:22 AM UTC 24
Finished Aug 23 08:17:25 AM UTC 24
Peak memory 235992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008831948 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_
intg_err.2008831948
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1861597340
Short name T913
Test name
Test status
Simulation time 24548584 ps
CPU time 1.33 seconds
Started Aug 23 08:17:25 AM UTC 24
Finished Aug 23 08:17:27 AM UTC 24
Peak memory 230316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1861597340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1861597340
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3853170779
Short name T907
Test name
Test status
Simulation time 69946829 ps
CPU time 0.9 seconds
Started Aug 23 08:17:25 AM UTC 24
Finished Aug 23 08:17:27 AM UTC 24
Peak memory 218224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853170779 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3853170779
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.149274164
Short name T906
Test name
Test status
Simulation time 46596423 ps
CPU time 1.32 seconds
Started Aug 23 08:17:23 AM UTC 24
Finished Aug 23 08:17:26 AM UTC 24
Peak memory 218812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=149274164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.lc_ctrl_jtag_alert_test.149274164
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4137719645
Short name T943
Test name
Test status
Simulation time 7478145737 ps
CPU time 9.71 seconds
Started Aug 23 08:17:23 AM UTC 24
Finished Aug 23 08:17:34 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4137719645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.4137719645
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4249084491
Short name T920
Test name
Test status
Simulation time 3293209559 ps
CPU time 6.24 seconds
Started Aug 23 08:17:22 AM UTC 24
Finished Aug 23 08:17:29 AM UTC 24
Peak memory 218468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4249084491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4249084491
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3094059088
Short name T900
Test name
Test status
Simulation time 59116211 ps
CPU time 1.28 seconds
Started Aug 23 08:17:22 AM UTC 24
Finished Aug 23 08:17:24 AM UTC 24
Peak memory 220568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3094059088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3094059088
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.806497603
Short name T910
Test name
Test status
Simulation time 152992770 ps
CPU time 2.29 seconds
Started Aug 23 08:17:23 AM UTC 24
Finished Aug 23 08:17:27 AM UTC 24
Peak memory 228904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806497603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_ena
bled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.806497603
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2554891433
Short name T901
Test name
Test status
Simulation time 81281861 ps
CPU time 1.55 seconds
Started Aug 23 08:17:22 AM UTC 24
Finished Aug 23 08:17:24 AM UTC 24
Peak memory 218580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma
p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2554891433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_rw.2554891433
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3147000822
Short name T903
Test name
Test status
Simulation time 40556535 ps
CPU time 0.96 seconds
Started Aug 23 08:17:23 AM UTC 24
Finished Aug 23 08:17:25 AM UTC 24
Peak memory 218700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3147000822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3147000822
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2541176954
Short name T911
Test name
Test status
Simulation time 157687655 ps
CPU time 1.2 seconds
Started Aug 23 08:17:25 AM UTC 24
Finished Aug 23 08:17:27 AM UTC 24
Peak memory 229048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254117
6954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc
_ctrl_same_csr_outstanding.2541176954
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.66820532
Short name T912
Test name
Test status
Simulation time 92085995 ps
CPU time 2.47 seconds
Started Aug 23 08:17:23 AM UTC 24
Finished Aug 23 08:17:27 AM UTC 24
Peak memory 229788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66820532 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.66820532
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3872964293
Short name T123
Test name
Test status
Simulation time 152699466 ps
CPU time 2.15 seconds
Started Aug 23 08:17:23 AM UTC 24
Finished Aug 23 08:17:27 AM UTC 24
Peak memory 233812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872964293 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_
intg_err.3872964293
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.606839753
Short name T919
Test name
Test status
Simulation time 23332348 ps
CPU time 1.22 seconds
Started Aug 23 08:17:26 AM UTC 24
Finished Aug 23 08:17:29 AM UTC 24
Peak memory 228476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=606839753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.606839753
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.738927862
Short name T197
Test name
Test status
Simulation time 20018188 ps
CPU time 0.71 seconds
Started Aug 23 08:17:26 AM UTC 24
Finished Aug 23 08:17:28 AM UTC 24
Peak memory 217984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738927862 -assert nopost
proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.738927862
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3589340606
Short name T917
Test name
Test status
Simulation time 103653304 ps
CPU time 1.03 seconds
Started Aug 23 08:17:26 AM UTC 24
Finished Aug 23 08:17:28 AM UTC 24
Peak memory 218732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=3589340606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3589340606
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.264579082
Short name T929
Test name
Test status
Simulation time 1775959097 ps
CPU time 5.08 seconds
Started Aug 23 08:17:25 AM UTC 24
Finished Aug 23 08:17:31 AM UTC 24
Peak memory 219152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=264579082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.264579082
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1626270090
Short name T933
Test name
Test status
Simulation time 2012183961 ps
CPU time 5.65 seconds
Started Aug 23 08:17:25 AM UTC 24
Finished Aug 23 08:17:31 AM UTC 24
Peak memory 218700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1626270090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1626270090
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3439666289
Short name T915
Test name
Test status
Simulation time 107979700 ps
CPU time 1.62 seconds
Started Aug 23 08:17:25 AM UTC 24
Finished Aug 23 08:17:27 AM UTC 24
Peak memory 220640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3439666289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3439666289
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.977576216
Short name T921
Test name
Test status
Simulation time 70445003 ps
CPU time 2.27 seconds
Started Aug 23 08:17:26 AM UTC 24
Finished Aug 23 08:17:29 AM UTC 24
Peak memory 229892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977576216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_ena
bled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.977576216
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3774359501
Short name T916
Test name
Test status
Simulation time 89905320 ps
CPU time 1.82 seconds
Started Aug 23 08:17:25 AM UTC 24
Finished Aug 23 08:17:28 AM UTC 24
Peak memory 218872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma
p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3774359501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_rw.3774359501
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.404228463
Short name T914
Test name
Test status
Simulation time 25710215 ps
CPU time 1.26 seconds
Started Aug 23 08:17:25 AM UTC 24
Finished Aug 23 08:17:27 AM UTC 24
Peak memory 218708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=404228463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.404228463
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1556876233
Short name T918
Test name
Test status
Simulation time 51185635 ps
CPU time 1 seconds
Started Aug 23 08:17:26 AM UTC 24
Finished Aug 23 08:17:28 AM UTC 24
Peak memory 218648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155687
6233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc
_ctrl_same_csr_outstanding.1556876233
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1743928277
Short name T927
Test name
Test status
Simulation time 511599479 ps
CPU time 3.17 seconds
Started Aug 23 08:17:26 AM UTC 24
Finished Aug 23 08:17:30 AM UTC 24
Peak memory 231752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743928277 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1743928277
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.918257069
Short name T930
Test name
Test status
Simulation time 110186211 ps
CPU time 1.33 seconds
Started Aug 23 08:17:29 AM UTC 24
Finished Aug 23 08:17:31 AM UTC 24
Peak memory 228476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=918257069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.918257069
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2417564132
Short name T198
Test name
Test status
Simulation time 22770424 ps
CPU time 0.72 seconds
Started Aug 23 08:17:29 AM UTC 24
Finished Aug 23 08:17:30 AM UTC 24
Peak memory 218224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417564132 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2417564132
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2070102539
Short name T926
Test name
Test status
Simulation time 53583277 ps
CPU time 1.67 seconds
Started Aug 23 08:17:27 AM UTC 24
Finished Aug 23 08:17:30 AM UTC 24
Peak memory 218732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=2070102539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2070102539
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3492938810
Short name T944
Test name
Test status
Simulation time 1022765162 ps
CPU time 5.82 seconds
Started Aug 23 08:17:27 AM UTC 24
Finished Aug 23 08:17:34 AM UTC 24
Peak memory 219436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3492938810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3492938810
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2515865298
Short name T997
Test name
Test status
Simulation time 1652633359 ps
CPU time 25.91 seconds
Started Aug 23 08:17:27 AM UTC 24
Finished Aug 23 08:17:55 AM UTC 24
Peak memory 219232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2515865298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2515865298
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2682677630
Short name T925
Test name
Test status
Simulation time 509510225 ps
CPU time 2.68 seconds
Started Aug 23 08:17:26 AM UTC 24
Finished Aug 23 08:17:30 AM UTC 24
Peak memory 221504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2682677630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2682677630
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4172590646
Short name T938
Test name
Test status
Simulation time 633921684 ps
CPU time 4.06 seconds
Started Aug 23 08:17:27 AM UTC 24
Finished Aug 23 08:17:33 AM UTC 24
Peak memory 229884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172590646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_en
abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4172590646
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3212597675
Short name T924
Test name
Test status
Simulation time 50099370 ps
CPU time 1.72 seconds
Started Aug 23 08:17:27 AM UTC 24
Finished Aug 23 08:17:30 AM UTC 24
Peak memory 218448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma
p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3212597675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_rw.3212597675
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1288179934
Short name T922
Test name
Test status
Simulation time 61552111 ps
CPU time 1.05 seconds
Started Aug 23 08:17:27 AM UTC 24
Finished Aug 23 08:17:29 AM UTC 24
Peak memory 228920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1288179934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1288179934
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2914843187
Short name T928
Test name
Test status
Simulation time 30267919 ps
CPU time 1.28 seconds
Started Aug 23 08:17:29 AM UTC 24
Finished Aug 23 08:17:31 AM UTC 24
Peak memory 218324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291484
3187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc
_ctrl_same_csr_outstanding.2914843187
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2313952000
Short name T937
Test name
Test status
Simulation time 623596691 ps
CPU time 3.62 seconds
Started Aug 23 08:17:28 AM UTC 24
Finished Aug 23 08:17:32 AM UTC 24
Peak memory 229708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313952000 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2313952000
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.541811724
Short name T931
Test name
Test status
Simulation time 132134572 ps
CPU time 2.45 seconds
Started Aug 23 08:17:28 AM UTC 24
Finished Aug 23 08:17:31 AM UTC 24
Peak memory 229700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541811724 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_i
ntg_err.541811724
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1855605502
Short name T941
Test name
Test status
Simulation time 58167062 ps
CPU time 1.13 seconds
Started Aug 23 08:17:31 AM UTC 24
Finished Aug 23 08:17:33 AM UTC 24
Peak memory 230516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1855605502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1855605502
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.171974033
Short name T939
Test name
Test status
Simulation time 14968821 ps
CPU time 0.76 seconds
Started Aug 23 08:17:31 AM UTC 24
Finished Aug 23 08:17:33 AM UTC 24
Peak memory 218512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171974033 -assert nopost
proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.171974033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3106892432
Short name T936
Test name
Test status
Simulation time 226787222 ps
CPU time 1.23 seconds
Started Aug 23 08:17:30 AM UTC 24
Finished Aug 23 08:17:32 AM UTC 24
Peak memory 218808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=3106892432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3106892432
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2659590949
Short name T984
Test name
Test status
Simulation time 514086274 ps
CPU time 11.42 seconds
Started Aug 23 08:17:30 AM UTC 24
Finished Aug 23 08:17:42 AM UTC 24
Peak memory 219408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2659590949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2659590949
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3067716322
Short name T996
Test name
Test status
Simulation time 2082146769 ps
CPU time 18.93 seconds
Started Aug 23 08:17:29 AM UTC 24
Finished Aug 23 08:17:49 AM UTC 24
Peak memory 219184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3067716322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3067716322
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3040891330
Short name T935
Test name
Test status
Simulation time 80741195 ps
CPU time 2.43 seconds
Started Aug 23 08:17:29 AM UTC 24
Finished Aug 23 08:17:32 AM UTC 24
Peak memory 221384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3040891330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3040891330
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.941465144
Short name T942
Test name
Test status
Simulation time 414526346 ps
CPU time 2.52 seconds
Started Aug 23 08:17:30 AM UTC 24
Finished Aug 23 08:17:33 AM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941465144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_ena
bled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.941465144
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3945943266
Short name T932
Test name
Test status
Simulation time 94267405 ps
CPU time 1.5 seconds
Started Aug 23 08:17:29 AM UTC 24
Finished Aug 23 08:17:31 AM UTC 24
Peak memory 218872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma
p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3945943266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_rw.3945943266
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2547659245
Short name T934
Test name
Test status
Simulation time 100276806 ps
CPU time 1.18 seconds
Started Aug 23 08:17:30 AM UTC 24
Finished Aug 23 08:17:32 AM UTC 24
Peak memory 218612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2547659245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2547659245
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.627996457
Short name T940
Test name
Test status
Simulation time 25529157 ps
CPU time 1.06 seconds
Started Aug 23 08:17:31 AM UTC 24
Finished Aug 23 08:17:33 AM UTC 24
Peak memory 218296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627996
457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_
ctrl_same_csr_outstanding.627996457
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.603713989
Short name T950
Test name
Test status
Simulation time 520544607 ps
CPU time 4.45 seconds
Started Aug 23 08:17:30 AM UTC 24
Finished Aug 23 08:17:35 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603713989 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.603713989
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2443078660
Short name T127
Test name
Test status
Simulation time 95575210 ps
CPU time 2.75 seconds
Started Aug 23 08:17:31 AM UTC 24
Finished Aug 23 08:17:35 AM UTC 24
Peak memory 223588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443078660 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_
intg_err.2443078660
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1948982573
Short name T952
Test name
Test status
Simulation time 40623700 ps
CPU time 1.23 seconds
Started Aug 23 08:17:34 AM UTC 24
Finished Aug 23 08:17:36 AM UTC 24
Peak memory 230516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1948982573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1948982573
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2535115171
Short name T948
Test name
Test status
Simulation time 152828923 ps
CPU time 0.84 seconds
Started Aug 23 08:17:34 AM UTC 24
Finished Aug 23 08:17:35 AM UTC 24
Peak memory 218224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535115171 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2535115171
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2169338775
Short name T946
Test name
Test status
Simulation time 42949786 ps
CPU time 1.56 seconds
Started Aug 23 08:17:32 AM UTC 24
Finished Aug 23 08:17:35 AM UTC 24
Peak memory 218808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=2169338775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2169338775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2411628582
Short name T998
Test name
Test status
Simulation time 2687552797 ps
CPU time 26.58 seconds
Started Aug 23 08:17:32 AM UTC 24
Finished Aug 23 08:18:00 AM UTC 24
Peak memory 219384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2411628582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2411628582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.544475749
Short name T987
Test name
Test status
Simulation time 697831276 ps
CPU time 10.12 seconds
Started Aug 23 08:17:32 AM UTC 24
Finished Aug 23 08:17:43 AM UTC 24
Peak memory 218200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=544475749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.544475749
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.266892105
Short name T947
Test name
Test status
Simulation time 827468060 ps
CPU time 2.95 seconds
Started Aug 23 08:17:31 AM UTC 24
Finished Aug 23 08:17:35 AM UTC 24
Peak memory 221436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri
scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=266892105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.266892105
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3841400629
Short name T951
Test name
Test status
Simulation time 777483767 ps
CPU time 2.32 seconds
Started Aug 23 08:17:32 AM UTC 24
Finished Aug 23 08:17:36 AM UTC 24
Peak memory 233928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim
eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841400629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_en
abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3841400629
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1361842651
Short name T949
Test name
Test status
Simulation time 267246065 ps
CPU time 2.23 seconds
Started Aug 23 08:17:32 AM UTC 24
Finished Aug 23 08:17:35 AM UTC 24
Peak memory 219772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma
p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1361842651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_rw.1361842651
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3539251897
Short name T945
Test name
Test status
Simulation time 30661879 ps
CPU time 1.35 seconds
Started Aug 23 08:17:32 AM UTC 24
Finished Aug 23 08:17:35 AM UTC 24
Peak memory 218700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr
eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3539251897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3539251897
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3742609537
Short name T955
Test name
Test status
Simulation time 77734252 ps
CPU time 1.6 seconds
Started Aug 23 08:17:34 AM UTC 24
Finished Aug 23 08:17:36 AM UTC 24
Peak memory 220808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374260
9537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc
_ctrl_same_csr_outstanding.3742609537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2247472023
Short name T964
Test name
Test status
Simulation time 389987863 ps
CPU time 2.94 seconds
Started Aug 23 08:17:33 AM UTC 24
Finished Aug 23 08:17:37 AM UTC 24
Peak memory 230048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247472023 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2247472023
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3978045502
Short name T121
Test name
Test status
Simulation time 156507242 ps
CPU time 1.98 seconds
Started Aug 23 08:17:33 AM UTC 24
Finished Aug 23 08:17:36 AM UTC 24
Peak memory 232624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978045502 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_
intg_err.3978045502
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2941581720
Short name T13
Test name
Test status
Simulation time 436345417 ps
CPU time 7.48 seconds
Started Aug 23 09:41:18 AM UTC 24
Finished Aug 23 09:41:27 AM UTC 24
Peak memory 229900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941581720 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2941581720
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.1160142598
Short name T8
Test name
Test status
Simulation time 2524015808 ps
CPU time 13.31 seconds
Started Aug 23 09:41:38 AM UTC 24
Finished Aug 23 09:41:52 AM UTC 24
Peak memory 229612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160142598 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1160142598
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1019783664
Short name T6
Test name
Test status
Simulation time 122356507 ps
CPU time 3.68 seconds
Started Aug 23 09:41:33 AM UTC 24
Finished Aug 23 09:41:38 AM UTC 24
Peak memory 229840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019783664
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_jtag_prog_failure.1019783664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3910085600
Short name T18
Test name
Test status
Simulation time 823892900 ps
CPU time 15.71 seconds
Started Aug 23 09:41:43 AM UTC 24
Finished Aug 23 09:42:00 AM UTC 24
Peak memory 229484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910085600
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_
ctrl_jtag_regwen_during_op.3910085600
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.3033583748
Short name T5
Test name
Test status
Simulation time 368524308 ps
CPU time 3.01 seconds
Started Aug 23 09:41:28 AM UTC 24
Finished Aug 23 09:41:32 AM UTC 24
Peak memory 229560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033583748
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_s
moke.3033583748
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.1110526727
Short name T22
Test name
Test status
Simulation time 4555482927 ps
CPU time 72.7 seconds
Started Aug 23 09:41:29 AM UTC 24
Finished Aug 23 09:42:43 AM UTC 24
Peak memory 295336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110526727
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_jtag_state_failure.1110526727
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3329603054
Short name T7
Test name
Test status
Simulation time 970749941 ps
CPU time 10.82 seconds
Started Aug 23 09:41:31 AM UTC 24
Finished Aug 23 09:41:43 AM UTC 24
Peak memory 262436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329603054
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_
ctrl_jtag_state_post_trans.3329603054
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1458547395
Short name T4
Test name
Test status
Simulation time 95458987 ps
CPU time 1.78 seconds
Started Aug 23 09:41:16 AM UTC 24
Finished Aug 23 09:41:19 AM UTC 24
Peak memory 229912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458547395 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1458547395
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.1361882275
Short name T16
Test name
Test status
Simulation time 1591334745 ps
CPU time 12.03 seconds
Started Aug 23 09:41:24 AM UTC 24
Finished Aug 23 09:41:37 AM UTC 24
Peak memory 229636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361882275 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1361882275
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.429027828
Short name T33
Test name
Test status
Simulation time 6801915855 ps
CPU time 11.11 seconds
Started Aug 23 09:41:54 AM UTC 24
Finished Aug 23 09:42:06 AM UTC 24
Peak memory 231872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429027828 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_toke
n_digest.429027828
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.1771632205
Short name T2
Test name
Test status
Simulation time 1193648916 ps
CPU time 7.49 seconds
Started Aug 23 09:40:58 AM UTC 24
Finished Aug 23 09:41:07 AM UTC 24
Peak memory 229552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771632205 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1771632205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.862781414
Short name T3
Test name
Test status
Simulation time 169106838 ps
CPU time 7.34 seconds
Started Aug 23 09:41:07 AM UTC 24
Finished Aug 23 09:41:16 AM UTC 24
Peak memory 260784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862781414 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.862781414
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2030008192
Short name T1
Test name
Test status
Simulation time 40608925 ps
CPU time 0.8 seconds
Started Aug 23 09:40:59 AM UTC 24
Finished Aug 23 09:41:01 AM UTC 24
Peak memory 222904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030008192 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.
lc_ctrl_volatile_unlock_smoke.2030008192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.971225341
Short name T98
Test name
Test status
Simulation time 54359120 ps
CPU time 0.89 seconds
Started Aug 23 09:43:01 AM UTC 24
Finished Aug 23 09:43:02 AM UTC 24
Peak memory 218644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971225341 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.971225341
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.3992705317
Short name T104
Test name
Test status
Simulation time 87460455 ps
CPU time 0.71 seconds
Started Aug 23 09:42:24 AM UTC 24
Finished Aug 23 09:42:26 AM UTC 24
Peak memory 218372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992705317 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3992705317
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.1939409128
Short name T43
Test name
Test status
Simulation time 409963051 ps
CPU time 11.4 seconds
Started Aug 23 09:42:14 AM UTC 24
Finished Aug 23 09:42:27 AM UTC 24
Peak memory 237588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939409128 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1939409128
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.3997195859
Short name T95
Test name
Test status
Simulation time 1433547592 ps
CPU time 40.8 seconds
Started Aug 23 09:42:34 AM UTC 24
Finished Aug 23 09:43:16 AM UTC 24
Peak memory 231892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997195859
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jt
ag_errors.3997195859
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.3859818739
Short name T10
Test name
Test status
Simulation time 1135785341 ps
CPU time 12.96 seconds
Started Aug 23 09:42:43 AM UTC 24
Finished Aug 23 09:42:57 AM UTC 24
Peak memory 229612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859818739 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_prior
ity.3859818739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.1987442007
Short name T185
Test name
Test status
Simulation time 940164431 ps
CPU time 12.55 seconds
Started Aug 23 09:42:34 AM UTC 24
Finished Aug 23 09:42:48 AM UTC 24
Peak memory 231888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987442007
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_jtag_prog_failure.1987442007
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2525911858
Short name T73
Test name
Test status
Simulation time 2313328992 ps
CPU time 14.51 seconds
Started Aug 23 09:42:44 AM UTC 24
Finished Aug 23 09:43:00 AM UTC 24
Peak memory 229692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525911858
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_
ctrl_jtag_regwen_during_op.2525911858
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.3843342924
Short name T20
Test name
Test status
Simulation time 587851878 ps
CPU time 4.45 seconds
Started Aug 23 09:42:28 AM UTC 24
Finished Aug 23 09:42:33 AM UTC 24
Peak memory 229540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843342924
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_s
moke.3843342924
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.984624393
Short name T186
Test name
Test status
Simulation time 1056612046 ps
CPU time 26.93 seconds
Started Aug 23 09:42:28 AM UTC 24
Finished Aug 23 09:42:56 AM UTC 24
Peak memory 262452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984624393 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_jtag_state_failure.984624393
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.1698728430
Short name T21
Test name
Test status
Simulation time 776063656 ps
CPU time 13.02 seconds
Started Aug 23 09:42:28 AM UTC 24
Finished Aug 23 09:42:42 AM UTC 24
Peak memory 262436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698728430
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_
ctrl_jtag_state_post_trans.1698728430
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.3716800262
Short name T36
Test name
Test status
Simulation time 67720787 ps
CPU time 2.65 seconds
Started Aug 23 09:42:10 AM UTC 24
Finished Aug 23 09:42:14 AM UTC 24
Peak memory 231888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716800262 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3716800262
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.996780408
Short name T67
Test name
Test status
Simulation time 555048240 ps
CPU time 19.54 seconds
Started Aug 23 09:42:59 AM UTC 24
Finished Aug 23 09:43:20 AM UTC 24
Peak memory 289900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996780408 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.996780408
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.3161279141
Short name T41
Test name
Test status
Simulation time 828022410 ps
CPU time 9.05 seconds
Started Aug 23 09:42:44 AM UTC 24
Finished Aug 23 09:42:54 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161279141 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3161279141
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.957883050
Short name T42
Test name
Test status
Simulation time 1690751839 ps
CPU time 10.53 seconds
Started Aug 23 09:42:55 AM UTC 24
Finished Aug 23 09:43:07 AM UTC 24
Peak memory 231800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957883050 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_toke
n_digest.957883050
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.3255919352
Short name T47
Test name
Test status
Simulation time 3467958359 ps
CPU time 9.37 seconds
Started Aug 23 09:42:48 AM UTC 24
Finished Aug 23 09:42:59 AM UTC 24
Peak memory 232004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255919352 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_
mux.3255919352
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1254713075
Short name T35
Test name
Test status
Simulation time 138091818 ps
CPU time 2.42 seconds
Started Aug 23 09:42:06 AM UTC 24
Finished Aug 23 09:42:09 AM UTC 24
Peak memory 225800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254713075 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1254713075
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.2346449245
Short name T37
Test name
Test status
Simulation time 131295983 ps
CPU time 4.35 seconds
Started Aug 23 09:42:10 AM UTC 24
Finished Aug 23 09:42:15 AM UTC 24
Peak memory 236040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346449245 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2346449245
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.2404942927
Short name T345
Test name
Test status
Simulation time 18301765 ps
CPU time 0.98 seconds
Started Aug 23 09:48:29 AM UTC 24
Finished Aug 23 09:48:31 AM UTC 24
Peak memory 218760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404942927 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2404942927
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.2567458574
Short name T340
Test name
Test status
Simulation time 284755063 ps
CPU time 10.93 seconds
Started Aug 23 09:48:12 AM UTC 24
Finished Aug 23 09:48:24 AM UTC 24
Peak memory 237660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567458574 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2567458574
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.3726082701
Short name T341
Test name
Test status
Simulation time 1194365595 ps
CPU time 3.55 seconds
Started Aug 23 09:48:21 AM UTC 24
Finished Aug 23 09:48:26 AM UTC 24
Peak memory 229548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726082701 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3726082701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.3777037908
Short name T356
Test name
Test status
Simulation time 11067991535 ps
CPU time 32.98 seconds
Started Aug 23 09:48:21 AM UTC 24
Finished Aug 23 09:48:56 AM UTC 24
Peak memory 237652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777037908
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_j
tag_errors.3777037908
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.756927902
Short name T344
Test name
Test status
Simulation time 519253663 ps
CPU time 7.6 seconds
Started Aug 23 09:48:20 AM UTC 24
Finished Aug 23 09:48:29 AM UTC 24
Peak memory 232148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756927902 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_prog_failure.756927902
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.3833331046
Short name T82
Test name
Test status
Simulation time 726106928 ps
CPU time 3.59 seconds
Started Aug 23 09:48:15 AM UTC 24
Finished Aug 23 09:48:20 AM UTC 24
Peak memory 229560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833331046
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_
smoke.3833331046
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.3229066076
Short name T366
Test name
Test status
Simulation time 2586123487 ps
CPU time 55.67 seconds
Started Aug 23 09:48:15 AM UTC 24
Finished Aug 23 09:49:12 AM UTC 24
Peak memory 287100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229066076
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_jtag_state_failure.3229066076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.1815797373
Short name T346
Test name
Test status
Simulation time 582638744 ps
CPU time 13.76 seconds
Started Aug 23 09:48:18 AM UTC 24
Finished Aug 23 09:48:33 AM UTC 24
Peak memory 260388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815797373
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc
_ctrl_jtag_state_post_trans.1815797373
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.660453917
Short name T337
Test name
Test status
Simulation time 103772269 ps
CPU time 1.84 seconds
Started Aug 23 09:48:11 AM UTC 24
Finished Aug 23 09:48:14 AM UTC 24
Peak memory 229916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660453917 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.660453917
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.1573747631
Short name T302
Test name
Test status
Simulation time 1457863532 ps
CPU time 9.09 seconds
Started Aug 23 09:48:25 AM UTC 24
Finished Aug 23 09:48:35 AM UTC 24
Peak memory 237580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573747631 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1573747631
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.3556175295
Short name T350
Test name
Test status
Simulation time 1416189735 ps
CPU time 9.84 seconds
Started Aug 23 09:48:27 AM UTC 24
Finished Aug 23 09:48:38 AM UTC 24
Peak memory 231808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556175295 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_to
ken_digest.3556175295
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.1338989895
Short name T347
Test name
Test status
Simulation time 425216829 ps
CPU time 7.38 seconds
Started Aug 23 09:48:25 AM UTC 24
Finished Aug 23 09:48:33 AM UTC 24
Peak memory 231952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338989895 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token
_mux.1338989895
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.1789128597
Short name T331
Test name
Test status
Simulation time 628900194 ps
CPU time 3.54 seconds
Started Aug 23 09:48:02 AM UTC 24
Finished Aug 23 09:48:07 AM UTC 24
Peak memory 236092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789128597 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1789128597
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.2816643594
Short name T348
Test name
Test status
Simulation time 851696320 ps
CPU time 24.07 seconds
Started Aug 23 09:48:09 AM UTC 24
Finished Aug 23 09:48:35 AM UTC 24
Peak memory 262700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816643594 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2816643594
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.302421674
Short name T83
Test name
Test status
Simulation time 21429658707 ps
CPU time 92.87 seconds
Started Aug 23 09:48:28 AM UTC 24
Finished Aug 23 09:50:03 AM UTC 24
Peak memory 281020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=302421674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 10.lc_ctrl_stress_all.302421674
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3533261408
Short name T334
Test name
Test status
Simulation time 82386011 ps
CPU time 0.78 seconds
Started Aug 23 09:48:07 AM UTC 24
Finished Aug 23 09:48:10 AM UTC 24
Peak memory 218552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533261408 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10
.lc_ctrl_volatile_unlock_smoke.3533261408
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.2624408271
Short name T361
Test name
Test status
Simulation time 27821574 ps
CPU time 0.88 seconds
Started Aug 23 09:49:02 AM UTC 24
Finished Aug 23 09:49:04 AM UTC 24
Peak memory 218872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624408271 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2624408271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.3652333966
Short name T355
Test name
Test status
Simulation time 340934185 ps
CPU time 11.49 seconds
Started Aug 23 09:48:37 AM UTC 24
Finished Aug 23 09:48:49 AM UTC 24
Peak memory 237588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652333966 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3652333966
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.4048919128
Short name T32
Test name
Test status
Simulation time 937674430 ps
CPU time 3.56 seconds
Started Aug 23 09:48:48 AM UTC 24
Finished Aug 23 09:48:53 AM UTC 24
Peak memory 229620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048919128 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.4048919128
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.3818488107
Short name T375
Test name
Test status
Simulation time 4414197327 ps
CPU time 52.21 seconds
Started Aug 23 09:48:45 AM UTC 24
Finished Aug 23 09:49:39 AM UTC 24
Peak memory 237920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818488107
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_j
tag_errors.3818488107
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.874161664
Short name T354
Test name
Test status
Simulation time 747542149 ps
CPU time 3.77 seconds
Started Aug 23 09:48:44 AM UTC 24
Finished Aug 23 09:48:49 AM UTC 24
Peak memory 231824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874161664 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_prog_failure.874161664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.1637945009
Short name T353
Test name
Test status
Simulation time 588018257 ps
CPU time 6.67 seconds
Started Aug 23 09:48:37 AM UTC 24
Finished Aug 23 09:48:45 AM UTC 24
Peak memory 229496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637945009
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_
smoke.1637945009
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.2801158139
Short name T171
Test name
Test status
Simulation time 4989370861 ps
CPU time 78.88 seconds
Started Aug 23 09:48:39 AM UTC 24
Finished Aug 23 09:49:59 AM UTC 24
Peak memory 289172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801158139
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_jtag_state_failure.2801158139
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.2111992387
Short name T357
Test name
Test status
Simulation time 2043162494 ps
CPU time 15.94 seconds
Started Aug 23 09:48:40 AM UTC 24
Finished Aug 23 09:48:57 AM UTC 24
Peak memory 262432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111992387
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc
_ctrl_jtag_state_post_trans.2111992387
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.3153663290
Short name T351
Test name
Test status
Simulation time 245953058 ps
CPU time 2.29 seconds
Started Aug 23 09:48:36 AM UTC 24
Finished Aug 23 09:48:39 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153663290 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3153663290
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.1088560050
Short name T360
Test name
Test status
Simulation time 2148490852 ps
CPU time 13.01 seconds
Started Aug 23 09:48:49 AM UTC 24
Finished Aug 23 09:49:03 AM UTC 24
Peak memory 232268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088560050 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1088560050
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.798234575
Short name T364
Test name
Test status
Simulation time 1386531134 ps
CPU time 14.9 seconds
Started Aug 23 09:48:54 AM UTC 24
Finished Aug 23 09:49:09 AM UTC 24
Peak memory 231800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798234575 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_tok
en_digest.798234575
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.2631513627
Short name T358
Test name
Test status
Simulation time 2551609529 ps
CPU time 8.84 seconds
Started Aug 23 09:48:50 AM UTC 24
Finished Aug 23 09:49:00 AM UTC 24
Peak memory 237988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631513627 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token
_mux.2631513627
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.3809736421
Short name T217
Test name
Test status
Simulation time 837628268 ps
CPU time 9.23 seconds
Started Aug 23 09:48:37 AM UTC 24
Finished Aug 23 09:48:47 AM UTC 24
Peak memory 231944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809736421 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3809736421
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.1115393393
Short name T89
Test name
Test status
Simulation time 160171168 ps
CPU time 2.2 seconds
Started Aug 23 09:48:32 AM UTC 24
Finished Aug 23 09:48:36 AM UTC 24
Peak memory 229548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115393393 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1115393393
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.1560137525
Short name T359
Test name
Test status
Simulation time 227678034 ps
CPU time 24.76 seconds
Started Aug 23 09:48:34 AM UTC 24
Finished Aug 23 09:49:01 AM UTC 24
Peak memory 260268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560137525 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1560137525
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.680330904
Short name T352
Test name
Test status
Simulation time 152642138 ps
CPU time 6.25 seconds
Started Aug 23 09:48:36 AM UTC 24
Finished Aug 23 09:48:43 AM UTC 24
Peak memory 260440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680330904 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.680330904
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.3374612173
Short name T141
Test name
Test status
Simulation time 5705561336 ps
CPU time 53.94 seconds
Started Aug 23 09:48:58 AM UTC 24
Finished Aug 23 09:49:53 AM UTC 24
Peak memory 289320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374612173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_u
nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.3374612173
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4126256465
Short name T349
Test name
Test status
Simulation time 31568939 ps
CPU time 0.65 seconds
Started Aug 23 09:48:34 AM UTC 24
Finished Aug 23 09:48:36 AM UTC 24
Peak memory 217848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126256465 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11
.lc_ctrl_volatile_unlock_smoke.4126256465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.2279697997
Short name T377
Test name
Test status
Simulation time 17368860 ps
CPU time 0.96 seconds
Started Aug 23 09:49:40 AM UTC 24
Finished Aug 23 09:49:42 AM UTC 24
Peak memory 218584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279697997 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2279697997
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.4095483853
Short name T372
Test name
Test status
Simulation time 1920489004 ps
CPU time 13.69 seconds
Started Aug 23 09:49:10 AM UTC 24
Finished Aug 23 09:49:25 AM UTC 24
Peak memory 237588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095483853 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.4095483853
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.133056868
Short name T191
Test name
Test status
Simulation time 6372457928 ps
CPU time 8.72 seconds
Started Aug 23 09:49:23 AM UTC 24
Finished Aug 23 09:49:33 AM UTC 24
Peak memory 229620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133056868 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.133056868
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.1500819355
Short name T384
Test name
Test status
Simulation time 1736835070 ps
CPU time 43.59 seconds
Started Aug 23 09:49:22 AM UTC 24
Finished Aug 23 09:50:07 AM UTC 24
Peak memory 237592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500819355
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_j
tag_errors.1500819355
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.665585067
Short name T371
Test name
Test status
Simulation time 409647707 ps
CPU time 1.84 seconds
Started Aug 23 09:49:22 AM UTC 24
Finished Aug 23 09:49:25 AM UTC 24
Peak memory 229912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665585067 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_prog_failure.665585067
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.2617530455
Short name T368
Test name
Test status
Simulation time 393255524 ps
CPU time 6.49 seconds
Started Aug 23 09:49:13 AM UTC 24
Finished Aug 23 09:49:20 AM UTC 24
Peak memory 229488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617530455
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_
smoke.2617530455
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.1515166093
Short name T387
Test name
Test status
Simulation time 8344167419 ps
CPU time 53.2 seconds
Started Aug 23 09:49:14 AM UTC 24
Finished Aug 23 09:50:08 AM UTC 24
Peak memory 281156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515166093
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_jtag_state_failure.1515166093
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.3920612743
Short name T373
Test name
Test status
Simulation time 1165085480 ps
CPU time 11.63 seconds
Started Aug 23 09:49:22 AM UTC 24
Finished Aug 23 09:49:35 AM UTC 24
Peak memory 262512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920612743
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc
_ctrl_jtag_state_post_trans.3920612743
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.2988154657
Short name T365
Test name
Test status
Simulation time 97609932 ps
CPU time 1.45 seconds
Started Aug 23 09:49:07 AM UTC 24
Finished Aug 23 09:49:10 AM UTC 24
Peak memory 231968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988154657 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2988154657
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.88596879
Short name T378
Test name
Test status
Simulation time 469171564 ps
CPU time 17.12 seconds
Started Aug 23 09:49:25 AM UTC 24
Finished Aug 23 09:49:43 AM UTC 24
Peak memory 237584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88596879 -assert nopost
proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.88596879
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.3416483052
Short name T376
Test name
Test status
Simulation time 438766188 ps
CPU time 9.29 seconds
Started Aug 23 09:49:30 AM UTC 24
Finished Aug 23 09:49:41 AM UTC 24
Peak memory 232136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416483052 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_to
ken_digest.3416483052
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.551955151
Short name T374
Test name
Test status
Simulation time 423654210 ps
CPU time 11.13 seconds
Started Aug 23 09:49:26 AM UTC 24
Finished Aug 23 09:49:38 AM UTC 24
Peak memory 237920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551955151 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_
mux.551955151
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.2809694255
Short name T362
Test name
Test status
Simulation time 65552057 ps
CPU time 1.54 seconds
Started Aug 23 09:49:02 AM UTC 24
Finished Aug 23 09:49:05 AM UTC 24
Peak memory 222312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809694255 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2809694255
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.785327659
Short name T370
Test name
Test status
Simulation time 731562867 ps
CPU time 14.73 seconds
Started Aug 23 09:49:05 AM UTC 24
Finished Aug 23 09:49:21 AM UTC 24
Peak memory 260520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785327659 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.785327659
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.1160515104
Short name T367
Test name
Test status
Simulation time 86459605 ps
CPU time 6.14 seconds
Started Aug 23 09:49:05 AM UTC 24
Finished Aug 23 09:49:12 AM UTC 24
Peak memory 260384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160515104 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1160515104
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.2131742691
Short name T386
Test name
Test status
Simulation time 2286917487 ps
CPU time 32.88 seconds
Started Aug 23 09:49:33 AM UTC 24
Finished Aug 23 09:50:08 AM UTC 24
Peak memory 252324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2131742691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 12.lc_ctrl_stress_all.2131742691
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.247748633
Short name T142
Test name
Test status
Simulation time 3395586055 ps
CPU time 71.45 seconds
Started Aug 23 09:49:35 AM UTC 24
Finished Aug 23 09:50:48 AM UTC 24
Peak memory 272928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247748633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S
EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_un
lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.247748633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.904590438
Short name T363
Test name
Test status
Simulation time 41676262 ps
CPU time 0.77 seconds
Started Aug 23 09:49:04 AM UTC 24
Finished Aug 23 09:49:06 AM UTC 24
Peak memory 218948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904590438 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.
lc_ctrl_volatile_unlock_smoke.904590438
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.2502485159
Short name T385
Test name
Test status
Simulation time 43061044 ps
CPU time 1.07 seconds
Started Aug 23 09:50:06 AM UTC 24
Finished Aug 23 09:50:08 AM UTC 24
Peak memory 218584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502485159 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2502485159
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_errors.3429461118
Short name T169
Test name
Test status
Simulation time 328289533 ps
CPU time 10.2 seconds
Started Aug 23 09:49:45 AM UTC 24
Finished Aug 23 09:49:56 AM UTC 24
Peak memory 237916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429461118 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3429461118
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.3469701262
Short name T175
Test name
Test status
Simulation time 895387183 ps
CPU time 3.48 seconds
Started Aug 23 09:50:00 AM UTC 24
Finished Aug 23 09:50:04 AM UTC 24
Peak memory 229732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469701262 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3469701262
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.2403140352
Short name T399
Test name
Test status
Simulation time 2750317780 ps
CPU time 33.58 seconds
Started Aug 23 09:49:57 AM UTC 24
Finished Aug 23 09:50:32 AM UTC 24
Peak memory 231940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403140352
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_j
tag_errors.2403140352
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.1108259960
Short name T172
Test name
Test status
Simulation time 263283147 ps
CPU time 4.44 seconds
Started Aug 23 09:49:55 AM UTC 24
Finished Aug 23 09:50:00 AM UTC 24
Peak memory 231816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108259960
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_jtag_prog_failure.1108259960
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.2411841903
Short name T90
Test name
Test status
Simulation time 725000803 ps
CPU time 4.93 seconds
Started Aug 23 09:49:48 AM UTC 24
Finished Aug 23 09:49:54 AM UTC 24
Peak memory 229692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411841903
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_
smoke.2411841903
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.1565725164
Short name T406
Test name
Test status
Simulation time 7396754004 ps
CPU time 43.17 seconds
Started Aug 23 09:49:53 AM UTC 24
Finished Aug 23 09:50:37 AM UTC 24
Peak memory 287504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565725164
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_jtag_state_failure.1565725164
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.3796409184
Short name T174
Test name
Test status
Simulation time 311267211 ps
CPU time 9.13 seconds
Started Aug 23 09:49:54 AM UTC 24
Finished Aug 23 09:50:04 AM UTC 24
Peak memory 260464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796409184
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc
_ctrl_jtag_state_post_trans.3796409184
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.2071336865
Short name T381
Test name
Test status
Simulation time 139412515 ps
CPU time 2 seconds
Started Aug 23 09:49:44 AM UTC 24
Finished Aug 23 09:49:47 AM UTC 24
Peak memory 231968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071336865 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2071336865
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.1833549538
Short name T388
Test name
Test status
Simulation time 2115617841 ps
CPU time 9.09 seconds
Started Aug 23 09:50:00 AM UTC 24
Finished Aug 23 09:50:10 AM UTC 24
Peak memory 237576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833549538 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1833549538
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.2907564498
Short name T392
Test name
Test status
Simulation time 329259231 ps
CPU time 9.17 seconds
Started Aug 23 09:50:03 AM UTC 24
Finished Aug 23 09:50:14 AM UTC 24
Peak memory 231808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907564498 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_to
ken_digest.2907564498
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.392150952
Short name T389
Test name
Test status
Simulation time 597642089 ps
CPU time 8.47 seconds
Started Aug 23 09:50:01 AM UTC 24
Finished Aug 23 09:50:11 AM UTC 24
Peak memory 231952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392150952 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_
mux.392150952
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.2395057805
Short name T170
Test name
Test status
Simulation time 1070306540 ps
CPU time 9.2 seconds
Started Aug 23 09:49:48 AM UTC 24
Finished Aug 23 09:49:59 AM UTC 24
Peak memory 231944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395057805 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2395057805
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.3818522571
Short name T380
Test name
Test status
Simulation time 119222228 ps
CPU time 3.36 seconds
Started Aug 23 09:49:40 AM UTC 24
Finished Aug 23 09:49:44 AM UTC 24
Peak memory 229548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818522571 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3818522571
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.79686046
Short name T173
Test name
Test status
Simulation time 267361639 ps
CPU time 20.06 seconds
Started Aug 23 09:49:42 AM UTC 24
Finished Aug 23 09:50:03 AM UTC 24
Peak memory 262504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79686046 -assert nopostproc +UVM_TESTNAME=lc_ctr
l_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.79686046
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.1031240990
Short name T383
Test name
Test status
Simulation time 71799781 ps
CPU time 6.68 seconds
Started Aug 23 09:49:44 AM UTC 24
Finished Aug 23 09:49:52 AM UTC 24
Peak memory 262576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031240990 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1031240990
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.2525185032
Short name T458
Test name
Test status
Simulation time 69421016560 ps
CPU time 123.13 seconds
Started Aug 23 09:50:03 AM UTC 24
Finished Aug 23 09:52:09 AM UTC 24
Peak memory 231944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2525185032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 13.lc_ctrl_stress_all.2525185032
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.265048034
Short name T379
Test name
Test status
Simulation time 22796442 ps
CPU time 0.89 seconds
Started Aug 23 09:49:42 AM UTC 24
Finished Aug 23 09:49:44 AM UTC 24
Peak memory 222384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265048034 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.
lc_ctrl_volatile_unlock_smoke.265048034
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.325955298
Short name T404
Test name
Test status
Simulation time 19939218 ps
CPU time 0.8 seconds
Started Aug 23 09:50:34 AM UTC 24
Finished Aug 23 09:50:36 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325955298 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.325955298
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_errors.922507687
Short name T396
Test name
Test status
Simulation time 1683151399 ps
CPU time 10.77 seconds
Started Aug 23 09:50:11 AM UTC 24
Finished Aug 23 09:50:23 AM UTC 24
Peak memory 231948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922507687 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.922507687
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.2999008068
Short name T398
Test name
Test status
Simulation time 741504475 ps
CPU time 6.24 seconds
Started Aug 23 09:50:21 AM UTC 24
Finished Aug 23 09:50:28 AM UTC 24
Peak memory 229620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999008068 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2999008068
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.2707857179
Short name T179
Test name
Test status
Simulation time 3033538228 ps
CPU time 37.83 seconds
Started Aug 23 09:50:18 AM UTC 24
Finished Aug 23 09:50:57 AM UTC 24
Peak memory 232264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707857179
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_j
tag_errors.2707857179
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.2187888141
Short name T403
Test name
Test status
Simulation time 2154169738 ps
CPU time 14.86 seconds
Started Aug 23 09:50:18 AM UTC 24
Finished Aug 23 09:50:34 AM UTC 24
Peak memory 231868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187888141
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_jtag_prog_failure.2187888141
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.1495809207
Short name T395
Test name
Test status
Simulation time 629071882 ps
CPU time 6.68 seconds
Started Aug 23 09:50:12 AM UTC 24
Finished Aug 23 09:50:20 AM UTC 24
Peak memory 229560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495809207
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_
smoke.1495809207
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.3126812331
Short name T412
Test name
Test status
Simulation time 4306284881 ps
CPU time 25.69 seconds
Started Aug 23 09:50:14 AM UTC 24
Finished Aug 23 09:50:41 AM UTC 24
Peak memory 264900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126812331
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_jtag_state_failure.3126812331
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.3949657954
Short name T405
Test name
Test status
Simulation time 1239642481 ps
CPU time 21.48 seconds
Started Aug 23 09:50:14 AM UTC 24
Finished Aug 23 09:50:37 AM UTC 24
Peak memory 262432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949657954
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc
_ctrl_jtag_state_post_trans.3949657954
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.4062885922
Short name T393
Test name
Test status
Simulation time 303233629 ps
CPU time 1.89 seconds
Started Aug 23 09:50:11 AM UTC 24
Finished Aug 23 09:50:14 AM UTC 24
Peak memory 231968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062885922 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.4062885922
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.1510397355
Short name T402
Test name
Test status
Simulation time 848416161 ps
CPU time 10.21 seconds
Started Aug 23 09:50:22 AM UTC 24
Finished Aug 23 09:50:33 AM UTC 24
Peak memory 237720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510397355 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1510397355
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.1761167164
Short name T400
Test name
Test status
Simulation time 236247522 ps
CPU time 7.18 seconds
Started Aug 23 09:50:24 AM UTC 24
Finished Aug 23 09:50:32 AM UTC 24
Peak memory 232136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761167164 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_to
ken_digest.1761167164
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.3192865848
Short name T407
Test name
Test status
Simulation time 2731333596 ps
CPU time 12.74 seconds
Started Aug 23 09:50:24 AM UTC 24
Finished Aug 23 09:50:38 AM UTC 24
Peak memory 232276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192865848 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token
_mux.3192865848
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.74558172
Short name T397
Test name
Test status
Simulation time 1170668248 ps
CPU time 11.52 seconds
Started Aug 23 09:50:11 AM UTC 24
Finished Aug 23 09:50:24 AM UTC 24
Peak memory 232208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74558172 -assert nopostproc +UVM_TESTNAME=lc_ctr
l_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.74558172
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.908059673
Short name T391
Test name
Test status
Simulation time 73596172 ps
CPU time 2.42 seconds
Started Aug 23 09:50:08 AM UTC 24
Finished Aug 23 09:50:11 AM UTC 24
Peak memory 229560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908059673 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.908059673
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.1008303941
Short name T401
Test name
Test status
Simulation time 2172541669 ps
CPU time 22.21 seconds
Started Aug 23 09:50:09 AM UTC 24
Finished Aug 23 09:50:32 AM UTC 24
Peak memory 262604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008303941 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1008303941
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.2679662964
Short name T394
Test name
Test status
Simulation time 231955365 ps
CPU time 7.21 seconds
Started Aug 23 09:50:09 AM UTC 24
Finished Aug 23 09:50:17 AM UTC 24
Peak memory 262572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679662964 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2679662964
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.2672960063
Short name T506
Test name
Test status
Simulation time 4896512505 ps
CPU time 154.3 seconds
Started Aug 23 09:50:29 AM UTC 24
Finished Aug 23 09:53:06 AM UTC 24
Peak memory 285092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2672960063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 14.lc_ctrl_stress_all.2672960063
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2271726426
Short name T390
Test name
Test status
Simulation time 24210503 ps
CPU time 0.76 seconds
Started Aug 23 09:50:09 AM UTC 24
Finished Aug 23 09:50:11 AM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271726426 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14
.lc_ctrl_volatile_unlock_smoke.2271726426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.2862635546
Short name T181
Test name
Test status
Simulation time 59365147 ps
CPU time 0.84 seconds
Started Aug 23 09:50:56 AM UTC 24
Finished Aug 23 09:50:58 AM UTC 24
Peak memory 218760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862635546 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2862635546
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_errors.2278629346
Short name T410
Test name
Test status
Simulation time 4255816343 ps
CPU time 13.5 seconds
Started Aug 23 09:50:37 AM UTC 24
Finished Aug 23 09:50:52 AM UTC 24
Peak memory 232024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278629346 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2278629346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.1691065314
Short name T413
Test name
Test status
Simulation time 327476471 ps
CPU time 3.94 seconds
Started Aug 23 09:50:43 AM UTC 24
Finished Aug 23 09:50:48 AM UTC 24
Peak memory 229880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691065314 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1691065314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.2559364639
Short name T419
Test name
Test status
Simulation time 2929969135 ps
CPU time 25.2 seconds
Started Aug 23 09:50:42 AM UTC 24
Finished Aug 23 09:51:08 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559364639
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_j
tag_errors.2559364639
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.1762704907
Short name T178
Test name
Test status
Simulation time 533548473 ps
CPU time 12.9 seconds
Started Aug 23 09:50:42 AM UTC 24
Finished Aug 23 09:50:56 AM UTC 24
Peak memory 231808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762704907
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_jtag_prog_failure.1762704907
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.596266009
Short name T411
Test name
Test status
Simulation time 318924889 ps
CPU time 1.54 seconds
Started Aug 23 09:50:38 AM UTC 24
Finished Aug 23 09:50:41 AM UTC 24
Peak memory 228392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596266009 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_s
moke.596266009
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.712426441
Short name T433
Test name
Test status
Simulation time 2703172991 ps
CPU time 47.55 seconds
Started Aug 23 09:50:38 AM UTC 24
Finished Aug 23 09:51:27 AM UTC 24
Peak memory 289224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712426441 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_jtag_state_failure.712426441
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.3811773620
Short name T184
Test name
Test status
Simulation time 548381350 ps
CPU time 19.14 seconds
Started Aug 23 09:50:42 AM UTC 24
Finished Aug 23 09:51:02 AM UTC 24
Peak memory 262640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811773620
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc
_ctrl_jtag_state_post_trans.3811773620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.1136116352
Short name T408
Test name
Test status
Simulation time 370362503 ps
CPU time 3.06 seconds
Started Aug 23 09:50:36 AM UTC 24
Finished Aug 23 09:50:40 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136116352 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1136116352
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.199828309
Short name T414
Test name
Test status
Simulation time 259765386 ps
CPU time 12.07 seconds
Started Aug 23 09:50:49 AM UTC 24
Finished Aug 23 09:51:02 AM UTC 24
Peak memory 237588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199828309 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.199828309
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.2054809166
Short name T415
Test name
Test status
Simulation time 949523459 ps
CPU time 9.05 seconds
Started Aug 23 09:50:52 AM UTC 24
Finished Aug 23 09:51:02 AM UTC 24
Peak memory 237592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054809166 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_to
ken_digest.2054809166
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.2529745451
Short name T180
Test name
Test status
Simulation time 471589676 ps
CPU time 6.84 seconds
Started Aug 23 09:50:50 AM UTC 24
Finished Aug 23 09:50:58 AM UTC 24
Peak memory 237668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529745451 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token
_mux.2529745451
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.479664090
Short name T177
Test name
Test status
Simulation time 2401461310 ps
CPU time 12.03 seconds
Started Aug 23 09:50:38 AM UTC 24
Finished Aug 23 09:50:52 AM UTC 24
Peak memory 231872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479664090 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.479664090
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.1145219255
Short name T92
Test name
Test status
Simulation time 15181852 ps
CPU time 1.01 seconds
Started Aug 23 09:50:34 AM UTC 24
Finished Aug 23 09:50:36 AM UTC 24
Peak memory 222316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145219255 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1145219255
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.378208183
Short name T182
Test name
Test status
Simulation time 448934039 ps
CPU time 22.28 seconds
Started Aug 23 09:50:35 AM UTC 24
Finished Aug 23 09:50:59 AM UTC 24
Peak memory 260848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378208183 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.378208183
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.1366997666
Short name T409
Test name
Test status
Simulation time 199393119 ps
CPU time 3.35 seconds
Started Aug 23 09:50:36 AM UTC 24
Finished Aug 23 09:50:41 AM UTC 24
Peak memory 234596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366997666 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1366997666
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.2352932232
Short name T157
Test name
Test status
Simulation time 14330968594 ps
CPU time 399.05 seconds
Started Aug 23 09:50:52 AM UTC 24
Finished Aug 23 09:57:36 AM UTC 24
Peak memory 287136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2352932232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 15.lc_ctrl_stress_all.2352932232
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.4111636902
Short name T91
Test name
Test status
Simulation time 47894576 ps
CPU time 0.84 seconds
Started Aug 23 09:50:34 AM UTC 24
Finished Aug 23 09:50:36 AM UTC 24
Peak memory 220328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111636902 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15
.lc_ctrl_volatile_unlock_smoke.4111636902
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.2519102760
Short name T424
Test name
Test status
Simulation time 23096413 ps
CPU time 0.86 seconds
Started Aug 23 09:51:18 AM UTC 24
Finished Aug 23 09:51:20 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519102760 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2519102760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_errors.801084354
Short name T420
Test name
Test status
Simulation time 940704839 ps
CPU time 10.3 seconds
Started Aug 23 09:51:03 AM UTC 24
Finished Aug 23 09:51:14 AM UTC 24
Peak memory 237460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801084354 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.801084354
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.748076539
Short name T423
Test name
Test status
Simulation time 6378479499 ps
CPU time 6.48 seconds
Started Aug 23 09:51:09 AM UTC 24
Finished Aug 23 09:51:17 AM UTC 24
Peak memory 229620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748076539 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.748076539
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.689709599
Short name T454
Test name
Test status
Simulation time 9594268555 ps
CPU time 52.87 seconds
Started Aug 23 09:51:08 AM UTC 24
Finished Aug 23 09:52:03 AM UTC 24
Peak memory 232204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689709599 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_errors.689709599
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.3886660238
Short name T421
Test name
Test status
Simulation time 507864877 ps
CPU time 6.59 seconds
Started Aug 23 09:51:07 AM UTC 24
Finished Aug 23 09:51:15 AM UTC 24
Peak memory 232140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886660238
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_jtag_prog_failure.3886660238
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.2756586845
Short name T93
Test name
Test status
Simulation time 385524975 ps
CPU time 5.78 seconds
Started Aug 23 09:51:03 AM UTC 24
Finished Aug 23 09:51:10 AM UTC 24
Peak memory 229484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756586845
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_
smoke.2756586845
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.3251367761
Short name T481
Test name
Test status
Simulation time 17812308631 ps
CPU time 94.35 seconds
Started Aug 23 09:51:05 AM UTC 24
Finished Aug 23 09:52:41 AM UTC 24
Peak memory 291164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251367761
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_jtag_state_failure.3251367761
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.3012563388
Short name T425
Test name
Test status
Simulation time 614604442 ps
CPU time 12.79 seconds
Started Aug 23 09:51:06 AM UTC 24
Finished Aug 23 09:51:20 AM UTC 24
Peak memory 262512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012563388
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc
_ctrl_jtag_state_post_trans.3012563388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.1872964887
Short name T416
Test name
Test status
Simulation time 223259652 ps
CPU time 3.67 seconds
Started Aug 23 09:51:01 AM UTC 24
Finished Aug 23 09:51:05 AM UTC 24
Peak memory 236172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872964887 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1872964887
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.1082250171
Short name T428
Test name
Test status
Simulation time 329131049 ps
CPU time 9.24 seconds
Started Aug 23 09:51:11 AM UTC 24
Finished Aug 23 09:51:21 AM UTC 24
Peak memory 237656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082250171 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1082250171
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.875131225
Short name T434
Test name
Test status
Simulation time 9238120179 ps
CPU time 14.59 seconds
Started Aug 23 09:51:15 AM UTC 24
Finished Aug 23 09:51:30 AM UTC 24
Peak memory 237584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875131225 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_tok
en_digest.875131225
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.3809700975
Short name T427
Test name
Test status
Simulation time 252040992 ps
CPU time 6.7 seconds
Started Aug 23 09:51:13 AM UTC 24
Finished Aug 23 09:51:21 AM UTC 24
Peak memory 237668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809700975 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token
_mux.3809700975
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.514096623
Short name T422
Test name
Test status
Simulation time 2405944729 ps
CPU time 10.88 seconds
Started Aug 23 09:51:03 AM UTC 24
Finished Aug 23 09:51:15 AM UTC 24
Peak memory 231540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514096623 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.514096623
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.3643681416
Short name T417
Test name
Test status
Simulation time 925973024 ps
CPU time 7.51 seconds
Started Aug 23 09:50:57 AM UTC 24
Finished Aug 23 09:51:06 AM UTC 24
Peak memory 229548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643681416 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3643681416
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.1072751306
Short name T426
Test name
Test status
Simulation time 758874935 ps
CPU time 19.42 seconds
Started Aug 23 09:51:00 AM UTC 24
Finished Aug 23 09:51:20 AM UTC 24
Peak memory 262720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072751306 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1072751306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.1455464463
Short name T418
Test name
Test status
Simulation time 370474816 ps
CPU time 7.05 seconds
Started Aug 23 09:51:00 AM UTC 24
Finished Aug 23 09:51:08 AM UTC 24
Peak memory 262672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455464463 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1455464463
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1711946195
Short name T183
Test name
Test status
Simulation time 163131675 ps
CPU time 0.78 seconds
Started Aug 23 09:50:59 AM UTC 24
Finished Aug 23 09:51:00 AM UTC 24
Peak memory 218228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711946195 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16
.lc_ctrl_volatile_unlock_smoke.1711946195
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.3962736971
Short name T442
Test name
Test status
Simulation time 17231667 ps
CPU time 0.79 seconds
Started Aug 23 09:51:41 AM UTC 24
Finished Aug 23 09:51:43 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962736971 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3962736971
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_errors.1474942753
Short name T435
Test name
Test status
Simulation time 173081672 ps
CPU time 6.86 seconds
Started Aug 23 09:51:24 AM UTC 24
Finished Aug 23 09:51:32 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474942753 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1474942753
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.586981440
Short name T439
Test name
Test status
Simulation time 260176264 ps
CPU time 5.98 seconds
Started Aug 23 09:51:32 AM UTC 24
Finished Aug 23 09:51:39 AM UTC 24
Peak memory 229860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586981440 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.586981440
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.915120426
Short name T472
Test name
Test status
Simulation time 4065855403 ps
CPU time 53.59 seconds
Started Aug 23 09:51:31 AM UTC 24
Finished Aug 23 09:52:27 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915120426 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_errors.915120426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.1630436990
Short name T440
Test name
Test status
Simulation time 370042662 ps
CPU time 9.76 seconds
Started Aug 23 09:51:28 AM UTC 24
Finished Aug 23 09:51:39 AM UTC 24
Peak memory 231808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630436990
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_jtag_prog_failure.1630436990
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.2958738409
Short name T438
Test name
Test status
Simulation time 429091274 ps
CPU time 10.29 seconds
Started Aug 23 09:51:25 AM UTC 24
Finished Aug 23 09:51:36 AM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958738409
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_
smoke.2958738409
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.3754674352
Short name T499
Test name
Test status
Simulation time 3602782084 ps
CPU time 95.81 seconds
Started Aug 23 09:51:26 AM UTC 24
Finished Aug 23 09:53:04 AM UTC 24
Peak memory 291528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754674352
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_jtag_state_failure.3754674352
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.3745661202
Short name T441
Test name
Test status
Simulation time 302533960 ps
CPU time 11.97 seconds
Started Aug 23 09:51:27 AM UTC 24
Finished Aug 23 09:51:40 AM UTC 24
Peak memory 262440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745661202
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc
_ctrl_jtag_state_post_trans.3745661202
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.1967195192
Short name T431
Test name
Test status
Simulation time 61303276 ps
CPU time 2.94 seconds
Started Aug 23 09:51:22 AM UTC 24
Finished Aug 23 09:51:25 AM UTC 24
Peak memory 236176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967195192 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1967195192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.977804095
Short name T449
Test name
Test status
Simulation time 516135737 ps
CPU time 19.54 seconds
Started Aug 23 09:51:33 AM UTC 24
Finished Aug 23 09:51:53 AM UTC 24
Peak memory 237584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977804095 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.977804095
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.2377773961
Short name T448
Test name
Test status
Simulation time 883416270 ps
CPU time 14.16 seconds
Started Aug 23 09:51:37 AM UTC 24
Finished Aug 23 09:51:52 AM UTC 24
Peak memory 231808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377773961 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_to
ken_digest.2377773961
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.3098552753
Short name T444
Test name
Test status
Simulation time 1326404214 ps
CPU time 9.84 seconds
Started Aug 23 09:51:35 AM UTC 24
Finished Aug 23 09:51:46 AM UTC 24
Peak memory 231868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098552753 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token
_mux.3098552753
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.2696183307
Short name T436
Test name
Test status
Simulation time 3844584105 ps
CPU time 9.15 seconds
Started Aug 23 09:51:24 AM UTC 24
Finished Aug 23 09:51:34 AM UTC 24
Peak memory 231944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696183307 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2696183307
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.3896643143
Short name T430
Test name
Test status
Simulation time 389157916 ps
CPU time 2.88 seconds
Started Aug 23 09:51:20 AM UTC 24
Finished Aug 23 09:51:24 AM UTC 24
Peak memory 229628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896643143 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3896643143
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.2541208192
Short name T443
Test name
Test status
Simulation time 440305834 ps
CPU time 22.65 seconds
Started Aug 23 09:51:21 AM UTC 24
Finished Aug 23 09:51:45 AM UTC 24
Peak memory 262896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541208192 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2541208192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.3309803258
Short name T432
Test name
Test status
Simulation time 365378129 ps
CPU time 3.85 seconds
Started Aug 23 09:51:21 AM UTC 24
Finished Aug 23 09:51:26 AM UTC 24
Peak memory 238252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309803258 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3309803258
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.154871746
Short name T503
Test name
Test status
Simulation time 4179201940 ps
CPU time 84.12 seconds
Started Aug 23 09:51:39 AM UTC 24
Finished Aug 23 09:53:05 AM UTC 24
Peak memory 289324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=154871746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 17.lc_ctrl_stress_all.154871746
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.4203682936
Short name T429
Test name
Test status
Simulation time 48893261 ps
CPU time 0.76 seconds
Started Aug 23 09:51:21 AM UTC 24
Finished Aug 23 09:51:23 AM UTC 24
Peak memory 218288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203682936 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17
.lc_ctrl_volatile_unlock_smoke.4203682936
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.2176772365
Short name T462
Test name
Test status
Simulation time 51667417 ps
CPU time 0.94 seconds
Started Aug 23 09:52:09 AM UTC 24
Finished Aug 23 09:52:11 AM UTC 24
Peak memory 218584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176772365 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2176772365
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_errors.481346318
Short name T451
Test name
Test status
Simulation time 271649269 ps
CPU time 8.47 seconds
Started Aug 23 09:51:48 AM UTC 24
Finished Aug 23 09:51:58 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481346318 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.481346318
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.4228962279
Short name T456
Test name
Test status
Simulation time 566708025 ps
CPU time 7.57 seconds
Started Aug 23 09:51:58 AM UTC 24
Finished Aug 23 09:52:07 AM UTC 24
Peak memory 229600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228962279 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.4228962279
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.5631340
Short name T473
Test name
Test status
Simulation time 1590611245 ps
CPU time 31.83 seconds
Started Aug 23 09:51:57 AM UTC 24
Finished Aug 23 09:52:30 AM UTC 24
Peak memory 232148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5631340 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_errors.5631340
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.299501384
Short name T452
Test name
Test status
Simulation time 269772018 ps
CPU time 3.39 seconds
Started Aug 23 09:51:54 AM UTC 24
Finished Aug 23 09:51:58 AM UTC 24
Peak memory 231808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299501384 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_prog_failure.299501384
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.3481841293
Short name T450
Test name
Test status
Simulation time 103723131 ps
CPU time 2.91 seconds
Started Aug 23 09:51:53 AM UTC 24
Finished Aug 23 09:51:56 AM UTC 24
Peak memory 229452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481841293
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_
smoke.3481841293
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.1285241640
Short name T478
Test name
Test status
Simulation time 1375454722 ps
CPU time 45.53 seconds
Started Aug 23 09:51:53 AM UTC 24
Finished Aug 23 09:52:40 AM UTC 24
Peak memory 280900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285241640
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_jtag_state_failure.1285241640
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.3103176156
Short name T464
Test name
Test status
Simulation time 3946694898 ps
CPU time 17.55 seconds
Started Aug 23 09:51:54 AM UTC 24
Finished Aug 23 09:52:12 AM UTC 24
Peak memory 260464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103176156
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc
_ctrl_jtag_state_post_trans.3103176156
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.155368971
Short name T446
Test name
Test status
Simulation time 232814149 ps
CPU time 2.72 seconds
Started Aug 23 09:51:48 AM UTC 24
Finished Aug 23 09:51:52 AM UTC 24
Peak memory 236232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155368971 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.155368971
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.1276944860
Short name T465
Test name
Test status
Simulation time 2123769331 ps
CPU time 15.12 seconds
Started Aug 23 09:51:59 AM UTC 24
Finished Aug 23 09:52:15 AM UTC 24
Peak memory 237588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276944860 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1276944860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.3211797315
Short name T460
Test name
Test status
Simulation time 178538908 ps
CPU time 6.11 seconds
Started Aug 23 09:52:04 AM UTC 24
Finished Aug 23 09:52:11 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211797315 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_to
ken_digest.3211797315
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.1500211248
Short name T459
Test name
Test status
Simulation time 1119336064 ps
CPU time 5.2 seconds
Started Aug 23 09:52:02 AM UTC 24
Finished Aug 23 09:52:09 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500211248 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token
_mux.1500211248
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.2545154472
Short name T453
Test name
Test status
Simulation time 688308314 ps
CPU time 7.67 seconds
Started Aug 23 09:51:53 AM UTC 24
Finished Aug 23 09:52:01 AM UTC 24
Peak memory 231672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545154472 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2545154472
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.1522722405
Short name T72
Test name
Test status
Simulation time 38994512 ps
CPU time 2.44 seconds
Started Aug 23 09:51:43 AM UTC 24
Finished Aug 23 09:51:47 AM UTC 24
Peak memory 225456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522722405 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1522722405
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.3473988880
Short name T457
Test name
Test status
Simulation time 287995451 ps
CPU time 20.26 seconds
Started Aug 23 09:51:47 AM UTC 24
Finished Aug 23 09:52:08 AM UTC 24
Peak memory 258400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473988880 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3473988880
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.1061135689
Short name T447
Test name
Test status
Simulation time 537506118 ps
CPU time 4 seconds
Started Aug 23 09:51:47 AM UTC 24
Finished Aug 23 09:51:52 AM UTC 24
Peak memory 238260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061135689 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1061135689
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.378985744
Short name T556
Test name
Test status
Simulation time 19571746799 ps
CPU time 134.52 seconds
Started Aug 23 09:52:08 AM UTC 24
Finished Aug 23 09:54:25 AM UTC 24
Peak memory 262556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=378985744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 18.lc_ctrl_stress_all.378985744
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3458418368
Short name T445
Test name
Test status
Simulation time 41243206 ps
CPU time 0.71 seconds
Started Aug 23 09:51:46 AM UTC 24
Finished Aug 23 09:51:47 AM UTC 24
Peak memory 218524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458418368 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18
.lc_ctrl_volatile_unlock_smoke.3458418368
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.1078045558
Short name T437
Test name
Test status
Simulation time 58163827 ps
CPU time 0.77 seconds
Started Aug 23 09:52:31 AM UTC 24
Finished Aug 23 09:52:33 AM UTC 24
Peak memory 217368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078045558 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1078045558
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_errors.1281998183
Short name T470
Test name
Test status
Simulation time 1592366123 ps
CPU time 10.31 seconds
Started Aug 23 09:52:13 AM UTC 24
Finished Aug 23 09:52:25 AM UTC 24
Peak memory 231948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281998183 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1281998183
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.3633977812
Short name T471
Test name
Test status
Simulation time 5392224765 ps
CPU time 3.15 seconds
Started Aug 23 09:52:22 AM UTC 24
Finished Aug 23 09:52:27 AM UTC 24
Peak memory 229584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633977812 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3633977812
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.70915752
Short name T527
Test name
Test status
Simulation time 2866302660 ps
CPU time 68.68 seconds
Started Aug 23 09:52:21 AM UTC 24
Finished Aug 23 09:53:32 AM UTC 24
Peak memory 237580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70915752 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_errors.70915752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.1142129501
Short name T463
Test name
Test status
Simulation time 3156582892 ps
CPU time 12.73 seconds
Started Aug 23 09:52:18 AM UTC 24
Finished Aug 23 09:52:32 AM UTC 24
Peak memory 232204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142129501
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_jtag_prog_failure.1142129501
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.1167773829
Short name T466
Test name
Test status
Simulation time 327848786 ps
CPU time 1.5 seconds
Started Aug 23 09:52:13 AM UTC 24
Finished Aug 23 09:52:16 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167773829
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_
smoke.1167773829
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.1918190357
Short name T496
Test name
Test status
Simulation time 2438687429 ps
CPU time 41.81 seconds
Started Aug 23 09:52:17 AM UTC 24
Finished Aug 23 09:53:00 AM UTC 24
Peak memory 262856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918190357
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_jtag_state_failure.1918190357
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.1371394021
Short name T475
Test name
Test status
Simulation time 3129455822 ps
CPU time 12.8 seconds
Started Aug 23 09:52:18 AM UTC 24
Finished Aug 23 09:52:32 AM UTC 24
Peak memory 261240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371394021
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc
_ctrl_jtag_state_post_trans.1371394021
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.3755394701
Short name T467
Test name
Test status
Simulation time 142955769 ps
CPU time 2.83 seconds
Started Aug 23 09:52:13 AM UTC 24
Finished Aug 23 09:52:17 AM UTC 24
Peak memory 235316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755394701 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3755394701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.2744667541
Short name T479
Test name
Test status
Simulation time 1464395726 ps
CPU time 14.54 seconds
Started Aug 23 09:52:24 AM UTC 24
Finished Aug 23 09:52:40 AM UTC 24
Peak memory 232204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744667541 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2744667541
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.811680886
Short name T480
Test name
Test status
Simulation time 1819304953 ps
CPU time 11.9 seconds
Started Aug 23 09:52:28 AM UTC 24
Finished Aug 23 09:52:41 AM UTC 24
Peak memory 231412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811680886 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_tok
en_digest.811680886
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.2368898669
Short name T476
Test name
Test status
Simulation time 645314952 ps
CPU time 10.05 seconds
Started Aug 23 09:52:26 AM UTC 24
Finished Aug 23 09:52:37 AM UTC 24
Peak memory 237668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368898669 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token
_mux.2368898669
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.1965833026
Short name T469
Test name
Test status
Simulation time 1329494473 ps
CPU time 8.7 seconds
Started Aug 23 09:52:13 AM UTC 24
Finished Aug 23 09:52:23 AM UTC 24
Peak memory 237908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965833026 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1965833026
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.1703115817
Short name T84
Test name
Test status
Simulation time 10556283 ps
CPU time 0.77 seconds
Started Aug 23 09:52:10 AM UTC 24
Finished Aug 23 09:52:11 AM UTC 24
Peak memory 218164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703115817 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1703115817
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.610186997
Short name T176
Test name
Test status
Simulation time 189091283 ps
CPU time 17.3 seconds
Started Aug 23 09:52:12 AM UTC 24
Finished Aug 23 09:52:30 AM UTC 24
Peak memory 262576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610186997 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.610186997
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.2726628484
Short name T468
Test name
Test status
Simulation time 223589983 ps
CPU time 6.67 seconds
Started Aug 23 09:52:13 AM UTC 24
Finished Aug 23 09:52:21 AM UTC 24
Peak memory 262836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726628484 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2726628484
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.2641474279
Short name T156
Test name
Test status
Simulation time 35976647331 ps
CPU time 169.57 seconds
Started Aug 23 09:52:28 AM UTC 24
Finished Aug 23 09:55:20 AM UTC 24
Peak memory 283076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2641474279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 19.lc_ctrl_stress_all.2641474279
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3473737148
Short name T461
Test name
Test status
Simulation time 25218355 ps
CPU time 0.87 seconds
Started Aug 23 09:52:10 AM UTC 24
Finished Aug 23 09:52:11 AM UTC 24
Peak memory 218228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473737148 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19
.lc_ctrl_volatile_unlock_smoke.3473737148
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.1053951191
Short name T80
Test name
Test status
Simulation time 70005598 ps
CPU time 0.97 seconds
Started Aug 23 09:43:50 AM UTC 24
Finished Aug 23 09:43:52 AM UTC 24
Peak memory 218644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053951191 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1053951191
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.566872846
Short name T225
Test name
Test status
Simulation time 22261864 ps
CPU time 0.81 seconds
Started Aug 23 09:43:21 AM UTC 24
Finished Aug 23 09:43:23 AM UTC 24
Peak memory 218648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566872846 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.566872846
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.593743620
Short name T226
Test name
Test status
Simulation time 2160208610 ps
CPU time 11.14 seconds
Started Aug 23 09:43:17 AM UTC 24
Finished Aug 23 09:43:29 AM UTC 24
Peak memory 232396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593743620 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.593743620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.2871819267
Short name T11
Test name
Test status
Simulation time 183010470 ps
CPU time 2.64 seconds
Started Aug 23 09:43:28 AM UTC 24
Finished Aug 23 09:43:32 AM UTC 24
Peak memory 229864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871819267 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2871819267
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.42269936
Short name T96
Test name
Test status
Simulation time 3433365819 ps
CPU time 32.57 seconds
Started Aug 23 09:43:28 AM UTC 24
Finished Aug 23 09:44:02 AM UTC 24
Peak memory 237576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42269936 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_errors.42269936
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.258390008
Short name T77
Test name
Test status
Simulation time 2086687287 ps
CPU time 4.76 seconds
Started Aug 23 09:43:30 AM UTC 24
Finished Aug 23 09:43:36 AM UTC 24
Peak memory 229952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258390008 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.258390008
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.2243074404
Short name T227
Test name
Test status
Simulation time 601238092 ps
CPU time 5.72 seconds
Started Aug 23 09:43:26 AM UTC 24
Finished Aug 23 09:43:32 AM UTC 24
Peak memory 231808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243074404
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_jtag_prog_failure.2243074404
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1403031616
Short name T76
Test name
Test status
Simulation time 1161770168 ps
CPU time 27.5 seconds
Started Aug 23 09:43:31 AM UTC 24
Finished Aug 23 09:44:00 AM UTC 24
Peak memory 229488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403031616
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_
ctrl_jtag_regwen_during_op.1403031616
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.3692400899
Short name T75
Test name
Test status
Simulation time 128267603 ps
CPU time 2.45 seconds
Started Aug 23 09:43:22 AM UTC 24
Finished Aug 23 09:43:25 AM UTC 24
Peak memory 229820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692400899
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_s
moke.3692400899
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.229929939
Short name T229
Test name
Test status
Simulation time 5907470831 ps
CPU time 32.07 seconds
Started Aug 23 09:43:22 AM UTC 24
Finished Aug 23 09:43:55 AM UTC 24
Peak memory 264544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229929939 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_jtag_state_failure.229929939
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.531323201
Short name T221
Test name
Test status
Simulation time 2782547400 ps
CPU time 10.06 seconds
Started Aug 23 09:43:25 AM UTC 24
Finished Aug 23 09:43:36 AM UTC 24
Peak memory 234616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531323201 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_c
trl_jtag_state_post_trans.531323201
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.1141306610
Short name T224
Test name
Test status
Simulation time 88774122 ps
CPU time 2.07 seconds
Started Aug 23 09:43:17 AM UTC 24
Finished Aug 23 09:43:20 AM UTC 24
Peak memory 231872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141306610 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1141306610
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.3727771186
Short name T85
Test name
Test status
Simulation time 482833325 ps
CPU time 7.9 seconds
Started Aug 23 09:43:21 AM UTC 24
Finished Aug 23 09:43:31 AM UTC 24
Peak memory 229892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727771186 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3727771186
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.2282281582
Short name T97
Test name
Test status
Simulation time 836258264 ps
CPU time 31.33 seconds
Started Aug 23 09:43:50 AM UTC 24
Finished Aug 23 09:44:22 AM UTC 24
Peak memory 296184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282281582 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2282281582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.715910102
Short name T54
Test name
Test status
Simulation time 2164918615 ps
CPU time 14.04 seconds
Started Aug 23 09:43:32 AM UTC 24
Finished Aug 23 09:43:47 AM UTC 24
Peak memory 232336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715910102 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.715910102
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.4194239369
Short name T228
Test name
Test status
Simulation time 1180474693 ps
CPU time 11.86 seconds
Started Aug 23 09:43:36 AM UTC 24
Finished Aug 23 09:43:49 AM UTC 24
Peak memory 231748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194239369 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_tok
en_digest.4194239369
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.3387052783
Short name T48
Test name
Test status
Simulation time 1998148042 ps
CPU time 16.77 seconds
Started Aug 23 09:43:33 AM UTC 24
Finished Aug 23 09:43:51 AM UTC 24
Peak memory 231940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387052783 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_
mux.3387052783
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.3952349650
Short name T65
Test name
Test status
Simulation time 618186409 ps
CPU time 6.03 seconds
Started Aug 23 09:43:20 AM UTC 24
Finished Aug 23 09:43:27 AM UTC 24
Peak memory 232076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952349650 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3952349650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1003445884
Short name T223
Test name
Test status
Simulation time 15409566 ps
CPU time 1.06 seconds
Started Aug 23 09:43:04 AM UTC 24
Finished Aug 23 09:43:06 AM UTC 24
Peak memory 222312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003445884 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1003445884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.931966532
Short name T102
Test name
Test status
Simulation time 362902909 ps
CPU time 18.33 seconds
Started Aug 23 09:43:08 AM UTC 24
Finished Aug 23 09:43:27 AM UTC 24
Peak memory 262500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931966532 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.931966532
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.2111831097
Short name T220
Test name
Test status
Simulation time 198584534 ps
CPU time 6.07 seconds
Started Aug 23 09:43:09 AM UTC 24
Finished Aug 23 09:43:16 AM UTC 24
Peak memory 262840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111831097 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2111831097
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.3783819449
Short name T71
Test name
Test status
Simulation time 16454965955 ps
CPU time 467.65 seconds
Started Aug 23 09:43:36 AM UTC 24
Finished Aug 23 09:51:30 AM UTC 24
Peak memory 313716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3783819449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 2.lc_ctrl_stress_all.3783819449
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2043450112
Short name T99
Test name
Test status
Simulation time 10379849283 ps
CPU time 69.97 seconds
Started Aug 23 09:43:48 AM UTC 24
Finished Aug 23 09:45:00 AM UTC 24
Peak memory 254576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043450112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_u
nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.2043450112
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1481769026
Short name T38
Test name
Test status
Simulation time 12759336 ps
CPU time 0.75 seconds
Started Aug 23 09:43:07 AM UTC 24
Finished Aug 23 09:43:08 AM UTC 24
Peak memory 219272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481769026 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.
lc_ctrl_volatile_unlock_smoke.1481769026
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.2532641285
Short name T484
Test name
Test status
Simulation time 19829562 ps
CPU time 0.92 seconds
Started Aug 23 09:52:45 AM UTC 24
Finished Aug 23 09:52:46 AM UTC 24
Peak memory 218524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532641285 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2532641285
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_errors.1556390564
Short name T486
Test name
Test status
Simulation time 237086106 ps
CPU time 9.12 seconds
Started Aug 23 09:52:37 AM UTC 24
Finished Aug 23 09:52:47 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556390564 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1556390564
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.3266833696
Short name T483
Test name
Test status
Simulation time 336927836 ps
CPU time 2.3 seconds
Started Aug 23 09:52:41 AM UTC 24
Finished Aug 23 09:52:44 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266833696 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3266833696
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.3473455312
Short name T477
Test name
Test status
Simulation time 62407843 ps
CPU time 2 seconds
Started Aug 23 09:52:36 AM UTC 24
Finished Aug 23 09:52:39 AM UTC 24
Peak memory 229920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473455312 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3473455312
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.2995631092
Short name T489
Test name
Test status
Simulation time 307150073 ps
CPU time 8.08 seconds
Started Aug 23 09:52:41 AM UTC 24
Finished Aug 23 09:52:50 AM UTC 24
Peak memory 237576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995631092 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2995631092
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.3448710624
Short name T491
Test name
Test status
Simulation time 302469725 ps
CPU time 9.26 seconds
Started Aug 23 09:52:42 AM UTC 24
Finished Aug 23 09:52:53 AM UTC 24
Peak memory 232136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448710624 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_to
ken_digest.3448710624
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.1069537472
Short name T490
Test name
Test status
Simulation time 4569240562 ps
CPU time 8.29 seconds
Started Aug 23 09:52:41 AM UTC 24
Finished Aug 23 09:52:50 AM UTC 24
Peak memory 237712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069537472 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token
_mux.1069537472
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.1860680987
Short name T487
Test name
Test status
Simulation time 4922712370 ps
CPU time 9.26 seconds
Started Aug 23 09:52:38 AM UTC 24
Finished Aug 23 09:52:49 AM UTC 24
Peak memory 231936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860680987 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1860680987
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.1135982039
Short name T474
Test name
Test status
Simulation time 29879890 ps
CPU time 2.15 seconds
Started Aug 23 09:52:33 AM UTC 24
Finished Aug 23 09:52:36 AM UTC 24
Peak memory 225664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135982039 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1135982039
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.2390627255
Short name T494
Test name
Test status
Simulation time 536426755 ps
CPU time 21.22 seconds
Started Aug 23 09:52:34 AM UTC 24
Finished Aug 23 09:52:56 AM UTC 24
Peak memory 262832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390627255 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2390627255
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.3233887411
Short name T482
Test name
Test status
Simulation time 89780907 ps
CPU time 6.9 seconds
Started Aug 23 09:52:34 AM UTC 24
Finished Aug 23 09:52:42 AM UTC 24
Peak memory 262504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233887411 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3233887411
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.2086585247
Short name T612
Test name
Test status
Simulation time 28188819479 ps
CPU time 173.87 seconds
Started Aug 23 09:52:42 AM UTC 24
Finished Aug 23 09:55:39 AM UTC 24
Peak memory 237508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2086585247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 20.lc_ctrl_stress_all.2086585247
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.623551197
Short name T55
Test name
Test status
Simulation time 32223978 ps
CPU time 0.73 seconds
Started Aug 23 09:52:33 AM UTC 24
Finished Aug 23 09:52:35 AM UTC 24
Peak memory 218556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623551197 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.
lc_ctrl_volatile_unlock_smoke.623551197
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.444584676
Short name T497
Test name
Test status
Simulation time 48688002 ps
CPU time 0.89 seconds
Started Aug 23 09:53:00 AM UTC 24
Finished Aug 23 09:53:02 AM UTC 24
Peak memory 218584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444584676 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.444584676
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_errors.1499741952
Short name T50
Test name
Test status
Simulation time 188190872 ps
CPU time 6.96 seconds
Started Aug 23 09:52:51 AM UTC 24
Finished Aug 23 09:52:58 AM UTC 24
Peak memory 229900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499741952 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1499741952
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.3642141489
Short name T502
Test name
Test status
Simulation time 551958288 ps
CPU time 11.54 seconds
Started Aug 23 09:52:52 AM UTC 24
Finished Aug 23 09:53:04 AM UTC 24
Peak memory 229540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642141489 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3642141489
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.1686396816
Short name T492
Test name
Test status
Simulation time 62039047 ps
CPU time 1.76 seconds
Started Aug 23 09:52:51 AM UTC 24
Finished Aug 23 09:52:53 AM UTC 24
Peak memory 231968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686396816 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1686396816
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.987816410
Short name T505
Test name
Test status
Simulation time 411436948 ps
CPU time 11.84 seconds
Started Aug 23 09:52:53 AM UTC 24
Finished Aug 23 09:53:06 AM UTC 24
Peak memory 237584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987816410 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.987816410
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.2210482018
Short name T504
Test name
Test status
Simulation time 607660912 ps
CPU time 10.42 seconds
Started Aug 23 09:52:54 AM UTC 24
Finished Aug 23 09:53:06 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210482018 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_to
ken_digest.2210482018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.2780820487
Short name T498
Test name
Test status
Simulation time 1029767673 ps
CPU time 6.85 seconds
Started Aug 23 09:52:54 AM UTC 24
Finished Aug 23 09:53:03 AM UTC 24
Peak memory 237668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780820487 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token
_mux.2780820487
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.189167208
Short name T495
Test name
Test status
Simulation time 220057870 ps
CPU time 6.57 seconds
Started Aug 23 09:52:52 AM UTC 24
Finished Aug 23 09:52:59 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189167208 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.189167208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.1546585479
Short name T488
Test name
Test status
Simulation time 104987049 ps
CPU time 1.02 seconds
Started Aug 23 09:52:48 AM UTC 24
Finished Aug 23 09:52:50 AM UTC 24
Peak memory 228440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546585479 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1546585479
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.1115479265
Short name T508
Test name
Test status
Simulation time 163765170 ps
CPU time 18.33 seconds
Started Aug 23 09:52:49 AM UTC 24
Finished Aug 23 09:53:09 AM UTC 24
Peak memory 262704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115479265 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1115479265
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.3894694825
Short name T493
Test name
Test status
Simulation time 136896582 ps
CPU time 3.2 seconds
Started Aug 23 09:52:49 AM UTC 24
Finished Aug 23 09:52:53 AM UTC 24
Peak memory 234260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894694825 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3894694825
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.125849489
Short name T628
Test name
Test status
Simulation time 5917635409 ps
CPU time 177.61 seconds
Started Aug 23 09:52:58 AM UTC 24
Finished Aug 23 09:55:58 AM UTC 24
Peak memory 328252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=125849489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 21.lc_ctrl_stress_all.125849489
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.520503758
Short name T56
Test name
Test status
Simulation time 40377171 ps
CPU time 0.69 seconds
Started Aug 23 09:52:49 AM UTC 24
Finished Aug 23 09:52:51 AM UTC 24
Peak memory 218228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520503758 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.
lc_ctrl_volatile_unlock_smoke.520503758
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.1058580991
Short name T510
Test name
Test status
Simulation time 22171528 ps
CPU time 0.97 seconds
Started Aug 23 09:53:09 AM UTC 24
Finished Aug 23 09:53:11 AM UTC 24
Peak memory 218512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058580991 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1058580991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_errors.2810361057
Short name T51
Test name
Test status
Simulation time 1336843341 ps
CPU time 12.46 seconds
Started Aug 23 09:53:05 AM UTC 24
Finished Aug 23 09:53:18 AM UTC 24
Peak memory 231948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810361057 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2810361057
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.1398632726
Short name T511
Test name
Test status
Simulation time 486987035 ps
CPU time 5.52 seconds
Started Aug 23 09:53:06 AM UTC 24
Finished Aug 23 09:53:13 AM UTC 24
Peak memory 229376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398632726 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1398632726
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.3620189061
Short name T507
Test name
Test status
Simulation time 20853044 ps
CPU time 1.45 seconds
Started Aug 23 09:53:05 AM UTC 24
Finished Aug 23 09:53:07 AM UTC 24
Peak memory 229920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620189061 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3620189061
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.2566613562
Short name T515
Test name
Test status
Simulation time 1044190193 ps
CPU time 8.15 seconds
Started Aug 23 09:53:07 AM UTC 24
Finished Aug 23 09:53:16 AM UTC 24
Peak memory 231868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566613562 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2566613562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.2938288801
Short name T518
Test name
Test status
Simulation time 592784959 ps
CPU time 11.9 seconds
Started Aug 23 09:53:08 AM UTC 24
Finished Aug 23 09:53:21 AM UTC 24
Peak memory 232204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938288801 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_to
ken_digest.2938288801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.3281990158
Short name T516
Test name
Test status
Simulation time 640893563 ps
CPU time 8.93 seconds
Started Aug 23 09:53:07 AM UTC 24
Finished Aug 23 09:53:17 AM UTC 24
Peak memory 232212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281990158 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token
_mux.3281990158
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.269584040
Short name T512
Test name
Test status
Simulation time 341297071 ps
CPU time 7.43 seconds
Started Aug 23 09:53:06 AM UTC 24
Finished Aug 23 09:53:15 AM UTC 24
Peak memory 231684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269584040 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.269584040
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.218141376
Short name T501
Test name
Test status
Simulation time 48618717 ps
CPU time 2.16 seconds
Started Aug 23 09:53:01 AM UTC 24
Finished Aug 23 09:53:04 AM UTC 24
Peak memory 225624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218141376 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.218141376
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.170780563
Short name T524
Test name
Test status
Simulation time 461314346 ps
CPU time 23.27 seconds
Started Aug 23 09:53:05 AM UTC 24
Finished Aug 23 09:53:29 AM UTC 24
Peak memory 262416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170780563 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.170780563
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.2270665862
Short name T509
Test name
Test status
Simulation time 164256666 ps
CPU time 3.04 seconds
Started Aug 23 09:53:05 AM UTC 24
Finished Aug 23 09:53:09 AM UTC 24
Peak memory 234260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270665862 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2270665862
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.2851277557
Short name T553
Test name
Test status
Simulation time 6105793361 ps
CPU time 72.71 seconds
Started Aug 23 09:53:08 AM UTC 24
Finished Aug 23 09:54:22 AM UTC 24
Peak memory 262888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2851277557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 22.lc_ctrl_stress_all.2851277557
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.3988332036
Short name T571
Test name
Test status
Simulation time 6391227258 ps
CPU time 89.12 seconds
Started Aug 23 09:53:09 AM UTC 24
Finished Aug 23 09:54:40 AM UTC 24
Peak memory 272720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988332036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_u
nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.3988332036
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2577740187
Short name T500
Test name
Test status
Simulation time 36623392 ps
CPU time 0.75 seconds
Started Aug 23 09:53:02 AM UTC 24
Finished Aug 23 09:53:04 AM UTC 24
Peak memory 218228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577740187 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22
.lc_ctrl_volatile_unlock_smoke.2577740187
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.3534788660
Short name T525
Test name
Test status
Simulation time 26154500 ps
CPU time 1.11 seconds
Started Aug 23 09:53:28 AM UTC 24
Finished Aug 23 09:53:30 AM UTC 24
Peak memory 219084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534788660 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3534788660
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.285580771
Short name T521
Test name
Test status
Simulation time 1388310425 ps
CPU time 8.45 seconds
Started Aug 23 09:53:17 AM UTC 24
Finished Aug 23 09:53:27 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285580771 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.285580771
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.2678423909
Short name T520
Test name
Test status
Simulation time 486393515 ps
CPU time 5.8 seconds
Started Aug 23 09:53:20 AM UTC 24
Finished Aug 23 09:53:26 AM UTC 24
Peak memory 229616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678423909 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2678423909
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.174691429
Short name T517
Test name
Test status
Simulation time 91847078 ps
CPU time 1.51 seconds
Started Aug 23 09:53:16 AM UTC 24
Finished Aug 23 09:53:18 AM UTC 24
Peak memory 227936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174691429 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.174691429
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.2873341784
Short name T161
Test name
Test status
Simulation time 792975984 ps
CPU time 16.46 seconds
Started Aug 23 09:53:20 AM UTC 24
Finished Aug 23 09:53:37 AM UTC 24
Peak memory 237588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873341784 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2873341784
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.2748958321
Short name T160
Test name
Test status
Simulation time 436604862 ps
CPU time 12.91 seconds
Started Aug 23 09:53:22 AM UTC 24
Finished Aug 23 09:53:36 AM UTC 24
Peak memory 237596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748958321 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_to
ken_digest.2748958321
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.3478242082
Short name T523
Test name
Test status
Simulation time 498130990 ps
CPU time 6.98 seconds
Started Aug 23 09:53:21 AM UTC 24
Finished Aug 23 09:53:29 AM UTC 24
Peak memory 231888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478242082 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token
_mux.3478242082
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.1878811181
Short name T522
Test name
Test status
Simulation time 2808177980 ps
CPU time 9.23 seconds
Started Aug 23 09:53:17 AM UTC 24
Finished Aug 23 09:53:28 AM UTC 24
Peak memory 232008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878811181 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1878811181
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.1294322104
Short name T513
Test name
Test status
Simulation time 38946343 ps
CPU time 1.59 seconds
Started Aug 23 09:53:12 AM UTC 24
Finished Aug 23 09:53:15 AM UTC 24
Peak memory 224360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294322104 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1294322104
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.2224834093
Short name T164
Test name
Test status
Simulation time 1156004526 ps
CPU time 23.61 seconds
Started Aug 23 09:53:16 AM UTC 24
Finished Aug 23 09:53:41 AM UTC 24
Peak memory 262832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224834093 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2224834093
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.3885373623
Short name T519
Test name
Test status
Simulation time 145085235 ps
CPU time 5.75 seconds
Started Aug 23 09:53:16 AM UTC 24
Finished Aug 23 09:53:23 AM UTC 24
Peak memory 262580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885373623 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3885373623
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.3543833897
Short name T639
Test name
Test status
Simulation time 68537659899 ps
CPU time 159.79 seconds
Started Aug 23 09:53:23 AM UTC 24
Finished Aug 23 09:56:05 AM UTC 24
Peak memory 252320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3543833897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 23.lc_ctrl_stress_all.3543833897
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.586684609
Short name T514
Test name
Test status
Simulation time 54638647 ps
CPU time 0.69 seconds
Started Aug 23 09:53:14 AM UTC 24
Finished Aug 23 09:53:15 AM UTC 24
Peak memory 218228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586684609 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.
lc_ctrl_volatile_unlock_smoke.586684609
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.4141414106
Short name T165
Test name
Test status
Simulation time 143216308 ps
CPU time 0.83 seconds
Started Aug 23 09:53:40 AM UTC 24
Finished Aug 23 09:53:42 AM UTC 24
Peak memory 218644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141414106 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.4141414106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.1600858326
Short name T166
Test name
Test status
Simulation time 1756065334 ps
CPU time 9.15 seconds
Started Aug 23 09:53:33 AM UTC 24
Finished Aug 23 09:53:43 AM UTC 24
Peak memory 237512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600858326 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1600858326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.2864636297
Short name T162
Test name
Test status
Simulation time 527305556 ps
CPU time 2.99 seconds
Started Aug 23 09:53:34 AM UTC 24
Finished Aug 23 09:53:38 AM UTC 24
Peak memory 229900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864636297 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2864636297
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.2200063389
Short name T159
Test name
Test status
Simulation time 118754505 ps
CPU time 1.81 seconds
Started Aug 23 09:53:33 AM UTC 24
Finished Aug 23 09:53:35 AM UTC 24
Peak memory 233880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200063389 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2200063389
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.1857038105
Short name T535
Test name
Test status
Simulation time 1178569151 ps
CPU time 19.54 seconds
Started Aug 23 09:53:35 AM UTC 24
Finished Aug 23 09:53:56 AM UTC 24
Peak memory 231868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857038105 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1857038105
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.3187378038
Short name T536
Test name
Test status
Simulation time 824356882 ps
CPU time 18.05 seconds
Started Aug 23 09:53:37 AM UTC 24
Finished Aug 23 09:53:56 AM UTC 24
Peak memory 232072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187378038 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_to
ken_digest.3187378038
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.3191223566
Short name T531
Test name
Test status
Simulation time 1557865550 ps
CPU time 9.86 seconds
Started Aug 23 09:53:36 AM UTC 24
Finished Aug 23 09:53:47 AM UTC 24
Peak memory 231936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191223566 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token
_mux.3191223566
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.1661401325
Short name T167
Test name
Test status
Simulation time 295613132 ps
CPU time 9.12 seconds
Started Aug 23 09:53:33 AM UTC 24
Finished Aug 23 09:53:43 AM UTC 24
Peak memory 237660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661401325 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1661401325
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.1306578668
Short name T526
Test name
Test status
Simulation time 112105025 ps
CPU time 1.72 seconds
Started Aug 23 09:53:29 AM UTC 24
Finished Aug 23 09:53:31 AM UTC 24
Peak memory 224364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306578668 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1306578668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.2383574946
Short name T538
Test name
Test status
Simulation time 249198794 ps
CPU time 26.84 seconds
Started Aug 23 09:53:30 AM UTC 24
Finished Aug 23 09:53:58 AM UTC 24
Peak memory 262500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383574946 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2383574946
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.1822763640
Short name T163
Test name
Test status
Simulation time 271683775 ps
CPU time 8.11 seconds
Started Aug 23 09:53:30 AM UTC 24
Finished Aug 23 09:53:39 AM UTC 24
Peak memory 262504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822763640 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1822763640
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.1515236846
Short name T866
Test name
Test status
Simulation time 120461842294 ps
CPU time 563.81 seconds
Started Aug 23 09:53:39 AM UTC 24
Finished Aug 23 10:03:09 AM UTC 24
Peak memory 272580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1515236846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 24.lc_ctrl_stress_all.1515236846
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3091467782
Short name T144
Test name
Test status
Simulation time 1729685401 ps
CPU time 32.88 seconds
Started Aug 23 09:53:39 AM UTC 24
Finished Aug 23 09:54:13 AM UTC 24
Peak memory 248812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091467782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_u
nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3091467782
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2825426303
Short name T528
Test name
Test status
Simulation time 51926008 ps
CPU time 0.91 seconds
Started Aug 23 09:53:30 AM UTC 24
Finished Aug 23 09:53:32 AM UTC 24
Peak memory 228524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825426303 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24
.lc_ctrl_volatile_unlock_smoke.2825426303
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.271030555
Short name T485
Test name
Test status
Simulation time 14114039 ps
CPU time 0.95 seconds
Started Aug 23 09:53:59 AM UTC 24
Finished Aug 23 09:54:01 AM UTC 24
Peak memory 218760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271030555 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.271030555
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_errors.894534038
Short name T537
Test name
Test status
Simulation time 288928304 ps
CPU time 9.91 seconds
Started Aug 23 09:53:47 AM UTC 24
Finished Aug 23 09:53:58 AM UTC 24
Peak memory 231992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894534038 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.894534038
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.1176337136
Short name T533
Test name
Test status
Simulation time 276514228 ps
CPU time 2.08 seconds
Started Aug 23 09:53:48 AM UTC 24
Finished Aug 23 09:53:51 AM UTC 24
Peak memory 229668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176337136 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1176337136
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.4122445805
Short name T532
Test name
Test status
Simulation time 84760923 ps
CPU time 1.41 seconds
Started Aug 23 09:53:45 AM UTC 24
Finished Aug 23 09:53:47 AM UTC 24
Peak memory 227876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122445805 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.4122445805
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.2854006047
Short name T545
Test name
Test status
Simulation time 1087010800 ps
CPU time 17.24 seconds
Started Aug 23 09:53:52 AM UTC 24
Finished Aug 23 09:54:11 AM UTC 24
Peak memory 237580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854006047 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2854006047
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.2002056643
Short name T543
Test name
Test status
Simulation time 219422007 ps
CPU time 7.95 seconds
Started Aug 23 09:53:57 AM UTC 24
Finished Aug 23 09:54:06 AM UTC 24
Peak memory 232008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002056643 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_to
ken_digest.2002056643
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.749617967
Short name T541
Test name
Test status
Simulation time 660819162 ps
CPU time 10.22 seconds
Started Aug 23 09:53:52 AM UTC 24
Finished Aug 23 09:54:04 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749617967 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_
mux.749617967
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.55114594
Short name T539
Test name
Test status
Simulation time 378136319 ps
CPU time 9.28 seconds
Started Aug 23 09:53:48 AM UTC 24
Finished Aug 23 09:53:58 AM UTC 24
Peak memory 232208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55114594 -assert nopostproc +UVM_TESTNAME=lc_ctr
l_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.55114594
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.2640631873
Short name T530
Test name
Test status
Simulation time 38850517 ps
CPU time 2.45 seconds
Started Aug 23 09:53:42 AM UTC 24
Finished Aug 23 09:53:46 AM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640631873 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2640631873
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.3459406878
Short name T547
Test name
Test status
Simulation time 291195651 ps
CPU time 27.29 seconds
Started Aug 23 09:53:43 AM UTC 24
Finished Aug 23 09:54:12 AM UTC 24
Peak memory 262576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459406878 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3459406878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.3954789662
Short name T534
Test name
Test status
Simulation time 455601978 ps
CPU time 6.67 seconds
Started Aug 23 09:53:44 AM UTC 24
Finished Aug 23 09:53:51 AM UTC 24
Peak memory 262576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954789662 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3954789662
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.104810409
Short name T106
Test name
Test status
Simulation time 5335270756 ps
CPU time 75.77 seconds
Started Aug 23 09:53:58 AM UTC 24
Finished Aug 23 09:55:16 AM UTC 24
Peak memory 289180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=104810409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 25.lc_ctrl_stress_all.104810409
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.3656494421
Short name T145
Test name
Test status
Simulation time 4165519050 ps
CPU time 14.48 seconds
Started Aug 23 09:53:59 AM UTC 24
Finished Aug 23 09:54:15 AM UTC 24
Peak memory 237796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656494421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_u
nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.3656494421
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2015998009
Short name T529
Test name
Test status
Simulation time 14907853 ps
CPU time 0.69 seconds
Started Aug 23 09:53:42 AM UTC 24
Finished Aug 23 09:53:44 AM UTC 24
Peak memory 218524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015998009 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25
.lc_ctrl_volatile_unlock_smoke.2015998009
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.3026734144
Short name T551
Test name
Test status
Simulation time 84775091 ps
CPU time 0.79 seconds
Started Aug 23 09:54:20 AM UTC 24
Finished Aug 23 09:54:21 AM UTC 24
Peak memory 218880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026734144 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3026734144
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_errors.1824957071
Short name T549
Test name
Test status
Simulation time 382941971 ps
CPU time 11.77 seconds
Started Aug 23 09:54:06 AM UTC 24
Finished Aug 23 09:54:19 AM UTC 24
Peak memory 231384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824957071 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1824957071
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.3199390895
Short name T548
Test name
Test status
Simulation time 59960118 ps
CPU time 1.23 seconds
Started Aug 23 09:54:12 AM UTC 24
Finished Aug 23 09:54:14 AM UTC 24
Peak memory 227984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199390895 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3199390895
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.1016801833
Short name T544
Test name
Test status
Simulation time 35440850 ps
CPU time 1.75 seconds
Started Aug 23 09:54:06 AM UTC 24
Finished Aug 23 09:54:09 AM UTC 24
Peak memory 229464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016801833 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1016801833
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.540482143
Short name T559
Test name
Test status
Simulation time 1048024867 ps
CPU time 12.45 seconds
Started Aug 23 09:54:13 AM UTC 24
Finished Aug 23 09:54:26 AM UTC 24
Peak memory 237120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540482143 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.540482143
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.2870196490
Short name T557
Test name
Test status
Simulation time 424632393 ps
CPU time 10.15 seconds
Started Aug 23 09:54:14 AM UTC 24
Finished Aug 23 09:54:26 AM UTC 24
Peak memory 237520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870196490 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_to
ken_digest.2870196490
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.1110548419
Short name T552
Test name
Test status
Simulation time 391256482 ps
CPU time 7.64 seconds
Started Aug 23 09:54:13 AM UTC 24
Finished Aug 23 09:54:22 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110548419 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token
_mux.1110548419
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.318231011
Short name T550
Test name
Test status
Simulation time 982186001 ps
CPU time 8.73 seconds
Started Aug 23 09:54:09 AM UTC 24
Finished Aug 23 09:54:19 AM UTC 24
Peak memory 231960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318231011 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.318231011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.2266738818
Short name T540
Test name
Test status
Simulation time 43558817 ps
CPU time 2.37 seconds
Started Aug 23 09:53:59 AM UTC 24
Finished Aug 23 09:54:03 AM UTC 24
Peak memory 229884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266738818 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2266738818
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.3445580867
Short name T558
Test name
Test status
Simulation time 1515751055 ps
CPU time 20.56 seconds
Started Aug 23 09:54:04 AM UTC 24
Finished Aug 23 09:54:26 AM UTC 24
Peak memory 262504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445580867 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3445580867
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.3253182742
Short name T546
Test name
Test status
Simulation time 260136944 ps
CPU time 5.42 seconds
Started Aug 23 09:54:05 AM UTC 24
Finished Aug 23 09:54:12 AM UTC 24
Peak memory 260444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253182742 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3253182742
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.2651184419
Short name T611
Test name
Test status
Simulation time 24534250584 ps
CPU time 82.25 seconds
Started Aug 23 09:54:14 AM UTC 24
Finished Aug 23 09:55:38 AM UTC 24
Peak memory 263020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2651184419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 26.lc_ctrl_stress_all.2651184419
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.865537614
Short name T158
Test name
Test status
Simulation time 6754557788 ps
CPU time 184.91 seconds
Started Aug 23 09:54:15 AM UTC 24
Finished Aug 23 09:57:23 AM UTC 24
Peak memory 281224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865537614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S
EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_un
lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.865537614
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1962087205
Short name T542
Test name
Test status
Simulation time 29371242 ps
CPU time 0.84 seconds
Started Aug 23 09:54:03 AM UTC 24
Finished Aug 23 09:54:05 AM UTC 24
Peak memory 222376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962087205 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26
.lc_ctrl_volatile_unlock_smoke.1962087205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.1603763641
Short name T566
Test name
Test status
Simulation time 41853753 ps
CPU time 0.71 seconds
Started Aug 23 09:54:34 AM UTC 24
Finished Aug 23 09:54:36 AM UTC 24
Peak memory 217372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603763641 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1603763641
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_errors.2480607769
Short name T563
Test name
Test status
Simulation time 218021841 ps
CPU time 6.9 seconds
Started Aug 23 09:54:25 AM UTC 24
Finished Aug 23 09:54:33 AM UTC 24
Peak memory 229828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480607769 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2480607769
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.1754008661
Short name T562
Test name
Test status
Simulation time 264124562 ps
CPU time 2.08 seconds
Started Aug 23 09:54:27 AM UTC 24
Finished Aug 23 09:54:30 AM UTC 24
Peak memory 229612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754008661 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1754008661
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.3512338499
Short name T561
Test name
Test status
Simulation time 389803996 ps
CPU time 3.06 seconds
Started Aug 23 09:54:25 AM UTC 24
Finished Aug 23 09:54:29 AM UTC 24
Peak memory 236300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512338499 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3512338499
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.3713852781
Short name T570
Test name
Test status
Simulation time 407899928 ps
CPU time 11.93 seconds
Started Aug 23 09:54:27 AM UTC 24
Finished Aug 23 09:54:40 AM UTC 24
Peak memory 237576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713852781 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3713852781
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.1438152322
Short name T569
Test name
Test status
Simulation time 787518719 ps
CPU time 9.67 seconds
Started Aug 23 09:54:29 AM UTC 24
Finished Aug 23 09:54:40 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438152322 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_to
ken_digest.1438152322
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.2857387739
Short name T572
Test name
Test status
Simulation time 496724244 ps
CPU time 14.35 seconds
Started Aug 23 09:54:27 AM UTC 24
Finished Aug 23 09:54:43 AM UTC 24
Peak memory 237608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857387739 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token
_mux.2857387739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.2566178586
Short name T565
Test name
Test status
Simulation time 1138767034 ps
CPU time 6.86 seconds
Started Aug 23 09:54:26 AM UTC 24
Finished Aug 23 09:54:34 AM UTC 24
Peak memory 231944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566178586 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2566178586
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.3667712861
Short name T554
Test name
Test status
Simulation time 215238354 ps
CPU time 1.64 seconds
Started Aug 23 09:54:21 AM UTC 24
Finished Aug 23 09:54:24 AM UTC 24
Peak memory 224360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667712861 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3667712861
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.1091041207
Short name T576
Test name
Test status
Simulation time 294045401 ps
CPU time 27.48 seconds
Started Aug 23 09:54:22 AM UTC 24
Finished Aug 23 09:54:51 AM UTC 24
Peak memory 260784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091041207 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1091041207
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.282507236
Short name T564
Test name
Test status
Simulation time 142427291 ps
CPU time 8.49 seconds
Started Aug 23 09:54:23 AM UTC 24
Finished Aug 23 09:54:33 AM UTC 24
Peak memory 262564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282507236 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.282507236
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.3916038094
Short name T591
Test name
Test status
Simulation time 1228035910 ps
CPU time 39.79 seconds
Started Aug 23 09:54:32 AM UTC 24
Finished Aug 23 09:55:13 AM UTC 24
Peak memory 262832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3916038094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 27.lc_ctrl_stress_all.3916038094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2241869011
Short name T555
Test name
Test status
Simulation time 36952914 ps
CPU time 0.82 seconds
Started Aug 23 09:54:22 AM UTC 24
Finished Aug 23 09:54:24 AM UTC 24
Peak memory 222376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241869011 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27
.lc_ctrl_volatile_unlock_smoke.2241869011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.1339360551
Short name T580
Test name
Test status
Simulation time 16031468 ps
CPU time 1.01 seconds
Started Aug 23 09:54:54 AM UTC 24
Finished Aug 23 09:54:55 AM UTC 24
Peak memory 218524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339360551 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1339360551
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_errors.1070995205
Short name T581
Test name
Test status
Simulation time 1226776704 ps
CPU time 12.69 seconds
Started Aug 23 09:54:42 AM UTC 24
Finished Aug 23 09:54:56 AM UTC 24
Peak memory 232204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070995205 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1070995205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.2446186547
Short name T577
Test name
Test status
Simulation time 646741229 ps
CPU time 7.9 seconds
Started Aug 23 09:54:43 AM UTC 24
Finished Aug 23 09:54:52 AM UTC 24
Peak memory 229528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446186547 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2446186547
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.1093398343
Short name T575
Test name
Test status
Simulation time 340816391 ps
CPU time 2.91 seconds
Started Aug 23 09:54:42 AM UTC 24
Finished Aug 23 09:54:46 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093398343 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1093398343
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.1341175019
Short name T586
Test name
Test status
Simulation time 1458159709 ps
CPU time 14.17 seconds
Started Aug 23 09:54:46 AM UTC 24
Finished Aug 23 09:55:01 AM UTC 24
Peak memory 237580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341175019 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1341175019
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.2338519059
Short name T583
Test name
Test status
Simulation time 289224121 ps
CPU time 10.48 seconds
Started Aug 23 09:54:47 AM UTC 24
Finished Aug 23 09:54:58 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338519059 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_to
ken_digest.2338519059
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.1398534966
Short name T579
Test name
Test status
Simulation time 1786284397 ps
CPU time 7.44 seconds
Started Aug 23 09:54:46 AM UTC 24
Finished Aug 23 09:54:54 AM UTC 24
Peak memory 232212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398534966 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token
_mux.1398534966
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.1351953012
Short name T578
Test name
Test status
Simulation time 1565118645 ps
CPU time 9.55 seconds
Started Aug 23 09:54:42 AM UTC 24
Finished Aug 23 09:54:53 AM UTC 24
Peak memory 237404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351953012 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1351953012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.327745917
Short name T568
Test name
Test status
Simulation time 46530197 ps
CPU time 2.8 seconds
Started Aug 23 09:54:35 AM UTC 24
Finished Aug 23 09:54:39 AM UTC 24
Peak memory 225468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327745917 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.327745917
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.2054122338
Short name T585
Test name
Test status
Simulation time 244654246 ps
CPU time 20.26 seconds
Started Aug 23 09:54:39 AM UTC 24
Finished Aug 23 09:55:01 AM UTC 24
Peak memory 258740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054122338 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2054122338
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.738601761
Short name T574
Test name
Test status
Simulation time 86843309 ps
CPU time 3.47 seconds
Started Aug 23 09:54:41 AM UTC 24
Finished Aug 23 09:54:45 AM UTC 24
Peak memory 236308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738601761 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.738601761
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.3752164555
Short name T705
Test name
Test status
Simulation time 29623978638 ps
CPU time 155.44 seconds
Started Aug 23 09:54:52 AM UTC 24
Finished Aug 23 09:57:30 AM UTC 24
Peak memory 266796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3752164555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 28.lc_ctrl_stress_all.3752164555
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3003944700
Short name T567
Test name
Test status
Simulation time 44839591 ps
CPU time 0.78 seconds
Started Aug 23 09:54:36 AM UTC 24
Finished Aug 23 09:54:38 AM UTC 24
Peak memory 220328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003944700 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28
.lc_ctrl_volatile_unlock_smoke.3003944700
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.2758900331
Short name T594
Test name
Test status
Simulation time 129828251 ps
CPU time 1.1 seconds
Started Aug 23 09:55:14 AM UTC 24
Finished Aug 23 09:55:16 AM UTC 24
Peak memory 218524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758900331 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2758900331
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_errors.1914327203
Short name T590
Test name
Test status
Simulation time 736541004 ps
CPU time 9.69 seconds
Started Aug 23 09:55:02 AM UTC 24
Finished Aug 23 09:55:13 AM UTC 24
Peak memory 237596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914327203 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1914327203
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.771268564
Short name T592
Test name
Test status
Simulation time 944099799 ps
CPU time 11.48 seconds
Started Aug 23 09:55:02 AM UTC 24
Finished Aug 23 09:55:14 AM UTC 24
Peak memory 229556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771268564 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.771268564
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.3855878719
Short name T587
Test name
Test status
Simulation time 38180700 ps
CPU time 2.13 seconds
Started Aug 23 09:54:59 AM UTC 24
Finished Aug 23 09:55:02 AM UTC 24
Peak memory 233924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855878719 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3855878719
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.882908529
Short name T593
Test name
Test status
Simulation time 1312850284 ps
CPU time 11.48 seconds
Started Aug 23 09:55:03 AM UTC 24
Finished Aug 23 09:55:16 AM UTC 24
Peak memory 237580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882908529 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.882908529
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.2903330924
Short name T601
Test name
Test status
Simulation time 1482687635 ps
CPU time 12.97 seconds
Started Aug 23 09:55:08 AM UTC 24
Finished Aug 23 09:55:23 AM UTC 24
Peak memory 237592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903330924 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_to
ken_digest.2903330924
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.2405956761
Short name T595
Test name
Test status
Simulation time 3736585017 ps
CPU time 8.7 seconds
Started Aug 23 09:55:07 AM UTC 24
Finished Aug 23 09:55:17 AM UTC 24
Peak memory 231940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405956761 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token
_mux.2405956761
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.3042250982
Short name T589
Test name
Test status
Simulation time 1081933446 ps
CPU time 8.2 seconds
Started Aug 23 09:55:02 AM UTC 24
Finished Aug 23 09:55:11 AM UTC 24
Peak memory 231872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042250982 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3042250982
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.1434613185
Short name T584
Test name
Test status
Simulation time 141843715 ps
CPU time 3.4 seconds
Started Aug 23 09:54:56 AM UTC 24
Finished Aug 23 09:55:00 AM UTC 24
Peak memory 229220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434613185 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1434613185
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.771332585
Short name T597
Test name
Test status
Simulation time 452244188 ps
CPU time 20.35 seconds
Started Aug 23 09:54:57 AM UTC 24
Finished Aug 23 09:55:18 AM UTC 24
Peak memory 258416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771332585 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.771332585
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.1612802317
Short name T588
Test name
Test status
Simulation time 302647863 ps
CPU time 7.64 seconds
Started Aug 23 09:54:58 AM UTC 24
Finished Aug 23 09:55:07 AM UTC 24
Peak memory 262576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612802317 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1612802317
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.2516847213
Short name T107
Test name
Test status
Simulation time 30988849366 ps
CPU time 75.74 seconds
Started Aug 23 09:55:12 AM UTC 24
Finished Aug 23 09:56:29 AM UTC 24
Peak memory 418204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2516847213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 29.lc_ctrl_stress_all.2516847213
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.83934393
Short name T573
Test name
Test status
Simulation time 731503353 ps
CPU time 29.89 seconds
Started Aug 23 09:55:14 AM UTC 24
Finished Aug 23 09:55:45 AM UTC 24
Peak memory 262700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83934393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SE
Q=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unl
ock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.83934393
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1646369295
Short name T582
Test name
Test status
Simulation time 21857466 ps
CPU time 0.69 seconds
Started Aug 23 09:54:56 AM UTC 24
Finished Aug 23 09:54:57 AM UTC 24
Peak memory 218196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646369295 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29
.lc_ctrl_volatile_unlock_smoke.1646369295
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.1584380068
Short name T238
Test name
Test status
Simulation time 28057989 ps
CPU time 0.88 seconds
Started Aug 23 09:44:43 AM UTC 24
Finished Aug 23 09:44:45 AM UTC 24
Peak memory 218760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584380068 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1584380068
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1781670833
Short name T52
Test name
Test status
Simulation time 446349119 ps
CPU time 10.42 seconds
Started Aug 23 09:44:00 AM UTC 24
Finished Aug 23 09:44:12 AM UTC 24
Peak memory 231044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781670833 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1781670833
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.3896631286
Short name T26
Test name
Test status
Simulation time 6568532237 ps
CPU time 16.03 seconds
Started Aug 23 09:44:19 AM UTC 24
Finished Aug 23 09:44:36 AM UTC 24
Peak memory 229636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896631286 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3896631286
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.3162603206
Short name T149
Test name
Test status
Simulation time 4153812123 ps
CPU time 49.81 seconds
Started Aug 23 09:44:17 AM UTC 24
Finished Aug 23 09:45:08 AM UTC 24
Peak memory 237580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162603206
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jt
ag_errors.3162603206
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2169863154
Short name T210
Test name
Test status
Simulation time 6550267880 ps
CPU time 33.55 seconds
Started Aug 23 09:44:23 AM UTC 24
Finished Aug 23 09:44:58 AM UTC 24
Peak memory 230004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169863154 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_prior
ity.2169863154
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.1645720962
Short name T234
Test name
Test status
Simulation time 656771053 ps
CPU time 9.52 seconds
Started Aug 23 09:44:13 AM UTC 24
Finished Aug 23 09:44:24 AM UTC 24
Peak memory 235904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645720962
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_jtag_prog_failure.1645720962
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1553982706
Short name T237
Test name
Test status
Simulation time 1081881714 ps
CPU time 15.08 seconds
Started Aug 23 09:44:25 AM UTC 24
Finished Aug 23 09:44:41 AM UTC 24
Peak memory 229568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553982706
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_
ctrl_jtag_regwen_during_op.1553982706
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.2858443430
Short name T232
Test name
Test status
Simulation time 3926005389 ps
CPU time 8.84 seconds
Started Aug 23 09:44:05 AM UTC 24
Finished Aug 23 09:44:16 AM UTC 24
Peak memory 229544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858443430
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_s
moke.2858443430
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.1740837701
Short name T240
Test name
Test status
Simulation time 5714158532 ps
CPU time 36.96 seconds
Started Aug 23 09:44:10 AM UTC 24
Finished Aug 23 09:44:48 AM UTC 24
Peak memory 262508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740837701
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr
l_jtag_state_failure.1740837701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.993890266
Short name T235
Test name
Test status
Simulation time 1932375457 ps
CPU time 18.04 seconds
Started Aug 23 09:44:12 AM UTC 24
Finished Aug 23 09:44:31 AM UTC 24
Peak memory 260744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993890266 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_c
trl_jtag_state_post_trans.993890266
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1355176854
Short name T230
Test name
Test status
Simulation time 644979654 ps
CPU time 2.09 seconds
Started Aug 23 09:43:56 AM UTC 24
Finished Aug 23 09:43:59 AM UTC 24
Peak memory 231948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355176854 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1355176854
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.1830042126
Short name T187
Test name
Test status
Simulation time 1262266096 ps
CPU time 7.53 seconds
Started Aug 23 09:44:02 AM UTC 24
Finished Aug 23 09:44:11 AM UTC 24
Peak memory 225920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830042126 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1830042126
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.1159186507
Short name T68
Test name
Test status
Simulation time 190741388 ps
CPU time 20.36 seconds
Started Aug 23 09:44:42 AM UTC 24
Finished Aug 23 09:45:03 AM UTC 24
Peak memory 290036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159186507 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1159186507
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.1819340605
Short name T222
Test name
Test status
Simulation time 603707837 ps
CPU time 13.03 seconds
Started Aug 23 09:44:27 AM UTC 24
Finished Aug 23 09:44:41 AM UTC 24
Peak memory 231944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819340605 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1819340605
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.1489292372
Short name T239
Test name
Test status
Simulation time 424790733 ps
CPU time 12.95 seconds
Started Aug 23 09:44:32 AM UTC 24
Finished Aug 23 09:44:47 AM UTC 24
Peak memory 232132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489292372 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_tok
en_digest.1489292372
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.3387731069
Short name T236
Test name
Test status
Simulation time 246357113 ps
CPU time 7.68 seconds
Started Aug 23 09:44:28 AM UTC 24
Finished Aug 23 09:44:37 AM UTC 24
Peak memory 231868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387731069 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_
mux.3387731069
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.3695675514
Short name T66
Test name
Test status
Simulation time 363488308 ps
CPU time 7.49 seconds
Started Aug 23 09:44:00 AM UTC 24
Finished Aug 23 09:44:09 AM UTC 24
Peak memory 231896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695675514 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3695675514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.2396842979
Short name T94
Test name
Test status
Simulation time 33047275 ps
CPU time 1.94 seconds
Started Aug 23 09:43:52 AM UTC 24
Finished Aug 23 09:43:55 AM UTC 24
Peak memory 228640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396842979 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2396842979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2335911484
Short name T233
Test name
Test status
Simulation time 503461436 ps
CPU time 22.8 seconds
Started Aug 23 09:43:54 AM UTC 24
Finished Aug 23 09:44:18 AM UTC 24
Peak memory 262836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335911484 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2335911484
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.1386953579
Short name T231
Test name
Test status
Simulation time 192868323 ps
CPU time 6.5 seconds
Started Aug 23 09:43:55 AM UTC 24
Finished Aug 23 09:44:02 AM UTC 24
Peak memory 262504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386953579 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1386953579
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.2798122357
Short name T342
Test name
Test status
Simulation time 6811250383 ps
CPU time 227.9 seconds
Started Aug 23 09:44:37 AM UTC 24
Finished Aug 23 09:48:27 AM UTC 24
Peak memory 344476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2798122357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 3.lc_ctrl_stress_all.2798122357
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1793952905
Short name T39
Test name
Test status
Simulation time 17549729 ps
CPU time 0.78 seconds
Started Aug 23 09:43:52 AM UTC 24
Finished Aug 23 09:43:54 AM UTC 24
Peak memory 218556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793952905 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.
lc_ctrl_volatile_unlock_smoke.1793952905
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.2885999189
Short name T603
Test name
Test status
Simulation time 23965152 ps
CPU time 0.71 seconds
Started Aug 23 09:55:27 AM UTC 24
Finished Aug 23 09:55:28 AM UTC 24
Peak memory 217432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885999189 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2885999189
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_errors.297337621
Short name T608
Test name
Test status
Simulation time 346804371 ps
CPU time 14.72 seconds
Started Aug 23 09:55:19 AM UTC 24
Finished Aug 23 09:55:35 AM UTC 24
Peak memory 232216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297337621 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.297337621
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.1135983935
Short name T600
Test name
Test status
Simulation time 82880229 ps
CPU time 1.07 seconds
Started Aug 23 09:55:21 AM UTC 24
Finished Aug 23 09:55:23 AM UTC 24
Peak memory 229388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135983935 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1135983935
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.53902768
Short name T599
Test name
Test status
Simulation time 44544418 ps
CPU time 1.46 seconds
Started Aug 23 09:55:18 AM UTC 24
Finished Aug 23 09:55:20 AM UTC 24
Peak memory 229916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53902768 -assert nopostproc +UVM_TESTNAME=lc_ctr
l_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.53902768
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.3905757520
Short name T609
Test name
Test status
Simulation time 1466983547 ps
CPU time 13.03 seconds
Started Aug 23 09:55:22 AM UTC 24
Finished Aug 23 09:55:36 AM UTC 24
Peak memory 237980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905757520 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3905757520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.320442514
Short name T610
Test name
Test status
Simulation time 733327802 ps
CPU time 12.5 seconds
Started Aug 23 09:55:23 AM UTC 24
Finished Aug 23 09:55:37 AM UTC 24
Peak memory 232140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320442514 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_tok
en_digest.320442514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.3761622674
Short name T604
Test name
Test status
Simulation time 496882722 ps
CPU time 6.64 seconds
Started Aug 23 09:55:22 AM UTC 24
Finished Aug 23 09:55:30 AM UTC 24
Peak memory 237648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761622674 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token
_mux.3761622674
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.3078470716
Short name T605
Test name
Test status
Simulation time 322336544 ps
CPU time 9.51 seconds
Started Aug 23 09:55:19 AM UTC 24
Finished Aug 23 09:55:30 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078470716 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3078470716
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.4171306121
Short name T598
Test name
Test status
Simulation time 49131587 ps
CPU time 3.17 seconds
Started Aug 23 09:55:15 AM UTC 24
Finished Aug 23 09:55:19 AM UTC 24
Peak memory 225452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171306121 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.4171306121
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.38790755
Short name T615
Test name
Test status
Simulation time 4110180157 ps
CPU time 21.67 seconds
Started Aug 23 09:55:17 AM UTC 24
Finished Aug 23 09:55:40 AM UTC 24
Peak memory 262364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38790755 -assert nopostproc +UVM_TESTNAME=lc_ctr
l_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.38790755
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.1819543826
Short name T602
Test name
Test status
Simulation time 79617669 ps
CPU time 5.93 seconds
Started Aug 23 09:55:17 AM UTC 24
Finished Aug 23 09:55:24 AM UTC 24
Peak memory 262412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819543826 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1819543826
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.546631924
Short name T624
Test name
Test status
Simulation time 1253749203 ps
CPU time 26.65 seconds
Started Aug 23 09:55:24 AM UTC 24
Finished Aug 23 09:55:52 AM UTC 24
Peak memory 262528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=546631924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 30.lc_ctrl_stress_all.546631924
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.4254749208
Short name T596
Test name
Test status
Simulation time 48537199 ps
CPU time 0.69 seconds
Started Aug 23 09:55:17 AM UTC 24
Finished Aug 23 09:55:18 AM UTC 24
Peak memory 218152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254749208 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30
.lc_ctrl_volatile_unlock_smoke.4254749208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.3770067864
Short name T620
Test name
Test status
Simulation time 59538058 ps
CPU time 0.94 seconds
Started Aug 23 09:55:46 AM UTC 24
Finished Aug 23 09:55:48 AM UTC 24
Peak memory 218636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770067864 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3770067864
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.1152861646
Short name T560
Test name
Test status
Simulation time 221530327 ps
CPU time 7.25 seconds
Started Aug 23 09:55:37 AM UTC 24
Finished Aug 23 09:55:45 AM UTC 24
Peak memory 237928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152861646 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1152861646
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.464005515
Short name T616
Test name
Test status
Simulation time 829871929 ps
CPU time 5.81 seconds
Started Aug 23 09:55:38 AM UTC 24
Finished Aug 23 09:55:45 AM UTC 24
Peak memory 229556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464005515 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.464005515
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.1330911707
Short name T613
Test name
Test status
Simulation time 148166644 ps
CPU time 3.54 seconds
Started Aug 23 09:55:34 AM UTC 24
Finished Aug 23 09:55:39 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330911707 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1330911707
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.3805009057
Short name T618
Test name
Test status
Simulation time 441952847 ps
CPU time 7.33 seconds
Started Aug 23 09:55:39 AM UTC 24
Finished Aug 23 09:55:48 AM UTC 24
Peak memory 237916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805009057 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3805009057
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.2180924074
Short name T629
Test name
Test status
Simulation time 1931806194 ps
CPU time 17.5 seconds
Started Aug 23 09:55:41 AM UTC 24
Finished Aug 23 09:55:59 AM UTC 24
Peak memory 231152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180924074 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_to
ken_digest.2180924074
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.3938802836
Short name T622
Test name
Test status
Simulation time 643485476 ps
CPU time 8.36 seconds
Started Aug 23 09:55:41 AM UTC 24
Finished Aug 23 09:55:50 AM UTC 24
Peak memory 237296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938802836 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token
_mux.3938802836
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.669065830
Short name T617
Test name
Test status
Simulation time 3529087049 ps
CPU time 8.49 seconds
Started Aug 23 09:55:37 AM UTC 24
Finished Aug 23 09:55:47 AM UTC 24
Peak memory 232280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669065830 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.669065830
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.2117113053
Short name T606
Test name
Test status
Simulation time 206306718 ps
CPU time 1.88 seconds
Started Aug 23 09:55:29 AM UTC 24
Finished Aug 23 09:55:32 AM UTC 24
Peak memory 224360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117113053 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2117113053
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.1735298129
Short name T630
Test name
Test status
Simulation time 1301603531 ps
CPU time 27.05 seconds
Started Aug 23 09:55:31 AM UTC 24
Finished Aug 23 09:56:00 AM UTC 24
Peak memory 262496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735298129 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1735298129
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.2744269930
Short name T614
Test name
Test status
Simulation time 90700849 ps
CPU time 6.29 seconds
Started Aug 23 09:55:32 AM UTC 24
Finished Aug 23 09:55:40 AM UTC 24
Peak memory 262504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744269930 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2744269930
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.1200031340
Short name T692
Test name
Test status
Simulation time 20880570902 ps
CPU time 93.83 seconds
Started Aug 23 09:55:41 AM UTC 24
Finished Aug 23 09:57:16 AM UTC 24
Peak memory 237988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1200031340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 31.lc_ctrl_stress_all.1200031340
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2129397725
Short name T607
Test name
Test status
Simulation time 16512549 ps
CPU time 0.8 seconds
Started Aug 23 09:55:31 AM UTC 24
Finished Aug 23 09:55:33 AM UTC 24
Peak memory 218288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129397725 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31
.lc_ctrl_volatile_unlock_smoke.2129397725
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.3612947822
Short name T631
Test name
Test status
Simulation time 203625313 ps
CPU time 0.81 seconds
Started Aug 23 09:55:58 AM UTC 24
Finished Aug 23 09:56:00 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612947822 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3612947822
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_errors.200258562
Short name T632
Test name
Test status
Simulation time 483897655 ps
CPU time 10.13 seconds
Started Aug 23 09:55:49 AM UTC 24
Finished Aug 23 09:56:00 AM UTC 24
Peak memory 237928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200258562 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.200258562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.114627199
Short name T636
Test name
Test status
Simulation time 482941307 ps
CPU time 11.8 seconds
Started Aug 23 09:55:51 AM UTC 24
Finished Aug 23 09:56:04 AM UTC 24
Peak memory 229576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114627199 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.114627199
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.20308276
Short name T623
Test name
Test status
Simulation time 171572786 ps
CPU time 2.21 seconds
Started Aug 23 09:55:49 AM UTC 24
Finished Aug 23 09:55:52 AM UTC 24
Peak memory 232208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20308276 -assert nopostproc +UVM_TESTNAME=lc_ctr
l_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.20308276
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.3646623140
Short name T643
Test name
Test status
Simulation time 3278438224 ps
CPU time 15.21 seconds
Started Aug 23 09:55:54 AM UTC 24
Finished Aug 23 09:56:10 AM UTC 24
Peak memory 231940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646623140 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3646623140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.3461321009
Short name T641
Test name
Test status
Simulation time 2641141258 ps
CPU time 13.31 seconds
Started Aug 23 09:55:54 AM UTC 24
Finished Aug 23 09:56:08 AM UTC 24
Peak memory 232200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461321009 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_to
ken_digest.3461321009
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.3682998912
Short name T633
Test name
Test status
Simulation time 207573570 ps
CPU time 5.7 seconds
Started Aug 23 09:55:54 AM UTC 24
Finished Aug 23 09:56:01 AM UTC 24
Peak memory 229908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682998912 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token
_mux.3682998912
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.713271320
Short name T627
Test name
Test status
Simulation time 1254672611 ps
CPU time 6.07 seconds
Started Aug 23 09:55:50 AM UTC 24
Finished Aug 23 09:55:57 AM UTC 24
Peak memory 237592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713271320 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.713271320
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.2852510000
Short name T621
Test name
Test status
Simulation time 94615147 ps
CPU time 1.97 seconds
Started Aug 23 09:55:46 AM UTC 24
Finished Aug 23 09:55:49 AM UTC 24
Peak memory 228440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852510000 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2852510000
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.2683257593
Short name T645
Test name
Test status
Simulation time 267270384 ps
CPU time 24.23 seconds
Started Aug 23 09:55:47 AM UTC 24
Finished Aug 23 09:56:13 AM UTC 24
Peak memory 262500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683257593 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2683257593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.725925402
Short name T625
Test name
Test status
Simulation time 53710436 ps
CPU time 2.46 seconds
Started Aug 23 09:55:49 AM UTC 24
Finished Aug 23 09:55:52 AM UTC 24
Peak memory 236384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725925402 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.725925402
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.3424319838
Short name T860
Test name
Test status
Simulation time 37207450448 ps
CPU time 338.67 seconds
Started Aug 23 09:55:54 AM UTC 24
Finished Aug 23 10:01:37 AM UTC 24
Peak memory 262640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3424319838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 32.lc_ctrl_stress_all.3424319838
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.4076097513
Short name T619
Test name
Test status
Simulation time 24319761 ps
CPU time 0.8 seconds
Started Aug 23 09:55:46 AM UTC 24
Finished Aug 23 09:55:48 AM UTC 24
Peak memory 218552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076097513 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32
.lc_ctrl_volatile_unlock_smoke.4076097513
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.2791384275
Short name T644
Test name
Test status
Simulation time 38513631 ps
CPU time 0.84 seconds
Started Aug 23 09:56:09 AM UTC 24
Finished Aug 23 09:56:11 AM UTC 24
Peak memory 218760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791384275 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2791384275
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_errors.2165676539
Short name T648
Test name
Test status
Simulation time 5648217796 ps
CPU time 11.09 seconds
Started Aug 23 09:56:02 AM UTC 24
Finished Aug 23 09:56:14 AM UTC 24
Peak memory 231940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165676539 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2165676539
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.3874746364
Short name T640
Test name
Test status
Simulation time 465948395 ps
CPU time 2.79 seconds
Started Aug 23 09:56:05 AM UTC 24
Finished Aug 23 09:56:08 AM UTC 24
Peak memory 229548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874746364 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3874746364
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.3316980401
Short name T638
Test name
Test status
Simulation time 83596623 ps
CPU time 2.81 seconds
Started Aug 23 09:56:01 AM UTC 24
Finished Aug 23 09:56:05 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316980401 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3316980401
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.1434265060
Short name T654
Test name
Test status
Simulation time 1080421953 ps
CPU time 13.77 seconds
Started Aug 23 09:56:06 AM UTC 24
Finished Aug 23 09:56:21 AM UTC 24
Peak memory 237404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434265060 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1434265060
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.352642957
Short name T649
Test name
Test status
Simulation time 315259772 ps
CPU time 8.09 seconds
Started Aug 23 09:56:06 AM UTC 24
Finished Aug 23 09:56:15 AM UTC 24
Peak memory 231812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352642957 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_tok
en_digest.352642957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.2074399358
Short name T651
Test name
Test status
Simulation time 371364700 ps
CPU time 11.46 seconds
Started Aug 23 09:56:06 AM UTC 24
Finished Aug 23 09:56:19 AM UTC 24
Peak memory 231528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074399358 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token
_mux.2074399358
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.1076091360
Short name T642
Test name
Test status
Simulation time 166693081 ps
CPU time 5.01 seconds
Started Aug 23 09:56:03 AM UTC 24
Finished Aug 23 09:56:09 AM UTC 24
Peak memory 231944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076091360 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1076091360
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.2886068810
Short name T635
Test name
Test status
Simulation time 56584919 ps
CPU time 3.38 seconds
Started Aug 23 09:55:59 AM UTC 24
Finished Aug 23 09:56:04 AM UTC 24
Peak memory 229888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886068810 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2886068810
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.3393543711
Short name T652
Test name
Test status
Simulation time 772224606 ps
CPU time 17.48 seconds
Started Aug 23 09:56:01 AM UTC 24
Finished Aug 23 09:56:20 AM UTC 24
Peak memory 262496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393543711 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3393543711
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.500378140
Short name T637
Test name
Test status
Simulation time 248981397 ps
CPU time 2.44 seconds
Started Aug 23 09:56:01 AM UTC 24
Finished Aug 23 09:56:04 AM UTC 24
Peak memory 234336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500378140 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.500378140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.1540252405
Short name T713
Test name
Test status
Simulation time 33266709595 ps
CPU time 90.7 seconds
Started Aug 23 09:56:06 AM UTC 24
Finished Aug 23 09:57:39 AM UTC 24
Peak memory 281072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1540252405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 33.lc_ctrl_stress_all.1540252405
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1382370629
Short name T634
Test name
Test status
Simulation time 10786670 ps
CPU time 0.8 seconds
Started Aug 23 09:56:01 AM UTC 24
Finished Aug 23 09:56:03 AM UTC 24
Peak memory 218228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382370629 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33
.lc_ctrl_volatile_unlock_smoke.1382370629
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.4185921345
Short name T657
Test name
Test status
Simulation time 88051550 ps
CPU time 0.81 seconds
Started Aug 23 09:56:25 AM UTC 24
Finished Aug 23 09:56:27 AM UTC 24
Peak memory 219132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185921345 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.4185921345
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_errors.3948762579
Short name T658
Test name
Test status
Simulation time 684327498 ps
CPU time 11.29 seconds
Started Aug 23 09:56:14 AM UTC 24
Finished Aug 23 09:56:27 AM UTC 24
Peak memory 237660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948762579 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3948762579
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.4077088216
Short name T655
Test name
Test status
Simulation time 1826115855 ps
CPU time 7.62 seconds
Started Aug 23 09:56:16 AM UTC 24
Finished Aug 23 09:56:24 AM UTC 24
Peak memory 229620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077088216 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.4077088216
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.109982414
Short name T653
Test name
Test status
Simulation time 121659315 ps
CPU time 4.41 seconds
Started Aug 23 09:56:14 AM UTC 24
Finished Aug 23 09:56:20 AM UTC 24
Peak memory 232212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109982414 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.109982414
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.1778478912
Short name T663
Test name
Test status
Simulation time 497427991 ps
CPU time 11.58 seconds
Started Aug 23 09:56:19 AM UTC 24
Finished Aug 23 09:56:32 AM UTC 24
Peak memory 231952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778478912 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1778478912
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.3382643460
Short name T662
Test name
Test status
Simulation time 354758301 ps
CPU time 9.02 seconds
Started Aug 23 09:56:20 AM UTC 24
Finished Aug 23 09:56:30 AM UTC 24
Peak memory 237520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382643460 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_to
ken_digest.3382643460
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.3263480174
Short name T660
Test name
Test status
Simulation time 963111236 ps
CPU time 8.87 seconds
Started Aug 23 09:56:19 AM UTC 24
Finished Aug 23 09:56:29 AM UTC 24
Peak memory 231884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263480174 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token
_mux.3263480174
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.389771617
Short name T656
Test name
Test status
Simulation time 1785307381 ps
CPU time 8.62 seconds
Started Aug 23 09:56:16 AM UTC 24
Finished Aug 23 09:56:25 AM UTC 24
Peak memory 231888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389771617 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.389771617
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.128259861
Short name T646
Test name
Test status
Simulation time 34550888 ps
CPU time 1.6 seconds
Started Aug 23 09:56:11 AM UTC 24
Finished Aug 23 09:56:13 AM UTC 24
Peak memory 224364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128259861 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.128259861
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.999237698
Short name T665
Test name
Test status
Simulation time 1419457349 ps
CPU time 20.55 seconds
Started Aug 23 09:56:12 AM UTC 24
Finished Aug 23 09:56:34 AM UTC 24
Peak memory 258480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999237698 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.999237698
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.3236727826
Short name T650
Test name
Test status
Simulation time 253570108 ps
CPU time 3.14 seconds
Started Aug 23 09:56:14 AM UTC 24
Finished Aug 23 09:56:18 AM UTC 24
Peak memory 234660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236727826 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3236727826
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.882300229
Short name T862
Test name
Test status
Simulation time 99394125754 ps
CPU time 339.91 seconds
Started Aug 23 09:56:21 AM UTC 24
Finished Aug 23 10:02:05 AM UTC 24
Peak memory 233980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=882300229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 34.lc_ctrl_stress_all.882300229
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.4117538757
Short name T647
Test name
Test status
Simulation time 16237002 ps
CPU time 0.68 seconds
Started Aug 23 09:56:12 AM UTC 24
Finished Aug 23 09:56:14 AM UTC 24
Peak memory 219088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117538757 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34
.lc_ctrl_volatile_unlock_smoke.4117538757
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.2596264302
Short name T668
Test name
Test status
Simulation time 67364232 ps
CPU time 0.78 seconds
Started Aug 23 09:56:38 AM UTC 24
Finished Aug 23 09:56:40 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596264302 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2596264302
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_errors.2909899563
Short name T669
Test name
Test status
Simulation time 1046818043 ps
CPU time 9.78 seconds
Started Aug 23 09:56:30 AM UTC 24
Finished Aug 23 09:56:41 AM UTC 24
Peak memory 231940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909899563 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2909899563
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.787701591
Short name T666
Test name
Test status
Simulation time 296809392 ps
CPU time 1.37 seconds
Started Aug 23 09:56:31 AM UTC 24
Finished Aug 23 09:56:34 AM UTC 24
Peak memory 229100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787701591 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.787701591
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.3709301505
Short name T664
Test name
Test status
Simulation time 115723637 ps
CPU time 2.03 seconds
Started Aug 23 09:56:30 AM UTC 24
Finished Aug 23 09:56:33 AM UTC 24
Peak memory 231948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709301505 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3709301505
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.1767022443
Short name T671
Test name
Test status
Simulation time 1032467333 ps
CPU time 8.18 seconds
Started Aug 23 09:56:33 AM UTC 24
Finished Aug 23 09:56:42 AM UTC 24
Peak memory 237912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767022443 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1767022443
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.437300918
Short name T676
Test name
Test status
Simulation time 2860948933 ps
CPU time 11.32 seconds
Started Aug 23 09:56:35 AM UTC 24
Finished Aug 23 09:56:48 AM UTC 24
Peak memory 231872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437300918 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_tok
en_digest.437300918
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.1888458454
Short name T672
Test name
Test status
Simulation time 1002494378 ps
CPU time 8.24 seconds
Started Aug 23 09:56:34 AM UTC 24
Finished Aug 23 09:56:43 AM UTC 24
Peak memory 231956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888458454 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token
_mux.1888458454
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.774213185
Short name T670
Test name
Test status
Simulation time 1340435020 ps
CPU time 9.94 seconds
Started Aug 23 09:56:30 AM UTC 24
Finished Aug 23 09:56:41 AM UTC 24
Peak memory 237444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774213185 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.774213185
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.3768699753
Short name T661
Test name
Test status
Simulation time 205849055 ps
CPU time 2.21 seconds
Started Aug 23 09:56:26 AM UTC 24
Finished Aug 23 09:56:29 AM UTC 24
Peak memory 229624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768699753 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3768699753
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.2446487935
Short name T675
Test name
Test status
Simulation time 200599460 ps
CPU time 17.48 seconds
Started Aug 23 09:56:27 AM UTC 24
Finished Aug 23 09:56:46 AM UTC 24
Peak memory 258480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446487935 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2446487935
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.1198090503
Short name T667
Test name
Test status
Simulation time 361855549 ps
CPU time 6.71 seconds
Started Aug 23 09:56:30 AM UTC 24
Finished Aug 23 09:56:38 AM UTC 24
Peak memory 260416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198090503 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1198090503
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.547774990
Short name T702
Test name
Test status
Simulation time 9251565286 ps
CPU time 50.74 seconds
Started Aug 23 09:56:35 AM UTC 24
Finished Aug 23 09:57:27 AM UTC 24
Peak memory 289232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=547774990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 35.lc_ctrl_stress_all.547774990
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1565468963
Short name T698
Test name
Test status
Simulation time 1529285232 ps
CPU time 47.47 seconds
Started Aug 23 09:56:35 AM UTC 24
Finished Aug 23 09:57:24 AM UTC 24
Peak memory 281064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565468963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_u
nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1565468963
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1336873957
Short name T659
Test name
Test status
Simulation time 46152654 ps
CPU time 0.71 seconds
Started Aug 23 09:56:27 AM UTC 24
Finished Aug 23 09:56:29 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336873957 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35
.lc_ctrl_volatile_unlock_smoke.1336873957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.2161875359
Short name T683
Test name
Test status
Simulation time 40422739 ps
CPU time 0.85 seconds
Started Aug 23 09:56:56 AM UTC 24
Finished Aug 23 09:56:58 AM UTC 24
Peak memory 219120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161875359 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2161875359
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_errors.1610324067
Short name T680
Test name
Test status
Simulation time 703477852 ps
CPU time 7.36 seconds
Started Aug 23 09:56:44 AM UTC 24
Finished Aug 23 09:56:53 AM UTC 24
Peak memory 237280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610324067 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1610324067
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.2611146189
Short name T679
Test name
Test status
Simulation time 340439465 ps
CPU time 2.7 seconds
Started Aug 23 09:56:47 AM UTC 24
Finished Aug 23 09:56:50 AM UTC 24
Peak memory 229492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611146189 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2611146189
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.213096033
Short name T677
Test name
Test status
Simulation time 276772040 ps
CPU time 2.58 seconds
Started Aug 23 09:56:44 AM UTC 24
Finished Aug 23 09:56:48 AM UTC 24
Peak memory 235976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213096033 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.213096033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.3320855239
Short name T682
Test name
Test status
Simulation time 338050440 ps
CPU time 7.26 seconds
Started Aug 23 09:56:48 AM UTC 24
Finished Aug 23 09:56:56 AM UTC 24
Peak memory 237596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320855239 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3320855239
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.1699013952
Short name T688
Test name
Test status
Simulation time 1826354236 ps
CPU time 12.95 seconds
Started Aug 23 09:56:51 AM UTC 24
Finished Aug 23 09:57:05 AM UTC 24
Peak memory 237660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699013952 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_to
ken_digest.1699013952
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.2572672975
Short name T684
Test name
Test status
Simulation time 2163066720 ps
CPU time 8.3 seconds
Started Aug 23 09:56:49 AM UTC 24
Finished Aug 23 09:56:58 AM UTC 24
Peak memory 231940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572672975 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token
_mux.2572672975
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.3933072354
Short name T681
Test name
Test status
Simulation time 489141552 ps
CPU time 8.12 seconds
Started Aug 23 09:56:46 AM UTC 24
Finished Aug 23 09:56:55 AM UTC 24
Peak memory 237588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933072354 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3933072354
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.709576221
Short name T674
Test name
Test status
Simulation time 170255666 ps
CPU time 2.7 seconds
Started Aug 23 09:56:41 AM UTC 24
Finished Aug 23 09:56:44 AM UTC 24
Peak memory 225464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709576221 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.709576221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.1346949307
Short name T690
Test name
Test status
Simulation time 628107416 ps
CPU time 26.18 seconds
Started Aug 23 09:56:42 AM UTC 24
Finished Aug 23 09:57:09 AM UTC 24
Peak memory 262496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346949307 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1346949307
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.3765548812
Short name T678
Test name
Test status
Simulation time 79323308 ps
CPU time 6.27 seconds
Started Aug 23 09:56:43 AM UTC 24
Finished Aug 23 09:56:50 AM UTC 24
Peak memory 262776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765548812 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3765548812
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.1770688282
Short name T701
Test name
Test status
Simulation time 2941478973 ps
CPU time 33.93 seconds
Started Aug 23 09:56:51 AM UTC 24
Finished Aug 23 09:57:27 AM UTC 24
Peak memory 262560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1770688282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 36.lc_ctrl_stress_all.1770688282
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.734388823
Short name T757
Test name
Test status
Simulation time 8759878945 ps
CPU time 89.94 seconds
Started Aug 23 09:56:54 AM UTC 24
Finished Aug 23 09:58:25 AM UTC 24
Peak memory 291368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734388823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S
EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_un
lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.734388823
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.680414097
Short name T673
Test name
Test status
Simulation time 77297301 ps
CPU time 0.69 seconds
Started Aug 23 09:56:42 AM UTC 24
Finished Aug 23 09:56:43 AM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680414097 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.
lc_ctrl_volatile_unlock_smoke.680414097
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.1695110036
Short name T697
Test name
Test status
Simulation time 35118910 ps
CPU time 0.93 seconds
Started Aug 23 09:57:21 AM UTC 24
Finished Aug 23 09:57:23 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695110036 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1695110036
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.2988919776
Short name T626
Test name
Test status
Simulation time 742082256 ps
CPU time 14.49 seconds
Started Aug 23 09:57:06 AM UTC 24
Finished Aug 23 09:57:22 AM UTC 24
Peak memory 229968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988919776 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2988919776
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.2370369248
Short name T691
Test name
Test status
Simulation time 99741008 ps
CPU time 1.88 seconds
Started Aug 23 09:57:07 AM UTC 24
Finished Aug 23 09:57:10 AM UTC 24
Peak memory 227984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370369248 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2370369248
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.3709113067
Short name T689
Test name
Test status
Simulation time 226630993 ps
CPU time 3.09 seconds
Started Aug 23 09:57:02 AM UTC 24
Finished Aug 23 09:57:06 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709113067 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3709113067
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.2706451469
Short name T704
Test name
Test status
Simulation time 2669872277 ps
CPU time 16.08 seconds
Started Aug 23 09:57:10 AM UTC 24
Finished Aug 23 09:57:28 AM UTC 24
Peak memory 232012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706451469 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2706451469
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.2126067693
Short name T695
Test name
Test status
Simulation time 1083855282 ps
CPU time 8.44 seconds
Started Aug 23 09:57:12 AM UTC 24
Finished Aug 23 09:57:21 AM UTC 24
Peak memory 231808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126067693 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_to
ken_digest.2126067693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.1708971201
Short name T694
Test name
Test status
Simulation time 436559484 ps
CPU time 7.18 seconds
Started Aug 23 09:57:12 AM UTC 24
Finished Aug 23 09:57:20 AM UTC 24
Peak memory 232148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708971201 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token
_mux.1708971201
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.463682166
Short name T693
Test name
Test status
Simulation time 442786094 ps
CPU time 8.95 seconds
Started Aug 23 09:57:07 AM UTC 24
Finished Aug 23 09:57:17 AM UTC 24
Peak memory 231960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463682166 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.463682166
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.3107750242
Short name T686
Test name
Test status
Simulation time 71557523 ps
CPU time 2.38 seconds
Started Aug 23 09:56:57 AM UTC 24
Finished Aug 23 09:57:00 AM UTC 24
Peak memory 225532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107750242 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3107750242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.3369775166
Short name T696
Test name
Test status
Simulation time 209305463 ps
CPU time 22.47 seconds
Started Aug 23 09:56:59 AM UTC 24
Finished Aug 23 09:57:23 AM UTC 24
Peak memory 262496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369775166 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3369775166
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.228812548
Short name T687
Test name
Test status
Simulation time 74694168 ps
CPU time 2.86 seconds
Started Aug 23 09:57:00 AM UTC 24
Finished Aug 23 09:57:05 AM UTC 24
Peak memory 234344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228812548 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.228812548
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.2501718207
Short name T865
Test name
Test status
Simulation time 14756888263 ps
CPU time 342.35 seconds
Started Aug 23 09:57:17 AM UTC 24
Finished Aug 23 10:03:03 AM UTC 24
Peak memory 264604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2501718207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 37.lc_ctrl_stress_all.2501718207
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3495150648
Short name T685
Test name
Test status
Simulation time 34754024 ps
CPU time 0.83 seconds
Started Aug 23 09:56:58 AM UTC 24
Finished Aug 23 09:57:00 AM UTC 24
Peak memory 220328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495150648 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37
.lc_ctrl_volatile_unlock_smoke.3495150648
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.1467622259
Short name T708
Test name
Test status
Simulation time 41453706 ps
CPU time 0.93 seconds
Started Aug 23 09:57:32 AM UTC 24
Finished Aug 23 09:57:34 AM UTC 24
Peak memory 218760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467622259 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1467622259
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.2541267972
Short name T722
Test name
Test status
Simulation time 5878522766 ps
CPU time 19.73 seconds
Started Aug 23 09:57:25 AM UTC 24
Finished Aug 23 09:57:46 AM UTC 24
Peak memory 237652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541267972 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2541267972
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.2710187860
Short name T706
Test name
Test status
Simulation time 157434543 ps
CPU time 2.94 seconds
Started Aug 23 09:57:27 AM UTC 24
Finished Aug 23 09:57:31 AM UTC 24
Peak memory 229544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710187860 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2710187860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.105793653
Short name T703
Test name
Test status
Simulation time 290591186 ps
CPU time 2.17 seconds
Started Aug 23 09:57:24 AM UTC 24
Finished Aug 23 09:57:27 AM UTC 24
Peak memory 231888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105793653 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.105793653
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.117925328
Short name T717
Test name
Test status
Simulation time 418161488 ps
CPU time 12.53 seconds
Started Aug 23 09:57:28 AM UTC 24
Finished Aug 23 09:57:42 AM UTC 24
Peak memory 237580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117925328 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.117925328
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.614496992
Short name T718
Test name
Test status
Simulation time 699200349 ps
CPU time 13.29 seconds
Started Aug 23 09:57:28 AM UTC 24
Finished Aug 23 09:57:43 AM UTC 24
Peak memory 237848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614496992 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_tok
en_digest.614496992
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.1390201913
Short name T714
Test name
Test status
Simulation time 293002526 ps
CPU time 10.47 seconds
Started Aug 23 09:57:28 AM UTC 24
Finished Aug 23 09:57:40 AM UTC 24
Peak memory 237500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390201913 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token
_mux.1390201913
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.484107329
Short name T709
Test name
Test status
Simulation time 1137389858 ps
CPU time 8.04 seconds
Started Aug 23 09:57:25 AM UTC 24
Finished Aug 23 09:57:35 AM UTC 24
Peak memory 237592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484107329 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.484107329
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.4100075227
Short name T700
Test name
Test status
Simulation time 34145264 ps
CPU time 1.94 seconds
Started Aug 23 09:57:23 AM UTC 24
Finished Aug 23 09:57:26 AM UTC 24
Peak memory 224360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100075227 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.4100075227
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.1858394714
Short name T732
Test name
Test status
Simulation time 1433240243 ps
CPU time 31.31 seconds
Started Aug 23 09:57:24 AM UTC 24
Finished Aug 23 09:57:57 AM UTC 24
Peak memory 262496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858394714 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1858394714
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.3864675963
Short name T707
Test name
Test status
Simulation time 84268276 ps
CPU time 7.75 seconds
Started Aug 23 09:57:24 AM UTC 24
Finished Aug 23 09:57:33 AM UTC 24
Peak memory 262500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864675963 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3864675963
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.1548151828
Short name T744
Test name
Test status
Simulation time 1715461761 ps
CPU time 39.21 seconds
Started Aug 23 09:57:28 AM UTC 24
Finished Aug 23 09:58:09 AM UTC 24
Peak memory 262492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1548151828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 38.lc_ctrl_stress_all.1548151828
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.1330405520
Short name T762
Test name
Test status
Simulation time 6588416594 ps
CPU time 58.83 seconds
Started Aug 23 09:57:31 AM UTC 24
Finished Aug 23 09:58:31 AM UTC 24
Peak memory 281120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330405520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_u
nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.1330405520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1493768911
Short name T699
Test name
Test status
Simulation time 15665317 ps
CPU time 0.9 seconds
Started Aug 23 09:57:23 AM UTC 24
Finished Aug 23 09:57:25 AM UTC 24
Peak memory 228504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493768911 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38
.lc_ctrl_volatile_unlock_smoke.1493768911
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.1659304751
Short name T723
Test name
Test status
Simulation time 75752615 ps
CPU time 0.87 seconds
Started Aug 23 09:57:45 AM UTC 24
Finished Aug 23 09:57:47 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659304751 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1659304751
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_errors.216358343
Short name T724
Test name
Test status
Simulation time 5334866649 ps
CPU time 9.47 seconds
Started Aug 23 09:57:37 AM UTC 24
Finished Aug 23 09:57:48 AM UTC 24
Peak memory 237992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216358343 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.216358343
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.431672847
Short name T719
Test name
Test status
Simulation time 1023807528 ps
CPU time 3.84 seconds
Started Aug 23 09:57:40 AM UTC 24
Finished Aug 23 09:57:44 AM UTC 24
Peak memory 229836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431672847 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.431672847
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.3843036297
Short name T716
Test name
Test status
Simulation time 96052423 ps
CPU time 3.29 seconds
Started Aug 23 09:57:37 AM UTC 24
Finished Aug 23 09:57:41 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843036297 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3843036297
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1449659387
Short name T727
Test name
Test status
Simulation time 1430972375 ps
CPU time 9.7 seconds
Started Aug 23 09:57:41 AM UTC 24
Finished Aug 23 09:57:52 AM UTC 24
Peak memory 237912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449659387 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1449659387
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.3995919296
Short name T730
Test name
Test status
Simulation time 1266158566 ps
CPU time 10.78 seconds
Started Aug 23 09:57:43 AM UTC 24
Finished Aug 23 09:57:54 AM UTC 24
Peak memory 237520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995919296 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_to
ken_digest.3995919296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.2508344588
Short name T729
Test name
Test status
Simulation time 410829586 ps
CPU time 9.73 seconds
Started Aug 23 09:57:43 AM UTC 24
Finished Aug 23 09:57:53 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508344588 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token
_mux.2508344588
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.1483485454
Short name T721
Test name
Test status
Simulation time 229000219 ps
CPU time 5.99 seconds
Started Aug 23 09:57:38 AM UTC 24
Finished Aug 23 09:57:45 AM UTC 24
Peak memory 231948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483485454 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1483485454
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.1096569923
Short name T711
Test name
Test status
Simulation time 22111364 ps
CPU time 1.15 seconds
Started Aug 23 09:57:34 AM UTC 24
Finished Aug 23 09:57:36 AM UTC 24
Peak memory 222316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096569923 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1096569923
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.3402074433
Short name T737
Test name
Test status
Simulation time 2090182293 ps
CPU time 25.56 seconds
Started Aug 23 09:57:35 AM UTC 24
Finished Aug 23 09:58:02 AM UTC 24
Peak memory 258608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402074433 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3402074433
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.3265588662
Short name T720
Test name
Test status
Simulation time 257694378 ps
CPU time 6.66 seconds
Started Aug 23 09:57:37 AM UTC 24
Finished Aug 23 09:57:45 AM UTC 24
Peak memory 258480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265588662 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3265588662
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.3793088883
Short name T756
Test name
Test status
Simulation time 1070399236 ps
CPU time 38.92 seconds
Started Aug 23 09:57:43 AM UTC 24
Finished Aug 23 09:58:23 AM UTC 24
Peak memory 262576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3793088883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 39.lc_ctrl_stress_all.3793088883
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.4260180668
Short name T151
Test name
Test status
Simulation time 3709077761 ps
CPU time 79.89 seconds
Started Aug 23 09:57:44 AM UTC 24
Finished Aug 23 09:59:05 AM UTC 24
Peak memory 283244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260180668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_u
nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.4260180668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.947528280
Short name T712
Test name
Test status
Simulation time 36264532 ps
CPU time 0.86 seconds
Started Aug 23 09:57:35 AM UTC 24
Finished Aug 23 09:57:37 AM UTC 24
Peak memory 228780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947528280 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.
lc_ctrl_volatile_unlock_smoke.947528280
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.1222069695
Short name T247
Test name
Test status
Simulation time 44337849 ps
CPU time 0.91 seconds
Started Aug 23 09:45:19 AM UTC 24
Finished Aug 23 09:45:21 AM UTC 24
Peak memory 218524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222069695 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1222069695
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.763460809
Short name T148
Test name
Test status
Simulation time 1023164430 ps
CPU time 10.54 seconds
Started Aug 23 09:44:55 AM UTC 24
Finished Aug 23 09:45:07 AM UTC 24
Peak memory 231948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763460809 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.763460809
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.384885378
Short name T27
Test name
Test status
Simulation time 1144878414 ps
CPU time 5.23 seconds
Started Aug 23 09:45:08 AM UTC 24
Finished Aug 23 09:45:14 AM UTC 24
Peak memory 229460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384885378 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.384885378
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.483854447
Short name T245
Test name
Test status
Simulation time 755819609 ps
CPU time 7.88 seconds
Started Aug 23 09:45:08 AM UTC 24
Finished Aug 23 09:45:17 AM UTC 24
Peak memory 229212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483854447 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.483854447
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.3735938587
Short name T248
Test name
Test status
Simulation time 1343853895 ps
CPU time 16.51 seconds
Started Aug 23 09:45:04 AM UTC 24
Finished Aug 23 09:45:22 AM UTC 24
Peak memory 237216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735938587
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_jtag_prog_failure.3735938587
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3454138735
Short name T250
Test name
Test status
Simulation time 1053454806 ps
CPU time 14.54 seconds
Started Aug 23 09:45:08 AM UTC 24
Finished Aug 23 09:45:24 AM UTC 24
Peak memory 229484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454138735
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_
ctrl_jtag_regwen_during_op.3454138735
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.1253592151
Short name T79
Test name
Test status
Simulation time 818433269 ps
CPU time 5.7 seconds
Started Aug 23 09:45:01 AM UTC 24
Finished Aug 23 09:45:07 AM UTC 24
Peak memory 229184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253592151
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_s
moke.1253592151
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2475053312
Short name T253
Test name
Test status
Simulation time 934061348 ps
CPU time 28.09 seconds
Started Aug 23 09:45:01 AM UTC 24
Finished Aug 23 09:45:30 AM UTC 24
Peak memory 262112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475053312
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_jtag_state_failure.2475053312
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.2701055345
Short name T150
Test name
Test status
Simulation time 1764069829 ps
CPU time 12.02 seconds
Started Aug 23 09:45:03 AM UTC 24
Finished Aug 23 09:45:16 AM UTC 24
Peak memory 258416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701055345
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_
ctrl_jtag_state_post_trans.2701055345
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.1729079785
Short name T242
Test name
Test status
Simulation time 35570428 ps
CPU time 2.07 seconds
Started Aug 23 09:44:52 AM UTC 24
Finished Aug 23 09:44:55 AM UTC 24
Peak memory 236044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729079785 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1729079785
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.4225787716
Short name T147
Test name
Test status
Simulation time 2593711071 ps
CPU time 7.79 seconds
Started Aug 23 09:44:57 AM UTC 24
Finished Aug 23 09:45:06 AM UTC 24
Peak memory 229636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225787716 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.4225787716
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.586488617
Short name T103
Test name
Test status
Simulation time 448023869 ps
CPU time 17.77 seconds
Started Aug 23 09:45:18 AM UTC 24
Finished Aug 23 09:45:37 AM UTC 24
Peak memory 287892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586488617 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.586488617
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.140907773
Short name T254
Test name
Test status
Simulation time 3441693166 ps
CPU time 20.73 seconds
Started Aug 23 09:45:09 AM UTC 24
Finished Aug 23 09:45:31 AM UTC 24
Peak memory 237648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140907773 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.140907773
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.3156618189
Short name T251
Test name
Test status
Simulation time 1309499193 ps
CPU time 7.25 seconds
Started Aug 23 09:45:16 AM UTC 24
Finished Aug 23 09:45:24 AM UTC 24
Peak memory 231816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156618189 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_tok
en_digest.3156618189
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.2826421230
Short name T246
Test name
Test status
Simulation time 933473201 ps
CPU time 8.04 seconds
Started Aug 23 09:45:10 AM UTC 24
Finished Aug 23 09:45:19 AM UTC 24
Peak memory 231940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826421230 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_
mux.2826421230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.1218169768
Short name T69
Test name
Test status
Simulation time 828687133 ps
CPU time 9.43 seconds
Started Aug 23 09:44:56 AM UTC 24
Finished Aug 23 09:45:07 AM UTC 24
Peak memory 236904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218169768 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1218169768
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.3328997878
Short name T78
Test name
Test status
Simulation time 111187236 ps
CPU time 4.26 seconds
Started Aug 23 09:44:46 AM UTC 24
Finished Aug 23 09:44:51 AM UTC 24
Peak memory 229552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328997878 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3328997878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.183762449
Short name T244
Test name
Test status
Simulation time 371232075 ps
CPU time 26.03 seconds
Started Aug 23 09:44:49 AM UTC 24
Finished Aug 23 09:45:16 AM UTC 24
Peak memory 262504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183762449 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.183762449
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1344304360
Short name T243
Test name
Test status
Simulation time 168271068 ps
CPU time 5.85 seconds
Started Aug 23 09:44:50 AM UTC 24
Finished Aug 23 09:44:57 AM UTC 24
Peak memory 260372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344304360 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1344304360
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1449398379
Short name T241
Test name
Test status
Simulation time 23869572 ps
CPU time 0.72 seconds
Started Aug 23 09:44:48 AM UTC 24
Finished Aug 23 09:44:50 AM UTC 24
Peak memory 218348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449398379 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.
lc_ctrl_volatile_unlock_smoke.1449398379
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.249072762
Short name T734
Test name
Test status
Simulation time 35416115 ps
CPU time 1.03 seconds
Started Aug 23 09:57:58 AM UTC 24
Finished Aug 23 09:58:00 AM UTC 24
Peak memory 218644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249072762 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.249072762
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_errors.2915935046
Short name T738
Test name
Test status
Simulation time 705494894 ps
CPU time 12.05 seconds
Started Aug 23 09:57:49 AM UTC 24
Finished Aug 23 09:58:02 AM UTC 24
Peak memory 231948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915935046 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2915935046
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.1637099817
Short name T733
Test name
Test status
Simulation time 130364014 ps
CPU time 3.62 seconds
Started Aug 23 09:57:53 AM UTC 24
Finished Aug 23 09:57:57 AM UTC 24
Peak memory 229504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637099817 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1637099817
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.704244516
Short name T728
Test name
Test status
Simulation time 21134482 ps
CPU time 1.57 seconds
Started Aug 23 09:57:49 AM UTC 24
Finished Aug 23 09:57:52 AM UTC 24
Peak memory 231968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704244516 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.704244516
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.3341002528
Short name T736
Test name
Test status
Simulation time 651044197 ps
CPU time 8.43 seconds
Started Aug 23 09:57:53 AM UTC 24
Finished Aug 23 09:58:02 AM UTC 24
Peak memory 237584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341002528 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3341002528
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.3477406793
Short name T743
Test name
Test status
Simulation time 779618872 ps
CPU time 12.36 seconds
Started Aug 23 09:57:55 AM UTC 24
Finished Aug 23 09:58:09 AM UTC 24
Peak memory 237848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477406793 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_to
ken_digest.3477406793
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.2708690253
Short name T735
Test name
Test status
Simulation time 847316379 ps
CPU time 6.94 seconds
Started Aug 23 09:57:54 AM UTC 24
Finished Aug 23 09:58:02 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708690253 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token
_mux.2708690253
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.493372786
Short name T726
Test name
Test status
Simulation time 79195054 ps
CPU time 1.42 seconds
Started Aug 23 09:57:46 AM UTC 24
Finished Aug 23 09:57:49 AM UTC 24
Peak memory 224364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493372786 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.493372786
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.2766794616
Short name T740
Test name
Test status
Simulation time 1109196829 ps
CPU time 14.99 seconds
Started Aug 23 09:57:48 AM UTC 24
Finished Aug 23 09:58:04 AM UTC 24
Peak memory 262644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766794616 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2766794616
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.1216945854
Short name T731
Test name
Test status
Simulation time 65169404 ps
CPU time 7.34 seconds
Started Aug 23 09:57:48 AM UTC 24
Finished Aug 23 09:57:56 AM UTC 24
Peak memory 262644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216945854 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1216945854
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.3769118213
Short name T856
Test name
Test status
Simulation time 42495671718 ps
CPU time 156.44 seconds
Started Aug 23 09:57:58 AM UTC 24
Finished Aug 23 10:00:37 AM UTC 24
Peak memory 291308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3769118213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 40.lc_ctrl_stress_all.3769118213
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.1925123187
Short name T152
Test name
Test status
Simulation time 3199979315 ps
CPU time 90.14 seconds
Started Aug 23 09:57:58 AM UTC 24
Finished Aug 23 09:59:30 AM UTC 24
Peak memory 281200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925123187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_u
nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.1925123187
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1952596088
Short name T725
Test name
Test status
Simulation time 21665196 ps
CPU time 0.78 seconds
Started Aug 23 09:57:46 AM UTC 24
Finished Aug 23 09:57:48 AM UTC 24
Peak memory 218228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952596088 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40
.lc_ctrl_volatile_unlock_smoke.1952596088
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.1561109810
Short name T746
Test name
Test status
Simulation time 20741167 ps
CPU time 1.02 seconds
Started Aug 23 09:58:13 AM UTC 24
Finished Aug 23 09:58:15 AM UTC 24
Peak memory 218576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561109810 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1561109810
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_errors.4145211346
Short name T747
Test name
Test status
Simulation time 4574381400 ps
CPU time 9.69 seconds
Started Aug 23 09:58:04 AM UTC 24
Finished Aug 23 09:58:15 AM UTC 24
Peak memory 237724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145211346 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.4145211346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.3470107011
Short name T749
Test name
Test status
Simulation time 4469858392 ps
CPU time 8.5 seconds
Started Aug 23 09:58:05 AM UTC 24
Finished Aug 23 09:58:15 AM UTC 24
Peak memory 229612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470107011 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3470107011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.3443492571
Short name T742
Test name
Test status
Simulation time 28278856 ps
CPU time 1.64 seconds
Started Aug 23 09:58:04 AM UTC 24
Finished Aug 23 09:58:07 AM UTC 24
Peak memory 231968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443492571 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3443492571
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.1585416524
Short name T750
Test name
Test status
Simulation time 321574257 ps
CPU time 10.3 seconds
Started Aug 23 09:58:06 AM UTC 24
Finished Aug 23 09:58:17 AM UTC 24
Peak memory 237580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585416524 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1585416524
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.758571739
Short name T758
Test name
Test status
Simulation time 776753316 ps
CPU time 17.27 seconds
Started Aug 23 09:58:09 AM UTC 24
Finished Aug 23 09:58:28 AM UTC 24
Peak memory 237256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758571739 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_tok
en_digest.758571739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.3036640889
Short name T755
Test name
Test status
Simulation time 2404591203 ps
CPU time 12.52 seconds
Started Aug 23 09:58:08 AM UTC 24
Finished Aug 23 09:58:21 AM UTC 24
Peak memory 231940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036640889 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token
_mux.3036640889
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.3987702122
Short name T745
Test name
Test status
Simulation time 232528993 ps
CPU time 6.15 seconds
Started Aug 23 09:58:04 AM UTC 24
Finished Aug 23 09:58:11 AM UTC 24
Peak memory 237584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987702122 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3987702122
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.2258675820
Short name T741
Test name
Test status
Simulation time 514353704 ps
CPU time 5.16 seconds
Started Aug 23 09:57:58 AM UTC 24
Finished Aug 23 09:58:04 AM UTC 24
Peak memory 229688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258675820 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2258675820
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.1929139925
Short name T759
Test name
Test status
Simulation time 647396039 ps
CPU time 26.03 seconds
Started Aug 23 09:58:02 AM UTC 24
Finished Aug 23 09:58:29 AM UTC 24
Peak memory 260588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929139925 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1929139925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.2310744579
Short name T748
Test name
Test status
Simulation time 346046362 ps
CPU time 9.75 seconds
Started Aug 23 09:58:04 AM UTC 24
Finished Aug 23 09:58:15 AM UTC 24
Peak memory 260660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310744579 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2310744579
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.1619282035
Short name T864
Test name
Test status
Simulation time 40415209456 ps
CPU time 282.43 seconds
Started Aug 23 09:58:09 AM UTC 24
Finished Aug 23 10:02:55 AM UTC 24
Peak memory 234124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1619282035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 41.lc_ctrl_stress_all.1619282035
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.267554260
Short name T739
Test name
Test status
Simulation time 26160044 ps
CPU time 0.74 seconds
Started Aug 23 09:58:01 AM UTC 24
Finished Aug 23 09:58:03 AM UTC 24
Peak memory 218348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267554260 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.
lc_ctrl_volatile_unlock_smoke.267554260
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.1535867738
Short name T763
Test name
Test status
Simulation time 62181464 ps
CPU time 1 seconds
Started Aug 23 09:58:29 AM UTC 24
Finished Aug 23 09:58:31 AM UTC 24
Peak memory 218524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535867738 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1535867738
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.346472422
Short name T768
Test name
Test status
Simulation time 422409158 ps
CPU time 14.68 seconds
Started Aug 23 09:58:19 AM UTC 24
Finished Aug 23 09:58:35 AM UTC 24
Peak memory 232220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346472422 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.346472422
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.2259898957
Short name T760
Test name
Test status
Simulation time 832660149 ps
CPU time 8.14 seconds
Started Aug 23 09:58:21 AM UTC 24
Finished Aug 23 09:58:31 AM UTC 24
Peak memory 229552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259898957 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2259898957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.1861167649
Short name T754
Test name
Test status
Simulation time 121506403 ps
CPU time 2.11 seconds
Started Aug 23 09:58:18 AM UTC 24
Finished Aug 23 09:58:21 AM UTC 24
Peak memory 235972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861167649 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1861167649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.3042458395
Short name T765
Test name
Test status
Simulation time 3968652606 ps
CPU time 9.99 seconds
Started Aug 23 09:58:21 AM UTC 24
Finished Aug 23 09:58:33 AM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042458395 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3042458395
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.627880342
Short name T766
Test name
Test status
Simulation time 224202868 ps
CPU time 8.9 seconds
Started Aug 23 09:58:24 AM UTC 24
Finished Aug 23 09:58:34 AM UTC 24
Peak memory 231812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627880342 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_tok
en_digest.627880342
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.1544807711
Short name T764
Test name
Test status
Simulation time 543587694 ps
CPU time 8.17 seconds
Started Aug 23 09:58:23 AM UTC 24
Finished Aug 23 09:58:32 AM UTC 24
Peak memory 229908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544807711 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token
_mux.1544807711
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.500870813
Short name T761
Test name
Test status
Simulation time 1552128018 ps
CPU time 8.3 seconds
Started Aug 23 09:58:21 AM UTC 24
Finished Aug 23 09:58:31 AM UTC 24
Peak memory 231960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500870813 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.500870813
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.4015422877
Short name T752
Test name
Test status
Simulation time 181696166 ps
CPU time 2.45 seconds
Started Aug 23 09:58:16 AM UTC 24
Finished Aug 23 09:58:20 AM UTC 24
Peak memory 225604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015422877 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.4015422877
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.2486296574
Short name T771
Test name
Test status
Simulation time 680675822 ps
CPU time 18.8 seconds
Started Aug 23 09:58:16 AM UTC 24
Finished Aug 23 09:58:36 AM UTC 24
Peak memory 262408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486296574 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2486296574
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.2407173691
Short name T753
Test name
Test status
Simulation time 400055985 ps
CPU time 2.63 seconds
Started Aug 23 09:58:16 AM UTC 24
Finished Aug 23 09:58:20 AM UTC 24
Peak memory 234080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407173691 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2407173691
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.1796036629
Short name T843
Test name
Test status
Simulation time 7738960304 ps
CPU time 84.46 seconds
Started Aug 23 09:58:26 AM UTC 24
Finished Aug 23 09:59:53 AM UTC 24
Peak memory 262640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1796036629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 42.lc_ctrl_stress_all.1796036629
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.4180447605
Short name T751
Test name
Test status
Simulation time 145478475 ps
CPU time 0.66 seconds
Started Aug 23 09:58:16 AM UTC 24
Finished Aug 23 09:58:18 AM UTC 24
Peak memory 218284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180447605 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42
.lc_ctrl_volatile_unlock_smoke.4180447605
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.906936956
Short name T710
Test name
Test status
Simulation time 55534650 ps
CPU time 0.79 seconds
Started Aug 23 09:58:38 AM UTC 24
Finished Aug 23 09:58:39 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906936956 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.906936956
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_errors.2305507
Short name T778
Test name
Test status
Simulation time 2512136266 ps
CPU time 14.87 seconds
Started Aug 23 09:58:33 AM UTC 24
Finished Aug 23 09:58:49 AM UTC 24
Peak memory 232020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305507 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2305507
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.409896109
Short name T775
Test name
Test status
Simulation time 2999864791 ps
CPU time 7.49 seconds
Started Aug 23 09:58:36 AM UTC 24
Finished Aug 23 09:58:44 AM UTC 24
Peak memory 229684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409896109 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.409896109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.52457668
Short name T772
Test name
Test status
Simulation time 529652553 ps
CPU time 2.87 seconds
Started Aug 23 09:58:33 AM UTC 24
Finished Aug 23 09:58:37 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52457668 -assert nopostproc +UVM_TESTNAME=lc_ctr
l_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.52457668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.164260102
Short name T780
Test name
Test status
Simulation time 813857694 ps
CPU time 14.67 seconds
Started Aug 23 09:58:36 AM UTC 24
Finished Aug 23 09:58:52 AM UTC 24
Peak memory 237656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164260102 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.164260102
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.3145950137
Short name T776
Test name
Test status
Simulation time 3128745776 ps
CPU time 8.71 seconds
Started Aug 23 09:58:36 AM UTC 24
Finished Aug 23 09:58:46 AM UTC 24
Peak memory 229824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145950137 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_to
ken_digest.3145950137
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.1257307015
Short name T777
Test name
Test status
Simulation time 409446565 ps
CPU time 9.29 seconds
Started Aug 23 09:58:36 AM UTC 24
Finished Aug 23 09:58:46 AM UTC 24
Peak memory 231936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257307015 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token
_mux.1257307015
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.2226754568
Short name T774
Test name
Test status
Simulation time 966564066 ps
CPU time 8.61 seconds
Started Aug 23 09:58:34 AM UTC 24
Finished Aug 23 09:58:44 AM UTC 24
Peak memory 231872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226754568 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2226754568
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.3641514265
Short name T767
Test name
Test status
Simulation time 192368395 ps
CPU time 2.11 seconds
Started Aug 23 09:58:31 AM UTC 24
Finished Aug 23 09:58:34 AM UTC 24
Peak memory 229628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641514265 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3641514265
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.3044120137
Short name T783
Test name
Test status
Simulation time 207464290 ps
CPU time 19.82 seconds
Started Aug 23 09:58:33 AM UTC 24
Finished Aug 23 09:58:54 AM UTC 24
Peak memory 262572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044120137 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3044120137
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.2050190121
Short name T715
Test name
Test status
Simulation time 315150341 ps
CPU time 7.08 seconds
Started Aug 23 09:58:33 AM UTC 24
Finished Aug 23 09:58:41 AM UTC 24
Peak memory 260440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050190121 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2050190121
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.2900540478
Short name T784
Test name
Test status
Simulation time 1778036172 ps
CPU time 16.59 seconds
Started Aug 23 09:58:38 AM UTC 24
Finished Aug 23 09:58:55 AM UTC 24
Peak memory 262828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2900540478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 43.lc_ctrl_stress_all.2900540478
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2553372357
Short name T769
Test name
Test status
Simulation time 46758130 ps
CPU time 0.8 seconds
Started Aug 23 09:58:33 AM UTC 24
Finished Aug 23 09:58:35 AM UTC 24
Peak memory 218228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553372357 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43
.lc_ctrl_volatile_unlock_smoke.2553372357
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.1642740267
Short name T785
Test name
Test status
Simulation time 19639957 ps
CPU time 0.96 seconds
Started Aug 23 09:58:54 AM UTC 24
Finished Aug 23 09:58:57 AM UTC 24
Peak memory 218584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642740267 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1642740267
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_errors.1900662115
Short name T789
Test name
Test status
Simulation time 2323723249 ps
CPU time 12.11 seconds
Started Aug 23 09:58:46 AM UTC 24
Finished Aug 23 09:58:59 AM UTC 24
Peak memory 238044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900662115 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1900662115
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.1553573252
Short name T781
Test name
Test status
Simulation time 166477309 ps
CPU time 4.17 seconds
Started Aug 23 09:58:47 AM UTC 24
Finished Aug 23 09:58:52 AM UTC 24
Peak memory 229500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553573252 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1553573252
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.3258835762
Short name T779
Test name
Test status
Simulation time 99586246 ps
CPU time 3 seconds
Started Aug 23 09:58:46 AM UTC 24
Finished Aug 23 09:58:50 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258835762 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3258835762
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.3142364033
Short name T793
Test name
Test status
Simulation time 5319791140 ps
CPU time 11.59 seconds
Started Aug 23 09:58:50 AM UTC 24
Finished Aug 23 09:59:02 AM UTC 24
Peak memory 231828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142364033 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3142364033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.1013983618
Short name T791
Test name
Test status
Simulation time 354908525 ps
CPU time 9.45 seconds
Started Aug 23 09:58:51 AM UTC 24
Finished Aug 23 09:59:01 AM UTC 24
Peak memory 229764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013983618 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_to
ken_digest.1013983618
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.1661095080
Short name T790
Test name
Test status
Simulation time 323071661 ps
CPU time 9.77 seconds
Started Aug 23 09:58:50 AM UTC 24
Finished Aug 23 09:59:01 AM UTC 24
Peak memory 231960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661095080 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token
_mux.1661095080
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.3344705359
Short name T786
Test name
Test status
Simulation time 267193199 ps
CPU time 8.89 seconds
Started Aug 23 09:58:47 AM UTC 24
Finished Aug 23 09:58:57 AM UTC 24
Peak memory 232200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344705359 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3344705359
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.3290017365
Short name T770
Test name
Test status
Simulation time 15883905 ps
CPU time 1.29 seconds
Started Aug 23 09:58:41 AM UTC 24
Finished Aug 23 09:58:43 AM UTC 24
Peak memory 222316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290017365 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3290017365
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.3424826808
Short name T798
Test name
Test status
Simulation time 1070526478 ps
CPU time 21.77 seconds
Started Aug 23 09:58:44 AM UTC 24
Finished Aug 23 09:59:07 AM UTC 24
Peak memory 260528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424826808 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3424826808
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.3975254026
Short name T782
Test name
Test status
Simulation time 300677107 ps
CPU time 7.59 seconds
Started Aug 23 09:58:44 AM UTC 24
Finished Aug 23 09:58:53 AM UTC 24
Peak memory 262576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975254026 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3975254026
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.1492009200
Short name T820
Test name
Test status
Simulation time 1608631782 ps
CPU time 37.8 seconds
Started Aug 23 09:58:53 AM UTC 24
Finished Aug 23 09:59:32 AM UTC 24
Peak memory 258400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1492009200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 44.lc_ctrl_stress_all.1492009200
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.822129588
Short name T773
Test name
Test status
Simulation time 14073289 ps
CPU time 0.72 seconds
Started Aug 23 09:58:42 AM UTC 24
Finished Aug 23 09:58:44 AM UTC 24
Peak memory 218172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822129588 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.
lc_ctrl_volatile_unlock_smoke.822129588
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.980935631
Short name T799
Test name
Test status
Simulation time 20263161 ps
CPU time 0.86 seconds
Started Aug 23 09:59:06 AM UTC 24
Finished Aug 23 09:59:08 AM UTC 24
Peak memory 217372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980935631 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.980935631
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_errors.2214247231
Short name T797
Test name
Test status
Simulation time 927556279 ps
CPU time 6.51 seconds
Started Aug 23 09:58:59 AM UTC 24
Finished Aug 23 09:59:07 AM UTC 24
Peak memory 231948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214247231 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2214247231
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.2322372991
Short name T795
Test name
Test status
Simulation time 79430913 ps
CPU time 1.45 seconds
Started Aug 23 09:59:02 AM UTC 24
Finished Aug 23 09:59:05 AM UTC 24
Peak memory 227984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322372991 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2322372991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.213946803
Short name T792
Test name
Test status
Simulation time 31809077 ps
CPU time 1.41 seconds
Started Aug 23 09:58:59 AM UTC 24
Finished Aug 23 09:59:02 AM UTC 24
Peak memory 231968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213946803 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.213946803
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.4040760144
Short name T804
Test name
Test status
Simulation time 2257060555 ps
CPU time 8.57 seconds
Started Aug 23 09:59:02 AM UTC 24
Finished Aug 23 09:59:12 AM UTC 24
Peak memory 231940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040760144 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.4040760144
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.3807208752
Short name T803
Test name
Test status
Simulation time 624003508 ps
CPU time 6.08 seconds
Started Aug 23 09:59:04 AM UTC 24
Finished Aug 23 09:59:11 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807208752 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_to
ken_digest.3807208752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.1224415757
Short name T805
Test name
Test status
Simulation time 1072652846 ps
CPU time 9.04 seconds
Started Aug 23 09:59:02 AM UTC 24
Finished Aug 23 09:59:12 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224415757 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token
_mux.1224415757
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.1289391801
Short name T800
Test name
Test status
Simulation time 458428027 ps
CPU time 6.31 seconds
Started Aug 23 09:59:01 AM UTC 24
Finished Aug 23 09:59:08 AM UTC 24
Peak memory 231944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289391801 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1289391801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.2774952756
Short name T787
Test name
Test status
Simulation time 135750954 ps
CPU time 2.77 seconds
Started Aug 23 09:58:55 AM UTC 24
Finished Aug 23 09:58:58 AM UTC 24
Peak memory 229548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774952756 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2774952756
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.1421964630
Short name T815
Test name
Test status
Simulation time 323445167 ps
CPU time 25.49 seconds
Started Aug 23 09:58:58 AM UTC 24
Finished Aug 23 09:59:25 AM UTC 24
Peak memory 260460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421964630 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1421964630
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.2225190267
Short name T794
Test name
Test status
Simulation time 80764061 ps
CPU time 3.57 seconds
Started Aug 23 09:58:58 AM UTC 24
Finished Aug 23 09:59:03 AM UTC 24
Peak memory 234264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225190267 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2225190267
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.1034191260
Short name T859
Test name
Test status
Simulation time 11514544124 ps
CPU time 115.39 seconds
Started Aug 23 09:59:04 AM UTC 24
Finished Aug 23 10:01:01 AM UTC 24
Peak memory 289264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1034191260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 45.lc_ctrl_stress_all.1034191260
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.984412989
Short name T832
Test name
Test status
Simulation time 5985483556 ps
CPU time 35.36 seconds
Started Aug 23 09:59:06 AM UTC 24
Finished Aug 23 09:59:43 AM UTC 24
Peak memory 262684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984412989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S
EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_un
lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.984412989
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3961621811
Short name T788
Test name
Test status
Simulation time 23215541 ps
CPU time 0.81 seconds
Started Aug 23 09:58:57 AM UTC 24
Finished Aug 23 09:58:59 AM UTC 24
Peak memory 218552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961621811 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45
.lc_ctrl_volatile_unlock_smoke.3961621811
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.804917051
Short name T811
Test name
Test status
Simulation time 40183989 ps
CPU time 0.71 seconds
Started Aug 23 09:59:19 AM UTC 24
Finished Aug 23 09:59:20 AM UTC 24
Peak memory 217372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804917051 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.804917051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.2213390136
Short name T810
Test name
Test status
Simulation time 2068978238 ps
CPU time 9.02 seconds
Started Aug 23 09:59:10 AM UTC 24
Finished Aug 23 09:59:20 AM UTC 24
Peak memory 237588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213390136 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2213390136
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.4088387459
Short name T807
Test name
Test status
Simulation time 171264560 ps
CPU time 2.42 seconds
Started Aug 23 09:59:12 AM UTC 24
Finished Aug 23 09:59:15 AM UTC 24
Peak memory 229468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088387459 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.4088387459
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.4155519417
Short name T806
Test name
Test status
Simulation time 45615700 ps
CPU time 2.25 seconds
Started Aug 23 09:59:09 AM UTC 24
Finished Aug 23 09:59:13 AM UTC 24
Peak memory 232204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155519417 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.4155519417
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.1450627027
Short name T818
Test name
Test status
Simulation time 386768906 ps
CPU time 13.77 seconds
Started Aug 23 09:59:13 AM UTC 24
Finished Aug 23 09:59:28 AM UTC 24
Peak memory 231400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450627027 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1450627027
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.3945843176
Short name T812
Test name
Test status
Simulation time 249162525 ps
CPU time 7.39 seconds
Started Aug 23 09:59:13 AM UTC 24
Finished Aug 23 09:59:22 AM UTC 24
Peak memory 237596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945843176 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_to
ken_digest.3945843176
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.1938409456
Short name T813
Test name
Test status
Simulation time 1025605830 ps
CPU time 8.29 seconds
Started Aug 23 09:59:13 AM UTC 24
Finished Aug 23 09:59:23 AM UTC 24
Peak memory 231716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938409456 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token
_mux.1938409456
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.2421396599
Short name T808
Test name
Test status
Simulation time 203762928 ps
CPU time 5.35 seconds
Started Aug 23 09:59:10 AM UTC 24
Finished Aug 23 09:59:17 AM UTC 24
Peak memory 231948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421396599 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2421396599
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.1742313260
Short name T802
Test name
Test status
Simulation time 20412032 ps
CPU time 1.01 seconds
Started Aug 23 09:59:07 AM UTC 24
Finished Aug 23 09:59:09 AM UTC 24
Peak memory 228440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742313260 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1742313260
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.1807783166
Short name T821
Test name
Test status
Simulation time 504743975 ps
CPU time 22.48 seconds
Started Aug 23 09:59:09 AM UTC 24
Finished Aug 23 09:59:33 AM UTC 24
Peak memory 262576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807783166 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1807783166
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.244261034
Short name T809
Test name
Test status
Simulation time 84012485 ps
CPU time 7.94 seconds
Started Aug 23 09:59:09 AM UTC 24
Finished Aug 23 09:59:18 AM UTC 24
Peak memory 262556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244261034 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.244261034
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.3725985793
Short name T861
Test name
Test status
Simulation time 4941810118 ps
CPU time 151.18 seconds
Started Aug 23 09:59:15 AM UTC 24
Finished Aug 23 10:01:49 AM UTC 24
Peak memory 281092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3725985793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 46.lc_ctrl_stress_all.3725985793
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3808997603
Short name T801
Test name
Test status
Simulation time 50690071 ps
CPU time 0.7 seconds
Started Aug 23 09:59:07 AM UTC 24
Finished Aug 23 09:59:09 AM UTC 24
Peak memory 218644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808997603 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46
.lc_ctrl_volatile_unlock_smoke.3808997603
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.2897724890
Short name T823
Test name
Test status
Simulation time 206564627 ps
CPU time 0.72 seconds
Started Aug 23 09:59:34 AM UTC 24
Finished Aug 23 09:59:35 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897724890 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2897724890
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.1258018455
Short name T824
Test name
Test status
Simulation time 466488485 ps
CPU time 8.2 seconds
Started Aug 23 09:59:26 AM UTC 24
Finished Aug 23 09:59:36 AM UTC 24
Peak memory 232204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258018455 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1258018455
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.3747606181
Short name T827
Test name
Test status
Simulation time 918229844 ps
CPU time 10.46 seconds
Started Aug 23 09:59:26 AM UTC 24
Finished Aug 23 09:59:38 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747606181 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3747606181
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.2719596588
Short name T817
Test name
Test status
Simulation time 59185955 ps
CPU time 2.59 seconds
Started Aug 23 09:59:24 AM UTC 24
Finished Aug 23 09:59:27 AM UTC 24
Peak memory 231952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719596588 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2719596588
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.225857408
Short name T829
Test name
Test status
Simulation time 844433389 ps
CPU time 9.07 seconds
Started Aug 23 09:59:29 AM UTC 24
Finished Aug 23 09:59:39 AM UTC 24
Peak memory 237652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225857408 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.225857408
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.445717671
Short name T830
Test name
Test status
Simulation time 318826463 ps
CPU time 7.28 seconds
Started Aug 23 09:59:31 AM UTC 24
Finished Aug 23 09:59:39 AM UTC 24
Peak memory 237236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445717671 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_tok
en_digest.445717671
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.2145955953
Short name T825
Test name
Test status
Simulation time 306694155 ps
CPU time 7.69 seconds
Started Aug 23 09:59:29 AM UTC 24
Finished Aug 23 09:59:37 AM UTC 24
Peak memory 237864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145955953 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token
_mux.2145955953
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.952703724
Short name T822
Test name
Test status
Simulation time 413922131 ps
CPU time 6.95 seconds
Started Aug 23 09:59:26 AM UTC 24
Finished Aug 23 09:59:34 AM UTC 24
Peak memory 231960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952703724 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.952703724
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.1455508429
Short name T816
Test name
Test status
Simulation time 545207581 ps
CPU time 3.57 seconds
Started Aug 23 09:59:21 AM UTC 24
Finished Aug 23 09:59:26 AM UTC 24
Peak memory 225452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455508429 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1455508429
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.1856287804
Short name T837
Test name
Test status
Simulation time 232281503 ps
CPU time 25.87 seconds
Started Aug 23 09:59:22 AM UTC 24
Finished Aug 23 09:59:49 AM UTC 24
Peak memory 262836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856287804 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1856287804
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.2235572942
Short name T819
Test name
Test status
Simulation time 63678629 ps
CPU time 6.01 seconds
Started Aug 23 09:59:24 AM UTC 24
Finished Aug 23 09:59:31 AM UTC 24
Peak memory 262560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235572942 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2235572942
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.687937537
Short name T858
Test name
Test status
Simulation time 5175835638 ps
CPU time 86.02 seconds
Started Aug 23 09:59:31 AM UTC 24
Finished Aug 23 10:00:59 AM UTC 24
Peak memory 291172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=687937537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 47.lc_ctrl_stress_all.687937537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2871638389
Short name T814
Test name
Test status
Simulation time 48343495 ps
CPU time 0.82 seconds
Started Aug 23 09:59:21 AM UTC 24
Finished Aug 23 09:59:23 AM UTC 24
Peak memory 222376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871638389 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47
.lc_ctrl_volatile_unlock_smoke.2871638389
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.1833843408
Short name T841
Test name
Test status
Simulation time 72579695 ps
CPU time 1.04 seconds
Started Aug 23 09:59:50 AM UTC 24
Finished Aug 23 09:59:52 AM UTC 24
Peak memory 218464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833843408 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1833843408
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.3638454493
Short name T838
Test name
Test status
Simulation time 869593959 ps
CPU time 10.56 seconds
Started Aug 23 09:59:39 AM UTC 24
Finished Aug 23 09:59:51 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638454493 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3638454493
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.4106296691
Short name T833
Test name
Test status
Simulation time 162606053 ps
CPU time 1.4 seconds
Started Aug 23 09:59:40 AM UTC 24
Finished Aug 23 09:59:43 AM UTC 24
Peak memory 227984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106296691 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.4106296691
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.3227177521
Short name T831
Test name
Test status
Simulation time 40470720 ps
CPU time 2 seconds
Started Aug 23 09:59:39 AM UTC 24
Finished Aug 23 09:59:42 AM UTC 24
Peak memory 227876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227177521 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3227177521
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.3378484327
Short name T839
Test name
Test status
Simulation time 1314901399 ps
CPU time 9.17 seconds
Started Aug 23 09:59:40 AM UTC 24
Finished Aug 23 09:59:51 AM UTC 24
Peak memory 237576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378484327 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3378484327
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.1466909273
Short name T844
Test name
Test status
Simulation time 264184443 ps
CPU time 7.87 seconds
Started Aug 23 09:59:44 AM UTC 24
Finished Aug 23 09:59:53 AM UTC 24
Peak memory 237592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466909273 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_to
ken_digest.1466909273
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.2935580952
Short name T835
Test name
Test status
Simulation time 217402488 ps
CPU time 5.49 seconds
Started Aug 23 09:59:43 AM UTC 24
Finished Aug 23 09:59:49 AM UTC 24
Peak memory 236500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935580952 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token
_mux.2935580952
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.1580641605
Short name T836
Test name
Test status
Simulation time 261707282 ps
CPU time 9.16 seconds
Started Aug 23 09:59:39 AM UTC 24
Finished Aug 23 09:59:49 AM UTC 24
Peak memory 237656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580641605 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1580641605
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.1698779119
Short name T826
Test name
Test status
Simulation time 53899264 ps
CPU time 1.9 seconds
Started Aug 23 09:59:35 AM UTC 24
Finished Aug 23 09:59:38 AM UTC 24
Peak memory 224364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698779119 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1698779119
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.3802686610
Short name T851
Test name
Test status
Simulation time 1350264783 ps
CPU time 29.13 seconds
Started Aug 23 09:59:36 AM UTC 24
Finished Aug 23 10:00:06 AM UTC 24
Peak memory 262896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802686610 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3802686610
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.4058109787
Short name T834
Test name
Test status
Simulation time 136597520 ps
CPU time 7.96 seconds
Started Aug 23 09:59:39 AM UTC 24
Finished Aug 23 09:59:48 AM UTC 24
Peak memory 261904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058109787 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.4058109787
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.4057927550
Short name T863
Test name
Test status
Simulation time 9567218111 ps
CPU time 173.31 seconds
Started Aug 23 09:59:44 AM UTC 24
Finished Aug 23 10:02:40 AM UTC 24
Peak memory 289280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4057927550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 48.lc_ctrl_stress_all.4057927550
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1819488456
Short name T855
Test name
Test status
Simulation time 4081355762 ps
CPU time 39.26 seconds
Started Aug 23 09:59:48 AM UTC 24
Finished Aug 23 10:00:29 AM UTC 24
Peak memory 283504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819488456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_u
nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.1819488456
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2107365458
Short name T828
Test name
Test status
Simulation time 144245823 ps
CPU time 0.96 seconds
Started Aug 23 09:59:36 AM UTC 24
Finished Aug 23 09:59:38 AM UTC 24
Peak memory 228684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107365458 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48
.lc_ctrl_volatile_unlock_smoke.2107365458
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.4150658452
Short name T852
Test name
Test status
Simulation time 60582527 ps
CPU time 0.82 seconds
Started Aug 23 10:00:01 AM UTC 24
Finished Aug 23 10:00:08 AM UTC 24
Peak memory 218536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150658452 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.4150658452
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.2523232271
Short name T849
Test name
Test status
Simulation time 1341652972 ps
CPU time 9.71 seconds
Started Aug 23 09:59:53 AM UTC 24
Finished Aug 23 10:00:04 AM UTC 24
Peak memory 232280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523232271 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2523232271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.3376171114
Short name T796
Test name
Test status
Simulation time 1260881576 ps
CPU time 9.43 seconds
Started Aug 23 09:59:53 AM UTC 24
Finished Aug 23 10:00:03 AM UTC 24
Peak memory 229532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376171114 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3376171114
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.233137844
Short name T845
Test name
Test status
Simulation time 57107000 ps
CPU time 2.74 seconds
Started Aug 23 09:59:51 AM UTC 24
Finished Aug 23 09:59:55 AM UTC 24
Peak memory 236308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233137844 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.233137844
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.1499327018
Short name T853
Test name
Test status
Simulation time 1375803950 ps
CPU time 12.76 seconds
Started Aug 23 09:59:54 AM UTC 24
Finished Aug 23 10:00:08 AM UTC 24
Peak memory 237912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499327018 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1499327018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.3770670895
Short name T850
Test name
Test status
Simulation time 1127310222 ps
CPU time 8.16 seconds
Started Aug 23 09:59:56 AM UTC 24
Finished Aug 23 10:00:05 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770670895 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_to
ken_digest.3770670895
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.1047869671
Short name T848
Test name
Test status
Simulation time 805800603 ps
CPU time 6.72 seconds
Started Aug 23 09:59:54 AM UTC 24
Finished Aug 23 10:00:02 AM UTC 24
Peak memory 237588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047869671 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token
_mux.1047869671
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.462888655
Short name T847
Test name
Test status
Simulation time 285840325 ps
CPU time 6.37 seconds
Started Aug 23 09:59:53 AM UTC 24
Finished Aug 23 10:00:00 AM UTC 24
Peak memory 231884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462888655 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.462888655
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.2845564304
Short name T842
Test name
Test status
Simulation time 38447928 ps
CPU time 1.62 seconds
Started Aug 23 09:59:50 AM UTC 24
Finished Aug 23 09:59:52 AM UTC 24
Peak memory 224360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845564304 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2845564304
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.2033043902
Short name T854
Test name
Test status
Simulation time 1936154056 ps
CPU time 23.37 seconds
Started Aug 23 09:59:51 AM UTC 24
Finished Aug 23 10:00:16 AM UTC 24
Peak memory 262496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033043902 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2033043902
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.637567465
Short name T846
Test name
Test status
Simulation time 53857894 ps
CPU time 2.84 seconds
Started Aug 23 09:59:51 AM UTC 24
Finished Aug 23 09:59:55 AM UTC 24
Peak memory 234660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637567465 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.637567465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.3454007054
Short name T857
Test name
Test status
Simulation time 1433922324 ps
CPU time 39.27 seconds
Started Aug 23 09:59:57 AM UTC 24
Finished Aug 23 10:00:37 AM UTC 24
Peak memory 232148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3454007054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 49.lc_ctrl_stress_all.3454007054
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2207160430
Short name T840
Test name
Test status
Simulation time 45051492 ps
CPU time 0.92 seconds
Started Aug 23 09:59:50 AM UTC 24
Finished Aug 23 09:59:52 AM UTC 24
Peak memory 222376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207160430 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49
.lc_ctrl_volatile_unlock_smoke.2207160430
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.3111780142
Short name T264
Test name
Test status
Simulation time 42348457 ps
CPU time 0.86 seconds
Started Aug 23 09:45:54 AM UTC 24
Finished Aug 23 09:45:55 AM UTC 24
Peak memory 218760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111780142 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3111780142
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.1500842934
Short name T256
Test name
Test status
Simulation time 11921140 ps
CPU time 0.72 seconds
Started Aug 23 09:45:33 AM UTC 24
Finished Aug 23 09:45:34 AM UTC 24
Peak memory 217076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500842934 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1500842934
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.3588370745
Short name T53
Test name
Test status
Simulation time 542975177 ps
CPU time 6.91 seconds
Started Aug 23 09:45:25 AM UTC 24
Finished Aug 23 09:45:33 AM UTC 24
Peak memory 229828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588370745 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3588370745
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.2167355379
Short name T258
Test name
Test status
Simulation time 231638073 ps
CPU time 2.88 seconds
Started Aug 23 09:45:38 AM UTC 24
Finished Aug 23 09:45:42 AM UTC 24
Peak memory 229620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167355379 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2167355379
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.1390262388
Short name T279
Test name
Test status
Simulation time 2025524458 ps
CPU time 50.94 seconds
Started Aug 23 09:45:37 AM UTC 24
Finished Aug 23 09:46:29 AM UTC 24
Peak memory 232148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390262388
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jt
ag_errors.1390262388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.417376359
Short name T259
Test name
Test status
Simulation time 826461713 ps
CPU time 3.9 seconds
Started Aug 23 09:45:38 AM UTC 24
Finished Aug 23 09:45:43 AM UTC 24
Peak memory 229576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417376359 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.417376359
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.1546707289
Short name T263
Test name
Test status
Simulation time 952391675 ps
CPU time 14.89 seconds
Started Aug 23 09:45:37 AM UTC 24
Finished Aug 23 09:45:53 AM UTC 24
Peak memory 231960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546707289
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_jtag_prog_failure.1546707289
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.460395857
Short name T268
Test name
Test status
Simulation time 931930900 ps
CPU time 21.59 seconds
Started Aug 23 09:45:42 AM UTC 24
Finished Aug 23 09:46:05 AM UTC 24
Peak memory 229560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460395857 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_c
trl_jtag_regwen_during_op.460395857
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.681766748
Short name T257
Test name
Test status
Simulation time 270214735 ps
CPU time 1.51 seconds
Started Aug 23 09:45:34 AM UTC 24
Finished Aug 23 09:45:36 AM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681766748 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_sm
oke.681766748
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.2043091431
Short name T273
Test name
Test status
Simulation time 913701206 ps
CPU time 38.6 seconds
Started Aug 23 09:45:35 AM UTC 24
Finished Aug 23 09:46:15 AM UTC 24
Peak memory 262084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043091431
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_jtag_state_failure.2043091431
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.3430250241
Short name T261
Test name
Test status
Simulation time 452363206 ps
CPU time 12.22 seconds
Started Aug 23 09:45:35 AM UTC 24
Finished Aug 23 09:45:48 AM UTC 24
Peak memory 262512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430250241
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_
ctrl_jtag_state_post_trans.3430250241
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.1157451519
Short name T252
Test name
Test status
Simulation time 205056487 ps
CPU time 2.3 seconds
Started Aug 23 09:45:25 AM UTC 24
Finished Aug 23 09:45:29 AM UTC 24
Peak memory 231940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157451519 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1157451519
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.1409024953
Short name T188
Test name
Test status
Simulation time 825171706 ps
CPU time 4.88 seconds
Started Aug 23 09:45:30 AM UTC 24
Finished Aug 23 09:45:36 AM UTC 24
Peak memory 225464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409024953 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1409024953
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.2744839874
Short name T262
Test name
Test status
Simulation time 266287717 ps
CPU time 8.19 seconds
Started Aug 23 09:45:43 AM UTC 24
Finished Aug 23 09:45:52 AM UTC 24
Peak memory 232140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744839874 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2744839874
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.3151461979
Short name T271
Test name
Test status
Simulation time 5137376406 ps
CPU time 20.81 seconds
Started Aug 23 09:45:48 AM UTC 24
Finished Aug 23 09:46:10 AM UTC 24
Peak memory 237904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151461979 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_tok
en_digest.3151461979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.2068567502
Short name T265
Test name
Test status
Simulation time 1657155705 ps
CPU time 12.37 seconds
Started Aug 23 09:45:44 AM UTC 24
Finished Aug 23 09:45:58 AM UTC 24
Peak memory 237652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068567502 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_
mux.2068567502
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.1053723674
Short name T218
Test name
Test status
Simulation time 182101304 ps
CPU time 6.43 seconds
Started Aug 23 09:45:29 AM UTC 24
Finished Aug 23 09:45:37 AM UTC 24
Peak memory 237600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053723674 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1053723674
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.3568393236
Short name T86
Test name
Test status
Simulation time 71793788 ps
CPU time 0.95 seconds
Started Aug 23 09:45:22 AM UTC 24
Finished Aug 23 09:45:24 AM UTC 24
Peak memory 222316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568393236 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3568393236
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1272398819
Short name T260
Test name
Test status
Simulation time 842788589 ps
CPU time 18.2 seconds
Started Aug 23 09:45:24 AM UTC 24
Finished Aug 23 09:45:43 AM UTC 24
Peak memory 262580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272398819 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1272398819
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.1158177879
Short name T255
Test name
Test status
Simulation time 101289784 ps
CPU time 7.56 seconds
Started Aug 23 09:45:25 AM UTC 24
Finished Aug 23 09:45:34 AM UTC 24
Peak memory 262508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158177879 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1158177879
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.270198230
Short name T70
Test name
Test status
Simulation time 13558257825 ps
CPU time 97.84 seconds
Started Aug 23 09:45:49 AM UTC 24
Finished Aug 23 09:47:29 AM UTC 24
Peak memory 285084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=270198230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 5.lc_ctrl_stress_all.270198230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1026069992
Short name T101
Test name
Test status
Simulation time 6239114298 ps
CPU time 32.52 seconds
Started Aug 23 09:45:54 AM UTC 24
Finished Aug 23 09:46:27 AM UTC 24
Peak memory 281460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026069992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_u
nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.1026069992
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.134180700
Short name T249
Test name
Test status
Simulation time 15177944 ps
CPU time 0.79 seconds
Started Aug 23 09:45:22 AM UTC 24
Finished Aug 23 09:45:24 AM UTC 24
Peak memory 218552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134180700 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.l
c_ctrl_volatile_unlock_smoke.134180700
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.3509412902
Short name T280
Test name
Test status
Simulation time 54342825 ps
CPU time 0.8 seconds
Started Aug 23 09:46:27 AM UTC 24
Finished Aug 23 09:46:29 AM UTC 24
Peak memory 218644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509412902 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3509412902
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.4084932315
Short name T81
Test name
Test status
Simulation time 21466807 ps
CPU time 0.71 seconds
Started Aug 23 09:46:06 AM UTC 24
Finished Aug 23 09:46:08 AM UTC 24
Peak memory 216956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084932315 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.4084932315
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.3046521454
Short name T274
Test name
Test status
Simulation time 319288663 ps
CPU time 13.07 seconds
Started Aug 23 09:46:03 AM UTC 24
Finished Aug 23 09:46:17 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046521454 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3046521454
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.1012747408
Short name T28
Test name
Test status
Simulation time 590967784 ps
CPU time 4.1 seconds
Started Aug 23 09:46:16 AM UTC 24
Finished Aug 23 09:46:21 AM UTC 24
Peak memory 229548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012747408 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1012747408
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.263645401
Short name T275
Test name
Test status
Simulation time 210757981 ps
CPU time 2.09 seconds
Started Aug 23 09:46:17 AM UTC 24
Finished Aug 23 09:46:20 AM UTC 24
Peak memory 229868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263645401 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.263645401
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2156025750
Short name T278
Test name
Test status
Simulation time 1702460927 ps
CPU time 10.9 seconds
Started Aug 23 09:46:15 AM UTC 24
Finished Aug 23 09:46:27 AM UTC 24
Peak memory 231888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156025750
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_jtag_prog_failure.2156025750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2528965967
Short name T289
Test name
Test status
Simulation time 3168662005 ps
CPU time 29.41 seconds
Started Aug 23 09:46:17 AM UTC 24
Finished Aug 23 09:46:48 AM UTC 24
Peak memory 229628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528965967
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_
ctrl_jtag_regwen_during_op.2528965967
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.822446383
Short name T272
Test name
Test status
Simulation time 686312650 ps
CPU time 4.93 seconds
Started Aug 23 09:46:08 AM UTC 24
Finished Aug 23 09:46:15 AM UTC 24
Peak memory 229928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822446383 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_sm
oke.822446383
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.3551153469
Short name T295
Test name
Test status
Simulation time 8850025798 ps
CPU time 46.35 seconds
Started Aug 23 09:46:11 AM UTC 24
Finished Aug 23 09:46:59 AM UTC 24
Peak memory 262564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551153469
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_jtag_state_failure.3551153469
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.2202391310
Short name T277
Test name
Test status
Simulation time 1618795427 ps
CPU time 12.21 seconds
Started Aug 23 09:46:13 AM UTC 24
Finished Aug 23 09:46:26 AM UTC 24
Peak memory 256688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202391310
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_
ctrl_jtag_state_post_trans.2202391310
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.2157152233
Short name T270
Test name
Test status
Simulation time 59518006 ps
CPU time 1.92 seconds
Started Aug 23 09:46:02 AM UTC 24
Finished Aug 23 09:46:05 AM UTC 24
Peak memory 229912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157152233 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2157152233
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.3250574131
Short name T189
Test name
Test status
Simulation time 425581898 ps
CPU time 8.88 seconds
Started Aug 23 09:46:06 AM UTC 24
Finished Aug 23 09:46:16 AM UTC 24
Peak memory 229892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250574131 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3250574131
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.702739538
Short name T57
Test name
Test status
Simulation time 638776075 ps
CPU time 7.8 seconds
Started Aug 23 09:46:18 AM UTC 24
Finished Aug 23 09:46:27 AM UTC 24
Peak memory 227088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702739538 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.702739538
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.3725555030
Short name T286
Test name
Test status
Simulation time 853883951 ps
CPU time 15.97 seconds
Started Aug 23 09:46:21 AM UTC 24
Finished Aug 23 09:46:39 AM UTC 24
Peak memory 231564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725555030 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_tok
en_digest.3725555030
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.31317981
Short name T283
Test name
Test status
Simulation time 810758941 ps
CPU time 10.97 seconds
Started Aug 23 09:46:21 AM UTC 24
Finished Aug 23 09:46:34 AM UTC 24
Peak memory 237248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31317981 -assert nopost
proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.31317981
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.286104098
Short name T219
Test name
Test status
Simulation time 996513851 ps
CPU time 9.49 seconds
Started Aug 23 09:46:05 AM UTC 24
Finished Aug 23 09:46:16 AM UTC 24
Peak memory 237672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286104098 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.286104098
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.1347219183
Short name T87
Test name
Test status
Simulation time 189711556 ps
CPU time 4.81 seconds
Started Aug 23 09:45:56 AM UTC 24
Finished Aug 23 09:46:02 AM UTC 24
Peak memory 229964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347219183 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1347219183
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.98078744
Short name T276
Test name
Test status
Simulation time 550558939 ps
CPU time 21.13 seconds
Started Aug 23 09:46:01 AM UTC 24
Finished Aug 23 09:46:23 AM UTC 24
Peak memory 263020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98078744 -assert nopostproc +UVM_TESTNAME=lc_ctr
l_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.98078744
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.572868716
Short name T269
Test name
Test status
Simulation time 92038371 ps
CPU time 2.95 seconds
Started Aug 23 09:46:01 AM UTC 24
Finished Aug 23 09:46:05 AM UTC 24
Peak memory 234336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572868716 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.572868716
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.1669009059
Short name T303
Test name
Test status
Simulation time 4552523429 ps
CPU time 44.16 seconds
Started Aug 23 09:46:24 AM UTC 24
Finished Aug 23 09:47:10 AM UTC 24
Peak memory 258888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1669009059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 6.lc_ctrl_stress_all.1669009059
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.500989267
Short name T267
Test name
Test status
Simulation time 11453845 ps
CPU time 0.68 seconds
Started Aug 23 09:45:59 AM UTC 24
Finished Aug 23 09:46:00 AM UTC 24
Peak memory 218704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500989267 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.l
c_ctrl_volatile_unlock_smoke.500989267
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.936671940
Short name T296
Test name
Test status
Simulation time 41288763 ps
CPU time 0.72 seconds
Started Aug 23 09:47:00 AM UTC 24
Finished Aug 23 09:47:02 AM UTC 24
Peak memory 216492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936671940 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.936671940
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1358963300
Short name T214
Test name
Test status
Simulation time 20627156 ps
CPU time 0.82 seconds
Started Aug 23 09:46:37 AM UTC 24
Finished Aug 23 09:46:39 AM UTC 24
Peak memory 217076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358963300 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1358963300
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.1105103840
Short name T266
Test name
Test status
Simulation time 7426030335 ps
CPU time 14.47 seconds
Started Aug 23 09:46:33 AM UTC 24
Finished Aug 23 09:46:48 AM UTC 24
Peak memory 231940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105103840 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1105103840
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.2444029624
Short name T29
Test name
Test status
Simulation time 246117434 ps
CPU time 2.91 seconds
Started Aug 23 09:46:47 AM UTC 24
Finished Aug 23 09:46:51 AM UTC 24
Peak memory 229880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444029624 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2444029624
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3185087464
Short name T310
Test name
Test status
Simulation time 1343179303 ps
CPU time 36.38 seconds
Started Aug 23 09:46:46 AM UTC 24
Finished Aug 23 09:47:23 AM UTC 24
Peak memory 237204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185087464
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jt
ag_errors.3185087464
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.3745186106
Short name T291
Test name
Test status
Simulation time 480282596 ps
CPU time 3.36 seconds
Started Aug 23 09:46:49 AM UTC 24
Finished Aug 23 09:46:53 AM UTC 24
Peak memory 229580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745186106 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_prior
ity.3745186106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.2284870527
Short name T290
Test name
Test status
Simulation time 1050441428 ps
CPU time 5.59 seconds
Started Aug 23 09:46:45 AM UTC 24
Finished Aug 23 09:46:52 AM UTC 24
Peak memory 235904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284870527
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_jtag_prog_failure.2284870527
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1536462368
Short name T305
Test name
Test status
Simulation time 1023186615 ps
CPU time 23.18 seconds
Started Aug 23 09:46:49 AM UTC 24
Finished Aug 23 09:47:13 AM UTC 24
Peak memory 229484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536462368
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_
ctrl_jtag_regwen_during_op.1536462368
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.3988463282
Short name T287
Test name
Test status
Simulation time 636245901 ps
CPU time 4.61 seconds
Started Aug 23 09:46:39 AM UTC 24
Finished Aug 23 09:46:45 AM UTC 24
Peak memory 229560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988463282
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_s
moke.3988463282
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.10699935
Short name T307
Test name
Test status
Simulation time 1263669369 ps
CPU time 37.79 seconds
Started Aug 23 09:46:39 AM UTC 24
Finished Aug 23 09:47:18 AM UTC 24
Peak memory 280860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10699935 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_failure.10699935
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.3971316096
Short name T293
Test name
Test status
Simulation time 668478783 ps
CPU time 12.6 seconds
Started Aug 23 09:46:45 AM UTC 24
Finished Aug 23 09:46:59 AM UTC 24
Peak memory 262460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971316096
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_
ctrl_jtag_state_post_trans.3971316096
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.2974082950
Short name T284
Test name
Test status
Simulation time 359244153 ps
CPU time 2.49 seconds
Started Aug 23 09:46:31 AM UTC 24
Finished Aug 23 09:46:34 AM UTC 24
Peak memory 236044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974082950 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2974082950
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.3535705723
Short name T190
Test name
Test status
Simulation time 242028925 ps
CPU time 8.33 seconds
Started Aug 23 09:46:35 AM UTC 24
Finished Aug 23 09:46:44 AM UTC 24
Peak memory 225536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535705723 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3535705723
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.2852602806
Short name T294
Test name
Test status
Simulation time 480347115 ps
CPU time 7.22 seconds
Started Aug 23 09:46:51 AM UTC 24
Finished Aug 23 09:46:59 AM UTC 24
Peak memory 232232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852602806 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2852602806
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.3837961664
Short name T300
Test name
Test status
Simulation time 1002964540 ps
CPU time 10.22 seconds
Started Aug 23 09:46:54 AM UTC 24
Finished Aug 23 09:47:05 AM UTC 24
Peak memory 237512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837961664 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_tok
en_digest.3837961664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.680486817
Short name T298
Test name
Test status
Simulation time 1121071782 ps
CPU time 9.76 seconds
Started Aug 23 09:46:53 AM UTC 24
Finished Aug 23 09:47:04 AM UTC 24
Peak memory 232272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680486817 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.680486817
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.1670794026
Short name T288
Test name
Test status
Simulation time 407129443 ps
CPU time 8.82 seconds
Started Aug 23 09:46:35 AM UTC 24
Finished Aug 23 09:46:45 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670794026 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1670794026
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.2932156352
Short name T282
Test name
Test status
Simulation time 162402249 ps
CPU time 2.62 seconds
Started Aug 23 09:46:29 AM UTC 24
Finished Aug 23 09:46:32 AM UTC 24
Peak memory 225848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932156352 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2932156352
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3796858006
Short name T292
Test name
Test status
Simulation time 738158459 ps
CPU time 24.94 seconds
Started Aug 23 09:46:30 AM UTC 24
Finished Aug 23 09:46:56 AM UTC 24
Peak memory 260788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796858006 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3796858006
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3043626787
Short name T285
Test name
Test status
Simulation time 118966738 ps
CPU time 6 seconds
Started Aug 23 09:46:30 AM UTC 24
Finished Aug 23 09:46:37 AM UTC 24
Peak memory 256308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043626787 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3043626787
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.1793269577
Short name T382
Test name
Test status
Simulation time 5031955732 ps
CPU time 168.26 seconds
Started Aug 23 09:46:57 AM UTC 24
Finished Aug 23 09:49:48 AM UTC 24
Peak memory 295812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1793269577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 7.lc_ctrl_stress_all.1793269577
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.258776027
Short name T281
Test name
Test status
Simulation time 34664026 ps
CPU time 0.87 seconds
Started Aug 23 09:46:29 AM UTC 24
Finished Aug 23 09:46:30 AM UTC 24
Peak memory 222376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258776027 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.l
c_ctrl_volatile_unlock_smoke.258776027
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.64277313
Short name T315
Test name
Test status
Simulation time 186919533 ps
CPU time 0.85 seconds
Started Aug 23 09:47:31 AM UTC 24
Finished Aug 23 09:47:33 AM UTC 24
Peak memory 218644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64277313 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.64277313
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.394670401
Short name T58
Test name
Test status
Simulation time 1033845779 ps
CPU time 11.9 seconds
Started Aug 23 09:47:06 AM UTC 24
Finished Aug 23 09:47:19 AM UTC 24
Peak memory 231944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394670401 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.394670401
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.1736677190
Short name T30
Test name
Test status
Simulation time 587313596 ps
CPU time 12.41 seconds
Started Aug 23 09:47:20 AM UTC 24
Finished Aug 23 09:47:33 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736677190 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1736677190
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.3626946521
Short name T333
Test name
Test status
Simulation time 11577524098 ps
CPU time 48.86 seconds
Started Aug 23 09:47:20 AM UTC 24
Finished Aug 23 09:48:10 AM UTC 24
Peak memory 232144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626946521
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jt
ag_errors.3626946521
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.3009147407
Short name T309
Test name
Test status
Simulation time 384466859 ps
CPU time 1.96 seconds
Started Aug 23 09:47:20 AM UTC 24
Finished Aug 23 09:47:23 AM UTC 24
Peak memory 228976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009147407 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_prior
ity.3009147407
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.2848463448
Short name T308
Test name
Test status
Simulation time 1555371277 ps
CPU time 5.86 seconds
Started Aug 23 09:47:15 AM UTC 24
Finished Aug 23 09:47:22 AM UTC 24
Peak memory 231808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848463448
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_jtag_prog_failure.2848463448
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3737153070
Short name T320
Test name
Test status
Simulation time 3423169527 ps
CPU time 19.05 seconds
Started Aug 23 09:47:23 AM UTC 24
Finished Aug 23 09:47:43 AM UTC 24
Peak memory 229628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737153070
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_
ctrl_jtag_regwen_during_op.3737153070
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1631345888
Short name T306
Test name
Test status
Simulation time 164391126 ps
CPU time 1.61 seconds
Started Aug 23 09:47:12 AM UTC 24
Finished Aug 23 09:47:15 AM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631345888
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_s
moke.1631345888
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.2342193680
Short name T312
Test name
Test status
Simulation time 680033269 ps
CPU time 15.42 seconds
Started Aug 23 09:47:14 AM UTC 24
Finished Aug 23 09:47:31 AM UTC 24
Peak memory 262740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342193680
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_
ctrl_jtag_state_post_trans.2342193680
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.3412826198
Short name T301
Test name
Test status
Simulation time 63296062 ps
CPU time 2.36 seconds
Started Aug 23 09:47:05 AM UTC 24
Finished Aug 23 09:47:08 AM UTC 24
Peak memory 236304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412826198 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3412826198
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2353746187
Short name T88
Test name
Test status
Simulation time 431500223 ps
CPU time 10.41 seconds
Started Aug 23 09:47:11 AM UTC 24
Finished Aug 23 09:47:22 AM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353746187 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2353746187
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3968404381
Short name T314
Test name
Test status
Simulation time 1474746488 ps
CPU time 7.85 seconds
Started Aug 23 09:47:24 AM UTC 24
Finished Aug 23 09:47:33 AM UTC 24
Peak memory 237376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968404381 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3968404381
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.3558785334
Short name T318
Test name
Test status
Simulation time 1182347747 ps
CPU time 11.71 seconds
Started Aug 23 09:47:24 AM UTC 24
Finished Aug 23 09:47:37 AM UTC 24
Peak memory 229752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558785334 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_tok
en_digest.3558785334
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.1195955240
Short name T313
Test name
Test status
Simulation time 3638866584 ps
CPU time 6.27 seconds
Started Aug 23 09:47:24 AM UTC 24
Finished Aug 23 09:47:31 AM UTC 24
Peak memory 232092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195955240 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_
mux.1195955240
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.1336071861
Short name T62
Test name
Test status
Simulation time 2456919068 ps
CPU time 8.86 seconds
Started Aug 23 09:47:09 AM UTC 24
Finished Aug 23 09:47:19 AM UTC 24
Peak memory 237652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336071861 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1336071861
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.4281093012
Short name T297
Test name
Test status
Simulation time 36745219 ps
CPU time 2.01 seconds
Started Aug 23 09:47:00 AM UTC 24
Finished Aug 23 09:47:03 AM UTC 24
Peak memory 225060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281093012 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.4281093012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3079073973
Short name T311
Test name
Test status
Simulation time 1510228181 ps
CPU time 20.03 seconds
Started Aug 23 09:47:05 AM UTC 24
Finished Aug 23 09:47:26 AM UTC 24
Peak memory 262516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079073973 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3079073973
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.55824468
Short name T304
Test name
Test status
Simulation time 72535640 ps
CPU time 6.07 seconds
Started Aug 23 09:47:05 AM UTC 24
Finished Aug 23 09:47:12 AM UTC 24
Peak memory 262704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55824468 -assert nopostproc +UVM_TESTNAME=lc_ctr
l_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.55824468
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.1381354988
Short name T455
Test name
Test status
Simulation time 10018761391 ps
CPU time 276.06 seconds
Started Aug 23 09:47:27 AM UTC 24
Finished Aug 23 09:52:07 AM UTC 24
Peak memory 285084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1381354988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 8.lc_ctrl_stress_all.1381354988
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3669795516
Short name T139
Test name
Test status
Simulation time 885648780 ps
CPU time 17.55 seconds
Started Aug 23 09:47:30 AM UTC 24
Finished Aug 23 09:47:49 AM UTC 24
Peak memory 262628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669795516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_u
nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3669795516
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2257694002
Short name T299
Test name
Test status
Simulation time 13819635 ps
CPU time 0.86 seconds
Started Aug 23 09:47:02 AM UTC 24
Finished Aug 23 09:47:04 AM UTC 24
Peak memory 218496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257694002 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.
lc_ctrl_volatile_unlock_smoke.2257694002
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.1663889356
Short name T330
Test name
Test status
Simulation time 23265707 ps
CPU time 1.11 seconds
Started Aug 23 09:47:59 AM UTC 24
Finished Aug 23 09:48:01 AM UTC 24
Peak memory 218524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663889356 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1663889356
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.1757000116
Short name T323
Test name
Test status
Simulation time 1159251910 ps
CPU time 11.19 seconds
Started Aug 23 09:47:37 AM UTC 24
Finished Aug 23 09:47:49 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757000116 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1757000116
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.1728277839
Short name T31
Test name
Test status
Simulation time 673600833 ps
CPU time 7.43 seconds
Started Aug 23 09:47:49 AM UTC 24
Finished Aug 23 09:47:58 AM UTC 24
Peak memory 229608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728277839 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1728277839
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.3582070183
Short name T343
Test name
Test status
Simulation time 1643252072 ps
CPU time 44.82 seconds
Started Aug 23 09:47:49 AM UTC 24
Finished Aug 23 09:48:36 AM UTC 24
Peak memory 232144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582070183
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jt
ag_errors.3582070183
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.4158581601
Short name T329
Test name
Test status
Simulation time 10027506320 ps
CPU time 7.78 seconds
Started Aug 23 09:47:49 AM UTC 24
Finished Aug 23 09:47:58 AM UTC 24
Peak memory 229756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158581601 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_prior
ity.4158581601
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.2052803335
Short name T327
Test name
Test status
Simulation time 2570932192 ps
CPU time 9.14 seconds
Started Aug 23 09:47:47 AM UTC 24
Finished Aug 23 09:47:58 AM UTC 24
Peak memory 231952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052803335
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_jtag_prog_failure.2052803335
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1206855772
Short name T336
Test name
Test status
Simulation time 3390685526 ps
CPU time 20.42 seconds
Started Aug 23 09:47:51 AM UTC 24
Finished Aug 23 09:48:12 AM UTC 24
Peak memory 229948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206855772
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_
ctrl_jtag_regwen_during_op.1206855772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.2289367916
Short name T326
Test name
Test status
Simulation time 388016578 ps
CPU time 9.04 seconds
Started Aug 23 09:47:44 AM UTC 24
Finished Aug 23 09:47:54 AM UTC 24
Peak memory 229816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289367916
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_s
moke.2289367916
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.3217459599
Short name T339
Test name
Test status
Simulation time 2039789480 ps
CPU time 35.51 seconds
Started Aug 23 09:47:44 AM UTC 24
Finished Aug 23 09:48:21 AM UTC 24
Peak memory 282968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217459599
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_jtag_state_failure.3217459599
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1109003318
Short name T325
Test name
Test status
Simulation time 292591054 ps
CPU time 5.35 seconds
Started Aug 23 09:47:45 AM UTC 24
Finished Aug 23 09:47:51 AM UTC 24
Peak memory 232136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109003318
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_
ctrl_jtag_state_post_trans.1109003318
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.3540593939
Short name T319
Test name
Test status
Simulation time 29115225 ps
CPU time 1.82 seconds
Started Aug 23 09:47:36 AM UTC 24
Finished Aug 23 09:47:38 AM UTC 24
Peak memory 229912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540593939 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3540593939
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.1065394328
Short name T322
Test name
Test status
Simulation time 363259054 ps
CPU time 8.32 seconds
Started Aug 23 09:47:39 AM UTC 24
Finished Aug 23 09:47:48 AM UTC 24
Peak memory 225936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065394328 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1065394328
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3772234123
Short name T332
Test name
Test status
Simulation time 721209142 ps
CPU time 15.05 seconds
Started Aug 23 09:47:53 AM UTC 24
Finished Aug 23 09:48:09 AM UTC 24
Peak memory 231872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772234123 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3772234123
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2825563619
Short name T338
Test name
Test status
Simulation time 789832003 ps
CPU time 20.47 seconds
Started Aug 23 09:47:58 AM UTC 24
Finished Aug 23 09:48:19 AM UTC 24
Peak memory 231800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825563619 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_tok
en_digest.2825563619
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.2212540985
Short name T335
Test name
Test status
Simulation time 534983987 ps
CPU time 15.2 seconds
Started Aug 23 09:47:55 AM UTC 24
Finished Aug 23 09:48:11 AM UTC 24
Peak memory 232200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212540985 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_
mux.2212540985
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.281459137
Short name T63
Test name
Test status
Simulation time 393568821 ps
CPU time 8.03 seconds
Started Aug 23 09:47:38 AM UTC 24
Finished Aug 23 09:47:47 AM UTC 24
Peak memory 231960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281459137 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.281459137
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.29364392
Short name T317
Test name
Test status
Simulation time 1499377834 ps
CPU time 2.66 seconds
Started Aug 23 09:47:32 AM UTC 24
Finished Aug 23 09:47:36 AM UTC 24
Peak memory 229560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29364392 -assert nopostproc +UVM_TESTNAME=lc_ctr
l_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.29364392
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.538303791
Short name T324
Test name
Test status
Simulation time 166435635 ps
CPU time 14.7 seconds
Started Aug 23 09:47:34 AM UTC 24
Finished Aug 23 09:47:49 AM UTC 24
Peak memory 260452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538303791 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.538303791
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.3603109900
Short name T321
Test name
Test status
Simulation time 65375461 ps
CPU time 8.24 seconds
Started Aug 23 09:47:34 AM UTC 24
Finished Aug 23 09:47:43 AM UTC 24
Peak memory 262584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603109900 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3603109900
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.2781658388
Short name T192
Test name
Test status
Simulation time 51433106798 ps
CPU time 200.78 seconds
Started Aug 23 09:47:59 AM UTC 24
Finished Aug 23 09:51:22 AM UTC 24
Peak memory 295356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000
000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2781658388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 9.lc_ctrl_stress_all.2781658388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1002370158
Short name T140
Test name
Test status
Simulation time 5715059244 ps
CPU time 88.97 seconds
Started Aug 23 09:47:59 AM UTC 24
Finished Aug 23 09:49:30 AM UTC 24
Peak memory 291440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r
and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002370158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_u
nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.1002370158
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.582269356
Short name T316
Test name
Test status
Simulation time 44260153 ps
CPU time 0.8 seconds
Started Aug 23 09:47:34 AM UTC 24
Finished Aug 23 09:47:35 AM UTC 24
Peak memory 218228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582269356 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.l
c_ctrl_volatile_unlock_smoke.582269356
Directory /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_volatile_unlock_smoke/latest
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