| T816 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.222897108 |
|
|
Aug 27 08:06:20 PM UTC 24 |
Aug 27 08:06:30 PM UTC 24 |
483569706 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.3752288899 |
|
|
Aug 27 08:06:19 PM UTC 24 |
Aug 27 08:06:31 PM UTC 24 |
4528868168 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.4213433249 |
|
|
Aug 27 08:06:29 PM UTC 24 |
Aug 27 08:06:31 PM UTC 24 |
13356557 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.3859956339 |
|
|
Aug 27 08:06:19 PM UTC 24 |
Aug 27 08:06:32 PM UTC 24 |
351269297 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.658747842 |
|
|
Aug 27 08:06:27 PM UTC 24 |
Aug 27 08:06:32 PM UTC 24 |
227506234 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.1223874101 |
|
|
Aug 27 08:06:29 PM UTC 24 |
Aug 27 08:06:33 PM UTC 24 |
109499504 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.1578550503 |
|
|
Aug 27 08:06:23 PM UTC 24 |
Aug 27 08:06:33 PM UTC 24 |
787916701 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.4279738895 |
|
|
Aug 27 08:06:20 PM UTC 24 |
Aug 27 08:06:33 PM UTC 24 |
300291215 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.1488887459 |
|
|
Aug 27 08:06:23 PM UTC 24 |
Aug 27 08:06:34 PM UTC 24 |
324327457 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.2865370609 |
|
|
Aug 27 08:06:22 PM UTC 24 |
Aug 27 08:06:34 PM UTC 24 |
338389530 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1451172849 |
|
|
Aug 27 08:05:19 PM UTC 24 |
Aug 27 08:06:34 PM UTC 24 |
2683372109 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1894213902 |
|
|
Aug 27 08:05:36 PM UTC 24 |
Aug 27 08:06:34 PM UTC 24 |
1060724653 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.4268597100 |
|
|
Aug 27 08:06:25 PM UTC 24 |
Aug 27 08:06:35 PM UTC 24 |
1337823770 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.156387090 |
|
|
Aug 27 08:06:31 PM UTC 24 |
Aug 27 08:06:35 PM UTC 24 |
298065456 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.4262118121 |
|
|
Aug 27 08:06:34 PM UTC 24 |
Aug 27 08:06:36 PM UTC 24 |
13193163 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3316448151 |
|
|
Aug 27 08:06:34 PM UTC 24 |
Aug 27 08:06:36 PM UTC 24 |
15508164 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.2546943986 |
|
|
Aug 27 08:06:25 PM UTC 24 |
Aug 27 08:06:36 PM UTC 24 |
2669583460 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.275689253 |
|
|
Aug 27 08:06:22 PM UTC 24 |
Aug 27 08:06:37 PM UTC 24 |
649589868 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.2441566717 |
|
|
Aug 27 08:06:25 PM UTC 24 |
Aug 27 08:06:38 PM UTC 24 |
6156419897 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.1021801093 |
|
|
Aug 27 08:04:12 PM UTC 24 |
Aug 27 08:06:39 PM UTC 24 |
37571889617 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.1810504513 |
|
|
Aug 27 08:06:34 PM UTC 24 |
Aug 27 08:06:40 PM UTC 24 |
572159511 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.3932403989 |
|
|
Aug 27 08:06:36 PM UTC 24 |
Aug 27 08:06:40 PM UTC 24 |
276075527 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.1299102945 |
|
|
Aug 27 08:06:37 PM UTC 24 |
Aug 27 08:06:40 PM UTC 24 |
53218700 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.746583576 |
|
|
Aug 27 08:06:29 PM UTC 24 |
Aug 27 08:06:40 PM UTC 24 |
75796582 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.1528475013 |
|
|
Aug 27 08:06:31 PM UTC 24 |
Aug 27 08:06:42 PM UTC 24 |
389731493 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.657451554 |
|
|
Aug 27 08:06:33 PM UTC 24 |
Aug 27 08:06:42 PM UTC 24 |
745261553 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.346043493 |
|
|
Aug 27 08:06:30 PM UTC 24 |
Aug 27 08:06:42 PM UTC 24 |
992725531 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.937155646 |
|
|
Aug 27 08:06:31 PM UTC 24 |
Aug 27 08:06:42 PM UTC 24 |
306749757 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.3977924291 |
|
|
Aug 27 08:06:26 PM UTC 24 |
Aug 27 08:06:42 PM UTC 24 |
858005523 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.1245847053 |
|
|
Aug 27 08:06:33 PM UTC 24 |
Aug 27 08:06:43 PM UTC 24 |
1162832252 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.3918167515 |
|
|
Aug 27 08:06:41 PM UTC 24 |
Aug 27 08:06:43 PM UTC 24 |
18252975 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2037435833 |
|
|
Aug 27 08:05:12 PM UTC 24 |
Aug 27 08:06:45 PM UTC 24 |
6622180555 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.2233905808 |
|
|
Aug 27 08:06:10 PM UTC 24 |
Aug 27 08:06:45 PM UTC 24 |
663333924 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.2400449982 |
|
|
Aug 27 08:06:18 PM UTC 24 |
Aug 27 08:06:46 PM UTC 24 |
436151468 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.898360712 |
|
|
Aug 27 08:06:36 PM UTC 24 |
Aug 27 08:06:47 PM UTC 24 |
148315486 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.2745540105 |
|
|
Aug 27 08:06:26 PM UTC 24 |
Aug 27 08:06:47 PM UTC 24 |
967343474 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.3176714513 |
|
|
Aug 27 08:04:12 PM UTC 24 |
Aug 27 08:06:49 PM UTC 24 |
13045492572 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.1099694953 |
|
|
Aug 27 08:06:38 PM UTC 24 |
Aug 27 08:06:50 PM UTC 24 |
1346597086 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.45119398 |
|
|
Aug 27 08:06:36 PM UTC 24 |
Aug 27 08:06:51 PM UTC 24 |
1524224084 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.3085336270 |
|
|
Aug 27 08:06:36 PM UTC 24 |
Aug 27 08:06:53 PM UTC 24 |
708216889 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.4059468412 |
|
|
Aug 27 08:06:37 PM UTC 24 |
Aug 27 08:06:53 PM UTC 24 |
1292122314 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.3194479812 |
|
|
Aug 27 08:06:37 PM UTC 24 |
Aug 27 08:06:53 PM UTC 24 |
701041673 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.72157803 |
|
|
Aug 27 08:06:07 PM UTC 24 |
Aug 27 08:06:56 PM UTC 24 |
5190274442 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.1930647314 |
|
|
Aug 27 08:06:22 PM UTC 24 |
Aug 27 08:06:58 PM UTC 24 |
195775202 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.4114204980 |
|
|
Aug 27 08:06:29 PM UTC 24 |
Aug 27 08:06:59 PM UTC 24 |
994428940 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1893866276 |
|
|
Aug 27 08:05:59 PM UTC 24 |
Aug 27 08:07:20 PM UTC 24 |
1384016388 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.477262531 |
|
|
Aug 27 08:06:26 PM UTC 24 |
Aug 27 08:07:23 PM UTC 24 |
1990626772 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.762949938 |
|
|
Aug 27 08:05:54 PM UTC 24 |
Aug 27 08:07:27 PM UTC 24 |
1981072306 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.2066272268 |
|
|
Aug 27 08:05:59 PM UTC 24 |
Aug 27 08:07:30 PM UTC 24 |
3788027592 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.3251131404 |
|
|
Aug 27 08:05:13 PM UTC 24 |
Aug 27 08:07:30 PM UTC 24 |
2568170112 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.1045542386 |
|
|
Aug 27 08:01:54 PM UTC 24 |
Aug 27 08:07:32 PM UTC 24 |
43129417597 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.559281402 |
|
|
Aug 27 08:03:16 PM UTC 24 |
Aug 27 08:07:35 PM UTC 24 |
51431918074 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.202906029 |
|
|
Aug 27 08:03:25 PM UTC 24 |
Aug 27 08:07:40 PM UTC 24 |
22293476987 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.3279906593 |
|
|
Aug 27 08:05:54 PM UTC 24 |
Aug 27 08:07:41 PM UTC 24 |
10787864084 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.808816350 |
|
|
Aug 27 08:06:26 PM UTC 24 |
Aug 27 08:07:43 PM UTC 24 |
6276046894 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.3230668438 |
|
|
Aug 27 08:05:40 PM UTC 24 |
Aug 27 08:07:44 PM UTC 24 |
10861282801 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.4278674751 |
|
|
Aug 27 08:05:24 PM UTC 24 |
Aug 27 08:07:46 PM UTC 24 |
8686581938 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.2421204062 |
|
|
Aug 27 08:04:33 PM UTC 24 |
Aug 27 08:07:55 PM UTC 24 |
12342403111 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.2722195017 |
|
|
Aug 27 08:05:47 PM UTC 24 |
Aug 27 08:08:08 PM UTC 24 |
5797244529 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.3171681097 |
|
|
Aug 27 08:06:33 PM UTC 24 |
Aug 27 08:08:13 PM UTC 24 |
5691884271 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.1688010373 |
|
|
Aug 27 08:06:22 PM UTC 24 |
Aug 27 08:08:14 PM UTC 24 |
5704473271 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.2541979538 |
|
|
Aug 27 08:04:08 PM UTC 24 |
Aug 27 08:09:23 PM UTC 24 |
14264598185 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.2544151793 |
|
|
Aug 27 08:06:13 PM UTC 24 |
Aug 27 08:09:26 PM UTC 24 |
7930891433 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.3847397550 |
|
|
Aug 27 08:04:37 PM UTC 24 |
Aug 27 08:09:28 PM UTC 24 |
174151106844 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.1312891163 |
|
|
Aug 27 08:04:27 PM UTC 24 |
Aug 27 08:09:30 PM UTC 24 |
14936741120 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.2178991364 |
|
|
Aug 27 08:02:12 PM UTC 24 |
Aug 27 08:09:44 PM UTC 24 |
23425907900 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.2616474938 |
|
|
Aug 27 08:06:06 PM UTC 24 |
Aug 27 08:09:46 PM UTC 24 |
8447893281 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.2092910122 |
|
|
Aug 27 08:06:39 PM UTC 24 |
Aug 27 08:10:09 PM UTC 24 |
7656994951 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.119981332 |
|
|
Aug 27 08:05:36 PM UTC 24 |
Aug 27 08:11:21 PM UTC 24 |
11271104290 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.211405048 |
|
|
Aug 27 08:04:59 PM UTC 24 |
Aug 27 08:11:36 PM UTC 24 |
24624633605 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.2116397987 |
|
|
Aug 27 08:05:05 PM UTC 24 |
Aug 27 08:12:11 PM UTC 24 |
14902170376 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2703942790 |
|
|
Aug 27 08:06:41 PM UTC 24 |
Aug 27 08:06:44 PM UTC 24 |
35154391 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1946866630 |
|
|
Aug 27 08:06:42 PM UTC 24 |
Aug 27 08:06:45 PM UTC 24 |
40652136 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2442979750 |
|
|
Aug 27 08:06:41 PM UTC 24 |
Aug 27 08:06:46 PM UTC 24 |
95040644 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1205842442 |
|
|
Aug 27 08:06:44 PM UTC 24 |
Aug 27 08:06:47 PM UTC 24 |
14321534 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1480881639 |
|
|
Aug 27 08:06:44 PM UTC 24 |
Aug 27 08:06:47 PM UTC 24 |
35031157 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1843173373 |
|
|
Aug 27 08:06:44 PM UTC 24 |
Aug 27 08:06:47 PM UTC 24 |
84832862 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1486847233 |
|
|
Aug 27 08:06:44 PM UTC 24 |
Aug 27 08:06:47 PM UTC 24 |
203135016 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3845247023 |
|
|
Aug 27 08:06:45 PM UTC 24 |
Aug 27 08:06:48 PM UTC 24 |
49671204 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3339478654 |
|
|
Aug 27 08:06:47 PM UTC 24 |
Aug 27 08:06:49 PM UTC 24 |
41768943 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3327113561 |
|
|
Aug 27 08:06:47 PM UTC 24 |
Aug 27 08:06:49 PM UTC 24 |
19867031 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1559936031 |
|
|
Aug 27 08:06:44 PM UTC 24 |
Aug 27 08:06:50 PM UTC 24 |
262535391 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3840759663 |
|
|
Aug 27 08:06:47 PM UTC 24 |
Aug 27 08:06:50 PM UTC 24 |
41891449 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1487577994 |
|
|
Aug 27 08:06:47 PM UTC 24 |
Aug 27 08:06:50 PM UTC 24 |
539762741 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1575519074 |
|
|
Aug 27 08:06:48 PM UTC 24 |
Aug 27 08:06:51 PM UTC 24 |
49090906 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2097241793 |
|
|
Aug 27 08:06:48 PM UTC 24 |
Aug 27 08:06:51 PM UTC 24 |
488157475 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2966914732 |
|
|
Aug 27 08:06:47 PM UTC 24 |
Aug 27 08:06:51 PM UTC 24 |
117167090 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.618720899 |
|
|
Aug 27 08:07:01 PM UTC 24 |
Aug 27 08:07:05 PM UTC 24 |
36766121 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1459939384 |
|
|
Aug 27 08:06:48 PM UTC 24 |
Aug 27 08:06:51 PM UTC 24 |
542452172 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.728984948 |
|
|
Aug 27 08:06:50 PM UTC 24 |
Aug 27 08:06:52 PM UTC 24 |
46206316 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3737577727 |
|
|
Aug 27 08:06:48 PM UTC 24 |
Aug 27 08:06:52 PM UTC 24 |
96819482 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3692719352 |
|
|
Aug 27 08:06:50 PM UTC 24 |
Aug 27 08:06:52 PM UTC 24 |
24560041 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2083840093 |
|
|
Aug 27 08:06:50 PM UTC 24 |
Aug 27 08:06:53 PM UTC 24 |
160790080 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.635944386 |
|
|
Aug 27 08:06:48 PM UTC 24 |
Aug 27 08:06:53 PM UTC 24 |
1444880980 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2883582799 |
|
|
Aug 27 08:06:51 PM UTC 24 |
Aug 27 08:06:54 PM UTC 24 |
63471792 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3805907184 |
|
|
Aug 27 08:06:51 PM UTC 24 |
Aug 27 08:06:54 PM UTC 24 |
92319731 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3396076383 |
|
|
Aug 27 08:06:51 PM UTC 24 |
Aug 27 08:06:54 PM UTC 24 |
160664172 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.4007512221 |
|
|
Aug 27 08:06:51 PM UTC 24 |
Aug 27 08:06:54 PM UTC 24 |
53257825 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1895425223 |
|
|
Aug 27 08:06:48 PM UTC 24 |
Aug 27 08:06:55 PM UTC 24 |
360075530 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4128600149 |
|
|
Aug 27 08:06:53 PM UTC 24 |
Aug 27 08:06:55 PM UTC 24 |
21100598 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1798660619 |
|
|
Aug 27 08:06:53 PM UTC 24 |
Aug 27 08:06:55 PM UTC 24 |
54351086 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1390000397 |
|
|
Aug 27 08:06:53 PM UTC 24 |
Aug 27 08:06:55 PM UTC 24 |
79690236 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.80927603 |
|
|
Aug 27 08:06:41 PM UTC 24 |
Aug 27 08:06:56 PM UTC 24 |
3999854546 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3846908217 |
|
|
Aug 27 08:06:42 PM UTC 24 |
Aug 27 08:06:56 PM UTC 24 |
373438927 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2938106152 |
|
|
Aug 27 08:06:53 PM UTC 24 |
Aug 27 08:06:56 PM UTC 24 |
517286172 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3468278320 |
|
|
Aug 27 08:06:54 PM UTC 24 |
Aug 27 08:06:57 PM UTC 24 |
74238789 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.140297944 |
|
|
Aug 27 08:06:54 PM UTC 24 |
Aug 27 08:06:57 PM UTC 24 |
18097581 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2621220901 |
|
|
Aug 27 08:06:54 PM UTC 24 |
Aug 27 08:06:57 PM UTC 24 |
20512400 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2003352598 |
|
|
Aug 27 08:06:53 PM UTC 24 |
Aug 27 08:06:57 PM UTC 24 |
120530861 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1229609315 |
|
|
Aug 27 08:06:48 PM UTC 24 |
Aug 27 08:06:57 PM UTC 24 |
633928994 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1780779732 |
|
|
Aug 27 08:06:54 PM UTC 24 |
Aug 27 08:06:57 PM UTC 24 |
43926071 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1752758845 |
|
|
Aug 27 08:06:53 PM UTC 24 |
Aug 27 08:06:58 PM UTC 24 |
224231597 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1655148272 |
|
|
Aug 27 08:06:54 PM UTC 24 |
Aug 27 08:06:58 PM UTC 24 |
91518796 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1688756434 |
|
|
Aug 27 08:06:56 PM UTC 24 |
Aug 27 08:06:58 PM UTC 24 |
39091528 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.335985689 |
|
|
Aug 27 08:06:54 PM UTC 24 |
Aug 27 08:06:58 PM UTC 24 |
511310044 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.459448051 |
|
|
Aug 27 08:06:53 PM UTC 24 |
Aug 27 08:06:58 PM UTC 24 |
217344349 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1674400577 |
|
|
Aug 27 08:07:01 PM UTC 24 |
Aug 27 08:07:04 PM UTC 24 |
15301434 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3220435379 |
|
|
Aug 27 08:07:08 PM UTC 24 |
Aug 27 08:07:11 PM UTC 24 |
19740738 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.813695224 |
|
|
Aug 27 08:06:56 PM UTC 24 |
Aug 27 08:06:59 PM UTC 24 |
240709284 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2400996018 |
|
|
Aug 27 08:06:56 PM UTC 24 |
Aug 27 08:06:59 PM UTC 24 |
52368509 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2087625303 |
|
|
Aug 27 08:06:57 PM UTC 24 |
Aug 27 08:06:59 PM UTC 24 |
52659009 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3905566997 |
|
|
Aug 27 08:06:57 PM UTC 24 |
Aug 27 08:06:59 PM UTC 24 |
106271121 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3650764917 |
|
|
Aug 27 08:06:57 PM UTC 24 |
Aug 27 08:06:59 PM UTC 24 |
27377387 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1409479178 |
|
|
Aug 27 08:06:57 PM UTC 24 |
Aug 27 08:07:00 PM UTC 24 |
63707964 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3093580764 |
|
|
Aug 27 08:06:57 PM UTC 24 |
Aug 27 08:07:00 PM UTC 24 |
132095566 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.259786613 |
|
|
Aug 27 08:06:57 PM UTC 24 |
Aug 27 08:07:01 PM UTC 24 |
49351743 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.4159406612 |
|
|
Aug 27 08:06:59 PM UTC 24 |
Aug 27 08:07:02 PM UTC 24 |
36045746 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3415115657 |
|
|
Aug 27 08:06:59 PM UTC 24 |
Aug 27 08:07:02 PM UTC 24 |
117372661 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2436592196 |
|
|
Aug 27 08:06:59 PM UTC 24 |
Aug 27 08:07:02 PM UTC 24 |
78405536 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.304434562 |
|
|
Aug 27 08:06:57 PM UTC 24 |
Aug 27 08:07:02 PM UTC 24 |
754125928 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.808421875 |
|
|
Aug 27 08:06:57 PM UTC 24 |
Aug 27 08:07:03 PM UTC 24 |
389982494 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1849206016 |
|
|
Aug 27 08:06:59 PM UTC 24 |
Aug 27 08:07:03 PM UTC 24 |
61233778 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1419709327 |
|
|
Aug 27 08:06:59 PM UTC 24 |
Aug 27 08:07:03 PM UTC 24 |
184863150 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1362510881 |
|
|
Aug 27 08:06:57 PM UTC 24 |
Aug 27 08:07:04 PM UTC 24 |
444831129 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2832494700 |
|
|
Aug 27 08:07:01 PM UTC 24 |
Aug 27 08:07:04 PM UTC 24 |
27448232 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.601653749 |
|
|
Aug 27 08:07:01 PM UTC 24 |
Aug 27 08:07:04 PM UTC 24 |
19704724 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2290496230 |
|
|
Aug 27 08:06:59 PM UTC 24 |
Aug 27 08:07:04 PM UTC 24 |
173893525 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.488463569 |
|
|
Aug 27 08:07:01 PM UTC 24 |
Aug 27 08:07:05 PM UTC 24 |
27524699 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.473267145 |
|
|
Aug 27 08:07:01 PM UTC 24 |
Aug 27 08:07:05 PM UTC 24 |
133260612 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.528665756 |
|
|
Aug 27 08:06:59 PM UTC 24 |
Aug 27 08:07:06 PM UTC 24 |
694391279 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1025752759 |
|
|
Aug 27 08:07:05 PM UTC 24 |
Aug 27 08:07:08 PM UTC 24 |
89535110 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4276512969 |
|
|
Aug 27 08:06:59 PM UTC 24 |
Aug 27 08:07:05 PM UTC 24 |
284111034 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2940392239 |
|
|
Aug 27 08:07:01 PM UTC 24 |
Aug 27 08:07:05 PM UTC 24 |
75915172 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.63339340 |
|
|
Aug 27 08:07:01 PM UTC 24 |
Aug 27 08:07:05 PM UTC 24 |
103606318 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1423446707 |
|
|
Aug 27 08:07:01 PM UTC 24 |
Aug 27 08:07:05 PM UTC 24 |
57825595 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3244598570 |
|
|
Aug 27 08:07:03 PM UTC 24 |
Aug 27 08:07:06 PM UTC 24 |
42714944 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1749954760 |
|
|
Aug 27 08:07:05 PM UTC 24 |
Aug 27 08:07:07 PM UTC 24 |
136769477 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2465207299 |
|
|
Aug 27 08:07:05 PM UTC 24 |
Aug 27 08:07:07 PM UTC 24 |
23697409 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2033170301 |
|
|
Aug 27 08:07:05 PM UTC 24 |
Aug 27 08:07:08 PM UTC 24 |
396367038 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4290271220 |
|
|
Aug 27 08:07:05 PM UTC 24 |
Aug 27 08:07:08 PM UTC 24 |
53203439 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3049559869 |
|
|
Aug 27 08:06:53 PM UTC 24 |
Aug 27 08:07:08 PM UTC 24 |
4831055960 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.927499199 |
|
|
Aug 27 08:07:05 PM UTC 24 |
Aug 27 08:07:08 PM UTC 24 |
528541153 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3435721001 |
|
|
Aug 27 08:07:24 PM UTC 24 |
Aug 27 08:07:27 PM UTC 24 |
59546795 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4223399689 |
|
|
Aug 27 08:07:05 PM UTC 24 |
Aug 27 08:07:09 PM UTC 24 |
98741375 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.722606927 |
|
|
Aug 27 08:07:05 PM UTC 24 |
Aug 27 08:07:09 PM UTC 24 |
309622817 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1816199729 |
|
|
Aug 27 08:07:07 PM UTC 24 |
Aug 27 08:07:09 PM UTC 24 |
58330234 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3527825639 |
|
|
Aug 27 08:07:03 PM UTC 24 |
Aug 27 08:07:09 PM UTC 24 |
350021274 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2602381432 |
|
|
Aug 27 08:07:05 PM UTC 24 |
Aug 27 08:07:09 PM UTC 24 |
1242728260 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1676286099 |
|
|
Aug 27 08:07:07 PM UTC 24 |
Aug 27 08:07:09 PM UTC 24 |
28731269 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4001323513 |
|
|
Aug 27 08:07:05 PM UTC 24 |
Aug 27 08:07:10 PM UTC 24 |
1327249660 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3414510536 |
|
|
Aug 27 08:07:07 PM UTC 24 |
Aug 27 08:07:11 PM UTC 24 |
57908260 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.111612313 |
|
|
Aug 27 08:07:08 PM UTC 24 |
Aug 27 08:07:11 PM UTC 24 |
762446508 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1236364027 |
|
|
Aug 27 08:07:03 PM UTC 24 |
Aug 27 08:07:11 PM UTC 24 |
517445166 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3990802088 |
|
|
Aug 27 08:07:08 PM UTC 24 |
Aug 27 08:07:11 PM UTC 24 |
101151493 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2571336621 |
|
|
Aug 27 08:07:07 PM UTC 24 |
Aug 27 08:07:11 PM UTC 24 |
651797767 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2392697319 |
|
|
Aug 27 08:07:08 PM UTC 24 |
Aug 27 08:07:12 PM UTC 24 |
22684351 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3453674600 |
|
|
Aug 27 08:07:09 PM UTC 24 |
Aug 27 08:07:12 PM UTC 24 |
49286993 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.953293289 |
|
|
Aug 27 08:07:08 PM UTC 24 |
Aug 27 08:07:12 PM UTC 24 |
90968419 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1031602371 |
|
|
Aug 27 08:06:59 PM UTC 24 |
Aug 27 08:07:12 PM UTC 24 |
443428711 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.932717645 |
|
|
Aug 27 08:07:07 PM UTC 24 |
Aug 27 08:07:13 PM UTC 24 |
405279609 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1317030805 |
|
|
Aug 27 08:07:11 PM UTC 24 |
Aug 27 08:07:13 PM UTC 24 |
18368252 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.869858139 |
|
|
Aug 27 08:07:10 PM UTC 24 |
Aug 27 08:07:13 PM UTC 24 |
30347825 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4115980192 |
|
|
Aug 27 08:07:11 PM UTC 24 |
Aug 27 08:07:14 PM UTC 24 |
98750873 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.671711052 |
|
|
Aug 27 08:07:10 PM UTC 24 |
Aug 27 08:07:14 PM UTC 24 |
177999409 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3371164753 |
|
|
Aug 27 08:07:10 PM UTC 24 |
Aug 27 08:07:14 PM UTC 24 |
51692059 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.7160848 |
|
|
Aug 27 08:07:11 PM UTC 24 |
Aug 27 08:07:14 PM UTC 24 |
59562420 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3725876312 |
|
|
Aug 27 08:07:11 PM UTC 24 |
Aug 27 08:07:14 PM UTC 24 |
154210504 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1054266986 |
|
|
Aug 27 08:07:13 PM UTC 24 |
Aug 27 08:07:15 PM UTC 24 |
46417483 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.512548110 |
|
|
Aug 27 08:07:12 PM UTC 24 |
Aug 27 08:07:15 PM UTC 24 |
186638318 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3639919461 |
|
|
Aug 27 08:07:12 PM UTC 24 |
Aug 27 08:07:16 PM UTC 24 |
590877665 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2275131054 |
|
|
Aug 27 08:07:11 PM UTC 24 |
Aug 27 08:07:17 PM UTC 24 |
132071508 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2331307846 |
|
|
Aug 27 08:07:15 PM UTC 24 |
Aug 27 08:07:17 PM UTC 24 |
60819593 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2493569958 |
|
|
Aug 27 08:07:13 PM UTC 24 |
Aug 27 08:07:18 PM UTC 24 |
99137766 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.155184135 |
|
|
Aug 27 08:07:15 PM UTC 24 |
Aug 27 08:07:18 PM UTC 24 |
52317871 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1810389281 |
|
|
Aug 27 08:07:15 PM UTC 24 |
Aug 27 08:07:18 PM UTC 24 |
125445703 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.5179568 |
|
|
Aug 27 08:07:15 PM UTC 24 |
Aug 27 08:07:18 PM UTC 24 |
65359399 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2449059832 |
|
|
Aug 27 08:07:15 PM UTC 24 |
Aug 27 08:07:18 PM UTC 24 |
747656509 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2524412875 |
|
|
Aug 27 08:07:13 PM UTC 24 |
Aug 27 08:07:18 PM UTC 24 |
396024582 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2014671866 |
|
|
Aug 27 08:07:15 PM UTC 24 |
Aug 27 08:07:19 PM UTC 24 |
230879672 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3587135248 |
|
|
Aug 27 08:07:15 PM UTC 24 |
Aug 27 08:07:19 PM UTC 24 |
247182229 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1646166810 |
|
|
Aug 27 08:07:17 PM UTC 24 |
Aug 27 08:07:19 PM UTC 24 |
23196193 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1810269690 |
|
|
Aug 27 08:07:17 PM UTC 24 |
Aug 27 08:07:19 PM UTC 24 |
15980800 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2076934587 |
|
|
Aug 27 08:07:15 PM UTC 24 |
Aug 27 08:07:19 PM UTC 24 |
101945241 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2604394292 |
|
|
Aug 27 08:07:15 PM UTC 24 |
Aug 27 08:07:19 PM UTC 24 |
260971279 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3535043436 |
|
|
Aug 27 08:07:17 PM UTC 24 |
Aug 27 08:07:19 PM UTC 24 |
65796886 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1586945669 |
|
|
Aug 27 08:07:15 PM UTC 24 |
Aug 27 08:07:20 PM UTC 24 |
32542270 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.828039909 |
|
|
Aug 27 08:07:15 PM UTC 24 |
Aug 27 08:07:20 PM UTC 24 |
1091889605 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1658301285 |
|
|
Aug 27 08:07:15 PM UTC 24 |
Aug 27 08:07:20 PM UTC 24 |
925485063 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1318020933 |
|
|
Aug 27 08:07:17 PM UTC 24 |
Aug 27 08:07:20 PM UTC 24 |
30118510 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2576198234 |
|
|
Aug 27 08:07:19 PM UTC 24 |
Aug 27 08:07:21 PM UTC 24 |
80607937 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3571444062 |
|
|
Aug 27 08:07:19 PM UTC 24 |
Aug 27 08:07:22 PM UTC 24 |
39141658 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3292251096 |
|
|
Aug 27 08:07:19 PM UTC 24 |
Aug 27 08:07:22 PM UTC 24 |
25881458 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3872252898 |
|
|
Aug 27 08:07:19 PM UTC 24 |
Aug 27 08:07:22 PM UTC 24 |
173958005 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1129758274 |
|
|
Aug 27 08:07:19 PM UTC 24 |
Aug 27 08:07:22 PM UTC 24 |
51476623 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3033093843 |
|
|
Aug 27 08:07:19 PM UTC 24 |
Aug 27 08:07:23 PM UTC 24 |
70151813 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2073793190 |
|
|
Aug 27 08:07:19 PM UTC 24 |
Aug 27 08:07:24 PM UTC 24 |
206387852 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1075806717 |
|
|
Aug 27 08:07:07 PM UTC 24 |
Aug 27 08:07:24 PM UTC 24 |
736148816 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2305769747 |
|
|
Aug 27 08:07:22 PM UTC 24 |
Aug 27 08:07:24 PM UTC 24 |
41105353 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3131065612 |
|
|
Aug 27 08:07:22 PM UTC 24 |
Aug 27 08:07:25 PM UTC 24 |
14094002 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3875847397 |
|
|
Aug 27 08:07:22 PM UTC 24 |
Aug 27 08:07:25 PM UTC 24 |
34514962 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4240469040 |
|
|
Aug 27 08:07:22 PM UTC 24 |
Aug 27 08:07:25 PM UTC 24 |
16871904 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2676000418 |
|
|
Aug 27 08:07:22 PM UTC 24 |
Aug 27 08:07:25 PM UTC 24 |
28015950 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3622676143 |
|
|
Aug 27 08:07:22 PM UTC 24 |
Aug 27 08:07:25 PM UTC 24 |
18970511 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3792705493 |
|
|
Aug 27 08:07:22 PM UTC 24 |
Aug 27 08:07:25 PM UTC 24 |
53214205 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2417891069 |
|
|
Aug 27 08:06:56 PM UTC 24 |
Aug 27 08:07:25 PM UTC 24 |
25696333577 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1071270391 |
|
|
Aug 27 08:07:22 PM UTC 24 |
Aug 27 08:07:25 PM UTC 24 |
65775133 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1032663994 |
|
|
Aug 27 08:07:22 PM UTC 24 |
Aug 27 08:07:25 PM UTC 24 |
240277405 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1117168872 |
|
|
Aug 27 08:07:22 PM UTC 24 |
Aug 27 08:07:25 PM UTC 24 |
65048177 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.404812999 |
|
|
Aug 27 08:07:12 PM UTC 24 |
Aug 27 08:07:26 PM UTC 24 |
1396827237 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2605313055 |
|
|
Aug 27 08:07:22 PM UTC 24 |
Aug 27 08:07:26 PM UTC 24 |
92300027 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2562688148 |
|
|
Aug 27 08:07:09 PM UTC 24 |
Aug 27 08:07:27 PM UTC 24 |
32412533664 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.263915707 |
|
|
Aug 27 08:07:22 PM UTC 24 |
Aug 27 08:07:27 PM UTC 24 |
744461605 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2570169154 |
|
|
Aug 27 08:07:24 PM UTC 24 |
Aug 27 08:07:27 PM UTC 24 |
16586697 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1086748052 |
|
|
Aug 27 08:07:22 PM UTC 24 |
Aug 27 08:07:27 PM UTC 24 |
93003612 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3418137070 |
|
|
Aug 27 08:07:22 PM UTC 24 |
Aug 27 08:07:27 PM UTC 24 |
82382147 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2743734182 |
|
|
Aug 27 08:07:24 PM UTC 24 |
Aug 27 08:07:27 PM UTC 24 |
12750752 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1702842106 |
|
|
Aug 27 08:07:24 PM UTC 24 |
Aug 27 08:07:27 PM UTC 24 |
51876479 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.894659883 |
|
|
Aug 27 08:07:24 PM UTC 24 |
Aug 27 08:07:27 PM UTC 24 |
25599526 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.4057932528 |
|
|
Aug 27 08:07:24 PM UTC 24 |
Aug 27 08:07:27 PM UTC 24 |
59669829 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2280606912 |
|
|
Aug 27 08:07:24 PM UTC 24 |
Aug 27 08:07:28 PM UTC 24 |
65220528 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3803215328 |
|
|
Aug 27 08:07:24 PM UTC 24 |
Aug 27 08:07:29 PM UTC 24 |
83454942 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3195226434 |
|
|
Aug 27 08:07:26 PM UTC 24 |
Aug 27 08:07:29 PM UTC 24 |
15352323 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.575580516 |
|
|
Aug 27 08:07:27 PM UTC 24 |
Aug 27 08:07:29 PM UTC 24 |
30571656 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.4070274983 |
|
|
Aug 27 08:07:26 PM UTC 24 |
Aug 27 08:07:29 PM UTC 24 |
42421913 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.991625636 |
|
|
Aug 27 08:07:27 PM UTC 24 |
Aug 27 08:07:29 PM UTC 24 |
89711136 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3442632654 |
|
|
Aug 27 08:07:27 PM UTC 24 |
Aug 27 08:07:29 PM UTC 24 |
46220274 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2957656438 |
|
|
Aug 27 08:07:26 PM UTC 24 |
Aug 27 08:07:29 PM UTC 24 |
194361716 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3043074993 |
|
|
Aug 27 08:07:27 PM UTC 24 |
Aug 27 08:07:30 PM UTC 24 |
43566892 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2252579609 |
|
|
Aug 27 08:07:27 PM UTC 24 |
Aug 27 08:07:30 PM UTC 24 |
53651532 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3483107993 |
|
|
Aug 27 08:07:27 PM UTC 24 |
Aug 27 08:07:30 PM UTC 24 |
233330421 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2889747676 |
|
|
Aug 27 08:07:27 PM UTC 24 |
Aug 27 08:07:31 PM UTC 24 |
152778506 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.727042111 |
|
|
Aug 27 08:07:26 PM UTC 24 |
Aug 27 08:07:31 PM UTC 24 |
1819201650 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.4163850606 |
|
|
Aug 27 08:07:09 PM UTC 24 |
Aug 27 08:07:32 PM UTC 24 |
3941888369 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3082812661 |
|
|
Aug 27 08:07:31 PM UTC 24 |
Aug 27 08:07:34 PM UTC 24 |
26694643 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.45391018 |
|
|
Aug 27 08:07:31 PM UTC 24 |
Aug 27 08:07:34 PM UTC 24 |
18052749 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2539009115 |
|
|
Aug 27 08:07:31 PM UTC 24 |
Aug 27 08:07:34 PM UTC 24 |
14991343 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1940811814 |
|
|
Aug 27 08:07:31 PM UTC 24 |
Aug 27 08:07:34 PM UTC 24 |
46601269 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.623335357 |
|
|
Aug 27 08:07:31 PM UTC 24 |
Aug 27 08:07:34 PM UTC 24 |
837924719 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.229194646 |
|
|
Aug 27 08:07:31 PM UTC 24 |
Aug 27 08:07:34 PM UTC 24 |
96367944 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1639665059 |
|
|
Aug 27 08:07:31 PM UTC 24 |
Aug 27 08:07:35 PM UTC 24 |
160714458 ps |