| T815 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.3682568952 |
|
|
Sep 04 04:59:55 PM UTC 24 |
Sep 04 05:00:09 PM UTC 24 |
4371963885 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.2768997684 |
|
|
Sep 04 04:59:55 PM UTC 24 |
Sep 04 05:00:10 PM UTC 24 |
2765755101 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.621322053 |
|
|
Sep 04 05:00:09 PM UTC 24 |
Sep 04 05:00:54 PM UTC 24 |
3274411881 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1779257711 |
|
|
Sep 04 05:00:09 PM UTC 24 |
Sep 04 05:00:12 PM UTC 24 |
33430466 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.2228944943 |
|
|
Sep 04 05:00:09 PM UTC 24 |
Sep 04 05:00:12 PM UTC 24 |
18997097 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.1276094856 |
|
|
Sep 04 04:59:46 PM UTC 24 |
Sep 04 05:00:12 PM UTC 24 |
691013132 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.1914473111 |
|
|
Sep 04 04:59:55 PM UTC 24 |
Sep 04 05:00:13 PM UTC 24 |
638662049 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.215444983 |
|
|
Sep 04 04:59:57 PM UTC 24 |
Sep 04 05:00:13 PM UTC 24 |
691932307 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.1985525997 |
|
|
Sep 04 05:00:11 PM UTC 24 |
Sep 04 05:00:15 PM UTC 24 |
25988996 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.2752748298 |
|
|
Sep 04 05:00:09 PM UTC 24 |
Sep 04 05:00:15 PM UTC 24 |
368437153 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.2484831525 |
|
|
Sep 04 05:00:09 PM UTC 24 |
Sep 04 05:00:15 PM UTC 24 |
316924915 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.1699886697 |
|
|
Sep 04 05:00:13 PM UTC 24 |
Sep 04 05:00:17 PM UTC 24 |
573965889 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.3472821699 |
|
|
Sep 04 04:59:57 PM UTC 24 |
Sep 04 05:00:18 PM UTC 24 |
680965619 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.1197354449 |
|
|
Sep 04 05:00:17 PM UTC 24 |
Sep 04 05:00:19 PM UTC 24 |
26273814 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.1275044386 |
|
|
Sep 04 05:00:09 PM UTC 24 |
Sep 04 05:00:20 PM UTC 24 |
985351832 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.20344303 |
|
|
Sep 04 05:00:09 PM UTC 24 |
Sep 04 05:00:20 PM UTC 24 |
126483267 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.503601369 |
|
|
Sep 04 05:00:18 PM UTC 24 |
Sep 04 05:00:20 PM UTC 24 |
39064986 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.17124412 |
|
|
Sep 04 05:00:17 PM UTC 24 |
Sep 04 05:00:21 PM UTC 24 |
218450857 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.1193768109 |
|
|
Sep 04 04:59:53 PM UTC 24 |
Sep 04 05:00:22 PM UTC 24 |
827738865 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.3165770629 |
|
|
Sep 04 05:00:09 PM UTC 24 |
Sep 04 05:00:22 PM UTC 24 |
4500058531 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.2431131718 |
|
|
Sep 04 05:00:12 PM UTC 24 |
Sep 04 05:00:22 PM UTC 24 |
1490233725 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.3930928057 |
|
|
Sep 04 05:00:09 PM UTC 24 |
Sep 04 05:00:22 PM UTC 24 |
547795334 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.1174725405 |
|
|
Sep 04 05:00:11 PM UTC 24 |
Sep 04 05:00:23 PM UTC 24 |
82822501 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.974516897 |
|
|
Sep 04 05:00:09 PM UTC 24 |
Sep 04 05:00:23 PM UTC 24 |
611884114 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.207662878 |
|
|
Sep 04 04:58:06 PM UTC 24 |
Sep 04 05:00:23 PM UTC 24 |
3012279760 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.3422688672 |
|
|
Sep 04 04:58:59 PM UTC 24 |
Sep 04 05:00:24 PM UTC 24 |
8414824737 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.1760166227 |
|
|
Sep 04 05:00:21 PM UTC 24 |
Sep 04 05:00:25 PM UTC 24 |
46890018 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.676512885 |
|
|
Sep 04 05:00:09 PM UTC 24 |
Sep 04 05:00:26 PM UTC 24 |
387657441 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.3484560593 |
|
|
Sep 04 05:00:09 PM UTC 24 |
Sep 04 05:00:28 PM UTC 24 |
7868586592 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.537235290 |
|
|
Sep 04 05:00:13 PM UTC 24 |
Sep 04 05:00:28 PM UTC 24 |
598536517 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.2456797343 |
|
|
Sep 04 05:00:26 PM UTC 24 |
Sep 04 05:00:28 PM UTC 24 |
14282314 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.1743431016 |
|
|
Sep 04 05:00:15 PM UTC 24 |
Sep 04 05:00:30 PM UTC 24 |
246313310 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.3416589823 |
|
|
Sep 04 05:00:23 PM UTC 24 |
Sep 04 05:00:32 PM UTC 24 |
1070530604 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.2080939995 |
|
|
Sep 04 05:00:13 PM UTC 24 |
Sep 04 05:00:32 PM UTC 24 |
881568321 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.2835841902 |
|
|
Sep 04 05:00:13 PM UTC 24 |
Sep 04 05:00:32 PM UTC 24 |
1330561002 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.1591067821 |
|
|
Sep 04 05:00:21 PM UTC 24 |
Sep 04 05:00:33 PM UTC 24 |
318554969 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.1163616048 |
|
|
Sep 04 05:00:21 PM UTC 24 |
Sep 04 05:00:34 PM UTC 24 |
440534704 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.667927406 |
|
|
Sep 04 05:00:23 PM UTC 24 |
Sep 04 05:00:36 PM UTC 24 |
731990111 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.3391124111 |
|
|
Sep 04 05:00:23 PM UTC 24 |
Sep 04 05:00:37 PM UTC 24 |
2445824867 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.1060680226 |
|
|
Sep 04 05:00:21 PM UTC 24 |
Sep 04 05:00:39 PM UTC 24 |
373420108 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.2075797905 |
|
|
Sep 04 05:00:02 PM UTC 24 |
Sep 04 05:00:39 PM UTC 24 |
329563064 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.2649726808 |
|
|
Sep 04 05:00:23 PM UTC 24 |
Sep 04 05:00:39 PM UTC 24 |
488932863 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.3865922293 |
|
|
Sep 04 05:00:19 PM UTC 24 |
Sep 04 05:00:45 PM UTC 24 |
238191366 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.2905387286 |
|
|
Sep 04 04:55:45 PM UTC 24 |
Sep 04 05:00:46 PM UTC 24 |
28994815222 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.1208063831 |
|
|
Sep 04 04:56:08 PM UTC 24 |
Sep 04 05:00:47 PM UTC 24 |
35368854533 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.3626909892 |
|
|
Sep 04 04:59:15 PM UTC 24 |
Sep 04 05:00:48 PM UTC 24 |
17542879126 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.2910119868 |
|
|
Sep 04 05:00:11 PM UTC 24 |
Sep 04 05:00:50 PM UTC 24 |
4632851020 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2099534978 |
|
|
Sep 04 04:58:31 PM UTC 24 |
Sep 04 05:00:57 PM UTC 24 |
10041403059 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.3755425007 |
|
|
Sep 04 04:59:52 PM UTC 24 |
Sep 04 05:01:02 PM UTC 24 |
15256488185 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.2942466494 |
|
|
Sep 04 04:59:58 PM UTC 24 |
Sep 04 05:01:03 PM UTC 24 |
5666027312 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.1391329833 |
|
|
Sep 04 04:55:32 PM UTC 24 |
Sep 04 05:01:15 PM UTC 24 |
50259322408 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.2356333140 |
|
|
Sep 04 04:59:06 PM UTC 24 |
Sep 04 05:01:30 PM UTC 24 |
42146369792 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.2556516747 |
|
|
Sep 04 05:00:00 PM UTC 24 |
Sep 04 05:01:31 PM UTC 24 |
5705421288 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.725301311 |
|
|
Sep 04 04:59:33 PM UTC 24 |
Sep 04 05:02:14 PM UTC 24 |
5241959612 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.981380519 |
|
|
Sep 04 04:59:33 PM UTC 24 |
Sep 04 05:02:24 PM UTC 24 |
16699178858 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.3879997937 |
|
|
Sep 04 04:59:14 PM UTC 24 |
Sep 04 05:02:38 PM UTC 24 |
84537121352 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.3184026403 |
|
|
Sep 04 04:58:37 PM UTC 24 |
Sep 04 05:03:17 PM UTC 24 |
6938339350 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.3579999914 |
|
|
Sep 04 05:00:15 PM UTC 24 |
Sep 04 05:03:33 PM UTC 24 |
7565878430 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.2916736162 |
|
|
Sep 04 04:59:06 PM UTC 24 |
Sep 04 05:03:38 PM UTC 24 |
45342524065 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.1173701261 |
|
|
Sep 04 05:00:26 PM UTC 24 |
Sep 04 05:04:37 PM UTC 24 |
65770826616 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.2128974346 |
|
|
Sep 04 04:58:15 PM UTC 24 |
Sep 04 05:05:14 PM UTC 24 |
26789268272 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.3518223937 |
|
|
Sep 04 04:59:50 PM UTC 24 |
Sep 04 05:05:20 PM UTC 24 |
30135648984 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2308242301 |
|
|
Sep 04 04:58:23 PM UTC 24 |
Sep 04 05:06:07 PM UTC 24 |
62393668632 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.610304969 |
|
|
Sep 04 04:59:42 PM UTC 24 |
Sep 04 05:06:36 PM UTC 24 |
53327739189 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.1651319745 |
|
|
Sep 04 04:56:19 PM UTC 24 |
Sep 04 05:08:59 PM UTC 24 |
21687449390 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.1598719164 |
|
|
Sep 04 04:57:05 PM UTC 24 |
Sep 04 05:12:32 PM UTC 24 |
107936438455 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.989368259 |
|
|
Sep 04 04:46:31 PM UTC 24 |
Sep 04 04:46:35 PM UTC 24 |
524337514 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3667549319 |
|
|
Sep 04 04:46:37 PM UTC 24 |
Sep 04 04:46:40 PM UTC 24 |
258845067 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.742097720 |
|
|
Sep 04 04:46:37 PM UTC 24 |
Sep 04 04:46:51 PM UTC 24 |
694723211 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2312096666 |
|
|
Sep 04 04:46:49 PM UTC 24 |
Sep 04 04:46:51 PM UTC 24 |
31694973 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.970059111 |
|
|
Sep 04 04:46:52 PM UTC 24 |
Sep 04 04:46:55 PM UTC 24 |
1100595472 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.957957839 |
|
|
Sep 04 04:46:53 PM UTC 24 |
Sep 04 04:46:56 PM UTC 24 |
357764442 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1940534000 |
|
|
Sep 04 04:46:57 PM UTC 24 |
Sep 04 04:46:59 PM UTC 24 |
52720500 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1079369426 |
|
|
Sep 04 04:46:40 PM UTC 24 |
Sep 04 04:47:00 PM UTC 24 |
734217045 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2204984440 |
|
|
Sep 04 04:46:55 PM UTC 24 |
Sep 04 04:47:00 PM UTC 24 |
44076870 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3370705117 |
|
|
Sep 04 04:46:56 PM UTC 24 |
Sep 04 04:47:01 PM UTC 24 |
252852584 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.975331837 |
|
|
Sep 04 04:47:00 PM UTC 24 |
Sep 04 04:47:03 PM UTC 24 |
18561179 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2194988531 |
|
|
Sep 04 04:47:00 PM UTC 24 |
Sep 04 04:47:04 PM UTC 24 |
27574199 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3100673197 |
|
|
Sep 04 04:47:01 PM UTC 24 |
Sep 04 04:47:04 PM UTC 24 |
17121331 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2701358280 |
|
|
Sep 04 04:47:02 PM UTC 24 |
Sep 04 04:47:05 PM UTC 24 |
36162103 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2590709459 |
|
|
Sep 04 04:47:04 PM UTC 24 |
Sep 04 04:47:08 PM UTC 24 |
33294221 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.4089619091 |
|
|
Sep 04 04:47:05 PM UTC 24 |
Sep 04 04:47:08 PM UTC 24 |
202127310 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1866071098 |
|
|
Sep 04 04:47:05 PM UTC 24 |
Sep 04 04:47:08 PM UTC 24 |
274831396 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3917991669 |
|
|
Sep 04 04:47:09 PM UTC 24 |
Sep 04 04:47:12 PM UTC 24 |
53669520 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2148804875 |
|
|
Sep 04 04:47:09 PM UTC 24 |
Sep 04 04:47:14 PM UTC 24 |
3173102105 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.209541870 |
|
|
Sep 04 04:47:09 PM UTC 24 |
Sep 04 04:47:15 PM UTC 24 |
138125939 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3689467491 |
|
|
Sep 04 04:47:12 PM UTC 24 |
Sep 04 04:47:16 PM UTC 24 |
77128632 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1439903296 |
|
|
Sep 04 04:47:16 PM UTC 24 |
Sep 04 04:47:19 PM UTC 24 |
14257305 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1031530263 |
|
|
Sep 04 04:47:15 PM UTC 24 |
Sep 04 04:47:19 PM UTC 24 |
476293647 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2708819109 |
|
|
Sep 04 04:47:17 PM UTC 24 |
Sep 04 04:47:20 PM UTC 24 |
13399607 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2396450223 |
|
|
Sep 04 04:47:19 PM UTC 24 |
Sep 04 04:47:22 PM UTC 24 |
174317759 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2650560431 |
|
|
Sep 04 04:47:20 PM UTC 24 |
Sep 04 04:47:22 PM UTC 24 |
35137066 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.294594023 |
|
|
Sep 04 04:47:20 PM UTC 24 |
Sep 04 04:47:22 PM UTC 24 |
22338412 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.655839729 |
|
|
Sep 04 04:47:15 PM UTC 24 |
Sep 04 04:47:23 PM UTC 24 |
232703453 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2062279603 |
|
|
Sep 04 04:47:21 PM UTC 24 |
Sep 04 04:47:23 PM UTC 24 |
51060052 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3015733839 |
|
|
Sep 04 04:47:23 PM UTC 24 |
Sep 04 04:47:26 PM UTC 24 |
43074341 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2368289064 |
|
|
Sep 04 04:47:24 PM UTC 24 |
Sep 04 04:47:27 PM UTC 24 |
26434911 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3933599011 |
|
|
Sep 04 04:47:23 PM UTC 24 |
Sep 04 04:47:27 PM UTC 24 |
79976073 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2391106037 |
|
|
Sep 04 04:47:27 PM UTC 24 |
Sep 04 04:47:31 PM UTC 24 |
78820009 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3781360302 |
|
|
Sep 04 04:47:26 PM UTC 24 |
Sep 04 04:47:31 PM UTC 24 |
484926609 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1881492374 |
|
|
Sep 04 04:47:28 PM UTC 24 |
Sep 04 04:47:32 PM UTC 24 |
51337546 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3207725201 |
|
|
Sep 04 04:47:32 PM UTC 24 |
Sep 04 04:47:34 PM UTC 24 |
29915078 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3499913522 |
|
|
Sep 04 04:47:06 PM UTC 24 |
Sep 04 04:47:34 PM UTC 24 |
13513369989 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2572502935 |
|
|
Sep 04 04:47:33 PM UTC 24 |
Sep 04 04:47:35 PM UTC 24 |
30514032 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3517070182 |
|
|
Sep 04 04:47:32 PM UTC 24 |
Sep 04 04:47:36 PM UTC 24 |
65179945 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.192137564 |
|
|
Sep 04 04:47:35 PM UTC 24 |
Sep 04 04:47:37 PM UTC 24 |
22230761 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.176930428 |
|
|
Sep 04 04:47:35 PM UTC 24 |
Sep 04 04:47:38 PM UTC 24 |
425658778 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1683243312 |
|
|
Sep 04 04:47:36 PM UTC 24 |
Sep 04 04:47:39 PM UTC 24 |
74540646 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1025060590 |
|
|
Sep 04 04:47:37 PM UTC 24 |
Sep 04 04:47:40 PM UTC 24 |
51726600 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.123079668 |
|
|
Sep 04 04:47:24 PM UTC 24 |
Sep 04 04:47:43 PM UTC 24 |
2547652054 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2824195070 |
|
|
Sep 04 04:47:40 PM UTC 24 |
Sep 04 04:47:43 PM UTC 24 |
48364719 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3654571739 |
|
|
Sep 04 04:47:41 PM UTC 24 |
Sep 04 04:47:44 PM UTC 24 |
51240293 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1632913560 |
|
|
Sep 04 04:47:40 PM UTC 24 |
Sep 04 04:47:45 PM UTC 24 |
191168192 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3498038692 |
|
|
Sep 04 04:47:23 PM UTC 24 |
Sep 04 04:47:46 PM UTC 24 |
768146156 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.4250700536 |
|
|
Sep 04 04:47:38 PM UTC 24 |
Sep 04 04:47:47 PM UTC 24 |
399564948 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.491085691 |
|
|
Sep 04 04:47:44 PM UTC 24 |
Sep 04 04:47:48 PM UTC 24 |
69981431 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4051603297 |
|
|
Sep 04 04:47:44 PM UTC 24 |
Sep 04 04:47:49 PM UTC 24 |
78892649 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2229681057 |
|
|
Sep 04 04:47:47 PM UTC 24 |
Sep 04 04:47:50 PM UTC 24 |
25816241 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.320334431 |
|
|
Sep 04 04:47:46 PM UTC 24 |
Sep 04 04:47:50 PM UTC 24 |
63109439 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.488763407 |
|
|
Sep 04 04:47:45 PM UTC 24 |
Sep 04 04:47:50 PM UTC 24 |
71893351 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.550707810 |
|
|
Sep 04 04:47:48 PM UTC 24 |
Sep 04 04:47:50 PM UTC 24 |
31652479 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3757743416 |
|
|
Sep 04 04:47:49 PM UTC 24 |
Sep 04 04:47:52 PM UTC 24 |
19332833 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1536679810 |
|
|
Sep 04 04:47:49 PM UTC 24 |
Sep 04 04:47:53 PM UTC 24 |
135426120 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2023058989 |
|
|
Sep 04 04:47:50 PM UTC 24 |
Sep 04 04:47:53 PM UTC 24 |
83213643 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.317211534 |
|
|
Sep 04 04:47:50 PM UTC 24 |
Sep 04 04:47:53 PM UTC 24 |
28361100 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1829226547 |
|
|
Sep 04 04:47:51 PM UTC 24 |
Sep 04 04:47:54 PM UTC 24 |
55052678 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.610022532 |
|
|
Sep 04 04:47:52 PM UTC 24 |
Sep 04 04:47:55 PM UTC 24 |
74114927 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1291050458 |
|
|
Sep 04 04:47:54 PM UTC 24 |
Sep 04 04:47:56 PM UTC 24 |
84001427 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4198779131 |
|
|
Sep 04 04:47:54 PM UTC 24 |
Sep 04 04:47:58 PM UTC 24 |
463288717 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3974774416 |
|
|
Sep 04 04:47:55 PM UTC 24 |
Sep 04 04:47:58 PM UTC 24 |
142724607 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.554083623 |
|
|
Sep 04 04:47:57 PM UTC 24 |
Sep 04 04:48:01 PM UTC 24 |
902166802 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2975199507 |
|
|
Sep 04 04:47:56 PM UTC 24 |
Sep 04 04:48:01 PM UTC 24 |
272516757 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.254018987 |
|
|
Sep 04 04:47:58 PM UTC 24 |
Sep 04 04:48:01 PM UTC 24 |
60401875 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2705495346 |
|
|
Sep 04 04:47:59 PM UTC 24 |
Sep 04 04:48:02 PM UTC 24 |
94196630 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3614829223 |
|
|
Sep 04 04:48:00 PM UTC 24 |
Sep 04 04:48:03 PM UTC 24 |
51906437 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.562268764 |
|
|
Sep 04 04:48:02 PM UTC 24 |
Sep 04 04:48:05 PM UTC 24 |
50723106 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3860228671 |
|
|
Sep 04 04:48:02 PM UTC 24 |
Sep 04 04:48:05 PM UTC 24 |
36826128 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.925032921 |
|
|
Sep 04 04:48:02 PM UTC 24 |
Sep 04 04:48:05 PM UTC 24 |
15157175 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2162030405 |
|
|
Sep 04 04:47:53 PM UTC 24 |
Sep 04 04:48:05 PM UTC 24 |
2157858417 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1090216489 |
|
|
Sep 04 04:47:54 PM UTC 24 |
Sep 04 04:48:06 PM UTC 24 |
5668280312 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3906241136 |
|
|
Sep 04 04:48:04 PM UTC 24 |
Sep 04 04:48:08 PM UTC 24 |
75051604 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2845475188 |
|
|
Sep 04 04:48:07 PM UTC 24 |
Sep 04 04:48:11 PM UTC 24 |
41301115 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1272610659 |
|
|
Sep 04 04:48:06 PM UTC 24 |
Sep 04 04:48:10 PM UTC 24 |
43646403 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3373118117 |
|
|
Sep 04 04:48:06 PM UTC 24 |
Sep 04 04:48:10 PM UTC 24 |
1230310999 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4261414696 |
|
|
Sep 04 04:48:03 PM UTC 24 |
Sep 04 04:48:11 PM UTC 24 |
951870014 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1978066755 |
|
|
Sep 04 04:48:07 PM UTC 24 |
Sep 04 04:48:12 PM UTC 24 |
70412582 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2603869685 |
|
|
Sep 04 04:48:11 PM UTC 24 |
Sep 04 04:48:13 PM UTC 24 |
15449173 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1334219909 |
|
|
Sep 04 04:48:12 PM UTC 24 |
Sep 04 04:48:14 PM UTC 24 |
48179433 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2901295804 |
|
|
Sep 04 04:48:12 PM UTC 24 |
Sep 04 04:48:15 PM UTC 24 |
24453385 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1627493325 |
|
|
Sep 04 04:48:08 PM UTC 24 |
Sep 04 04:48:15 PM UTC 24 |
814197609 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3329955993 |
|
|
Sep 04 04:48:13 PM UTC 24 |
Sep 04 04:48:17 PM UTC 24 |
372730600 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.821703293 |
|
|
Sep 04 04:48:16 PM UTC 24 |
Sep 04 04:48:19 PM UTC 24 |
386772390 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2393531127 |
|
|
Sep 04 04:48:06 PM UTC 24 |
Sep 04 04:48:19 PM UTC 24 |
1804755356 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2810783137 |
|
|
Sep 04 04:48:13 PM UTC 24 |
Sep 04 04:48:19 PM UTC 24 |
106461996 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1551495195 |
|
|
Sep 04 04:47:40 PM UTC 24 |
Sep 04 04:48:20 PM UTC 24 |
4806583061 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1977230832 |
|
|
Sep 04 04:48:16 PM UTC 24 |
Sep 04 04:48:20 PM UTC 24 |
1122623430 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1841385410 |
|
|
Sep 04 04:48:18 PM UTC 24 |
Sep 04 04:48:21 PM UTC 24 |
290832765 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1130039841 |
|
|
Sep 04 04:48:20 PM UTC 24 |
Sep 04 04:48:23 PM UTC 24 |
47840327 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3025250175 |
|
|
Sep 04 04:48:15 PM UTC 24 |
Sep 04 04:48:23 PM UTC 24 |
524098646 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1675138562 |
|
|
Sep 04 04:48:20 PM UTC 24 |
Sep 04 04:48:23 PM UTC 24 |
74262912 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3753531030 |
|
|
Sep 04 04:48:19 PM UTC 24 |
Sep 04 04:48:24 PM UTC 24 |
41235228 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.425249372 |
|
|
Sep 04 04:48:19 PM UTC 24 |
Sep 04 04:48:25 PM UTC 24 |
407106777 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1847896314 |
|
|
Sep 04 04:48:21 PM UTC 24 |
Sep 04 04:48:25 PM UTC 24 |
288549015 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1338886765 |
|
|
Sep 04 04:48:22 PM UTC 24 |
Sep 04 04:48:25 PM UTC 24 |
698316899 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3811275959 |
|
|
Sep 04 04:48:22 PM UTC 24 |
Sep 04 04:48:27 PM UTC 24 |
483733705 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3281428562 |
|
|
Sep 04 04:48:24 PM UTC 24 |
Sep 04 04:48:27 PM UTC 24 |
48057342 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3948189109 |
|
|
Sep 04 04:48:25 PM UTC 24 |
Sep 04 04:48:27 PM UTC 24 |
60685473 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1842723470 |
|
|
Sep 04 04:48:25 PM UTC 24 |
Sep 04 04:48:28 PM UTC 24 |
73834618 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4240106845 |
|
|
Sep 04 04:48:27 PM UTC 24 |
Sep 04 04:48:29 PM UTC 24 |
36282251 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2934868922 |
|
|
Sep 04 04:48:06 PM UTC 24 |
Sep 04 04:48:30 PM UTC 24 |
1786477336 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3058743189 |
|
|
Sep 04 04:48:26 PM UTC 24 |
Sep 04 04:48:30 PM UTC 24 |
43749668 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.154764088 |
|
|
Sep 04 04:48:26 PM UTC 24 |
Sep 04 04:48:31 PM UTC 24 |
118248060 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3244204555 |
|
|
Sep 04 04:48:28 PM UTC 24 |
Sep 04 04:48:31 PM UTC 24 |
38930825 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2115554702 |
|
|
Sep 04 04:48:28 PM UTC 24 |
Sep 04 04:48:31 PM UTC 24 |
201460003 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.55431626 |
|
|
Sep 04 04:48:24 PM UTC 24 |
Sep 04 04:48:32 PM UTC 24 |
424324152 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.926572200 |
|
|
Sep 04 04:48:29 PM UTC 24 |
Sep 04 04:48:33 PM UTC 24 |
66302624 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1556477574 |
|
|
Sep 04 04:48:31 PM UTC 24 |
Sep 04 04:48:33 PM UTC 24 |
38472077 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.417317237 |
|
|
Sep 04 04:48:24 PM UTC 24 |
Sep 04 04:48:34 PM UTC 24 |
2338704007 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1714407987 |
|
|
Sep 04 04:48:14 PM UTC 24 |
Sep 04 04:48:35 PM UTC 24 |
26467030341 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3660036254 |
|
|
Sep 04 04:48:32 PM UTC 24 |
Sep 04 04:48:35 PM UTC 24 |
26876881 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1726686796 |
|
|
Sep 04 04:48:34 PM UTC 24 |
Sep 04 04:48:36 PM UTC 24 |
92229651 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1016062862 |
|
|
Sep 04 04:48:33 PM UTC 24 |
Sep 04 04:48:37 PM UTC 24 |
236277877 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2590204265 |
|
|
Sep 04 04:48:35 PM UTC 24 |
Sep 04 04:48:38 PM UTC 24 |
18947423 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4026768068 |
|
|
Sep 04 04:48:52 PM UTC 24 |
Sep 04 04:48:55 PM UTC 24 |
40000149 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3517310801 |
|
|
Sep 04 04:48:33 PM UTC 24 |
Sep 04 04:48:38 PM UTC 24 |
113943630 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2226157513 |
|
|
Sep 04 04:48:35 PM UTC 24 |
Sep 04 04:48:38 PM UTC 24 |
20666995 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1486580418 |
|
|
Sep 04 04:48:34 PM UTC 24 |
Sep 04 04:48:39 PM UTC 24 |
101442173 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3035487110 |
|
|
Sep 04 04:48:36 PM UTC 24 |
Sep 04 04:48:39 PM UTC 24 |
363734708 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3963269381 |
|
|
Sep 04 04:48:32 PM UTC 24 |
Sep 04 04:48:40 PM UTC 24 |
179218569 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.715506764 |
|
|
Sep 04 04:48:37 PM UTC 24 |
Sep 04 04:48:41 PM UTC 24 |
39611398 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.630644949 |
|
|
Sep 04 04:48:31 PM UTC 24 |
Sep 04 04:48:41 PM UTC 24 |
961621971 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.200787156 |
|
|
Sep 04 04:48:38 PM UTC 24 |
Sep 04 04:48:41 PM UTC 24 |
20055062 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1121874163 |
|
|
Sep 04 04:48:40 PM UTC 24 |
Sep 04 04:48:43 PM UTC 24 |
120195151 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.188608641 |
|
|
Sep 04 04:48:40 PM UTC 24 |
Sep 04 04:48:44 PM UTC 24 |
335929857 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1183053634 |
|
|
Sep 04 04:48:31 PM UTC 24 |
Sep 04 04:48:44 PM UTC 24 |
4553209953 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.671411941 |
|
|
Sep 04 04:48:42 PM UTC 24 |
Sep 04 04:48:44 PM UTC 24 |
43346447 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1580669310 |
|
|
Sep 04 04:48:41 PM UTC 24 |
Sep 04 04:48:45 PM UTC 24 |
207488711 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1606545100 |
|
|
Sep 04 04:48:42 PM UTC 24 |
Sep 04 04:48:45 PM UTC 24 |
26843867 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1313736530 |
|
|
Sep 04 04:48:41 PM UTC 24 |
Sep 04 04:48:45 PM UTC 24 |
158514915 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1651664440 |
|
|
Sep 04 04:48:42 PM UTC 24 |
Sep 04 04:48:45 PM UTC 24 |
36616549 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4137261253 |
|
|
Sep 04 04:48:37 PM UTC 24 |
Sep 04 04:48:46 PM UTC 24 |
844136110 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.926405645 |
|
|
Sep 04 04:48:44 PM UTC 24 |
Sep 04 04:48:47 PM UTC 24 |
39324456 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.526019532 |
|
|
Sep 04 04:48:45 PM UTC 24 |
Sep 04 04:48:48 PM UTC 24 |
61747109 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1791155726 |
|
|
Sep 04 04:48:45 PM UTC 24 |
Sep 04 04:48:48 PM UTC 24 |
14886834 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1972098878 |
|
|
Sep 04 04:48:45 PM UTC 24 |
Sep 04 04:48:48 PM UTC 24 |
158537626 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.860251266 |
|
|
Sep 04 04:48:45 PM UTC 24 |
Sep 04 04:48:49 PM UTC 24 |
94868939 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1332355616 |
|
|
Sep 04 04:48:46 PM UTC 24 |
Sep 04 04:48:49 PM UTC 24 |
13108519 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2204627914 |
|
|
Sep 04 04:48:48 PM UTC 24 |
Sep 04 04:48:50 PM UTC 24 |
28284065 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2703879111 |
|
|
Sep 04 04:48:49 PM UTC 24 |
Sep 04 04:48:51 PM UTC 24 |
66814881 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1037725619 |
|
|
Sep 04 04:48:49 PM UTC 24 |
Sep 04 04:48:51 PM UTC 24 |
169042461 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1694790057 |
|
|
Sep 04 04:48:45 PM UTC 24 |
Sep 04 04:48:51 PM UTC 24 |
166947520 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1422190209 |
|
|
Sep 04 04:48:38 PM UTC 24 |
Sep 04 04:48:52 PM UTC 24 |
1247179016 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3344468473 |
|
|
Sep 04 04:48:50 PM UTC 24 |
Sep 04 04:48:52 PM UTC 24 |
125813566 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3877797928 |
|
|
Sep 04 04:48:50 PM UTC 24 |
Sep 04 04:48:53 PM UTC 24 |
249651123 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4060976599 |
|
|
Sep 04 04:48:49 PM UTC 24 |
Sep 04 04:48:54 PM UTC 24 |
851655140 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4260082677 |
|
|
Sep 04 04:48:52 PM UTC 24 |
Sep 04 04:48:54 PM UTC 24 |
13609899 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2907321219 |
|
|
Sep 04 04:48:46 PM UTC 24 |
Sep 04 04:48:54 PM UTC 24 |
435635044 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3084092638 |
|
|
Sep 04 04:48:51 PM UTC 24 |
Sep 04 04:48:55 PM UTC 24 |
343581127 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3358178788 |
|
|
Sep 04 04:48:53 PM UTC 24 |
Sep 04 04:48:56 PM UTC 24 |
103483610 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2625503199 |
|
|
Sep 04 04:48:49 PM UTC 24 |
Sep 04 04:48:56 PM UTC 24 |
236284295 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4215326490 |
|
|
Sep 04 04:48:54 PM UTC 24 |
Sep 04 04:48:57 PM UTC 24 |
13859690 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.108660310 |
|
|
Sep 04 04:48:53 PM UTC 24 |
Sep 04 04:48:57 PM UTC 24 |
351548878 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2307411816 |
|
|
Sep 04 04:48:53 PM UTC 24 |
Sep 04 04:48:58 PM UTC 24 |
51190980 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3183843381 |
|
|
Sep 04 04:48:52 PM UTC 24 |
Sep 04 04:48:58 PM UTC 24 |
301415222 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3135089287 |
|
|
Sep 04 04:48:55 PM UTC 24 |
Sep 04 04:48:58 PM UTC 24 |
29362079 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3490100698 |
|
|
Sep 04 04:48:57 PM UTC 24 |
Sep 04 04:48:59 PM UTC 24 |
31203717 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.629452318 |
|
|
Sep 04 04:48:56 PM UTC 24 |
Sep 04 04:48:59 PM UTC 24 |
102689988 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1021279138 |
|
|
Sep 04 04:48:57 PM UTC 24 |
Sep 04 04:49:00 PM UTC 24 |
349534463 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3935330865 |
|
|
Sep 04 04:48:58 PM UTC 24 |
Sep 04 04:49:01 PM UTC 24 |
44887243 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3931587480 |
|
|
Sep 04 04:48:59 PM UTC 24 |
Sep 04 04:49:02 PM UTC 24 |
35657278 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1342296802 |
|
|
Sep 04 04:48:59 PM UTC 24 |
Sep 04 04:49:02 PM UTC 24 |
17750949 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3959194096 |
|
|
Sep 04 04:48:59 PM UTC 24 |
Sep 04 04:49:02 PM UTC 24 |
90433776 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1109973948 |
|
|
Sep 04 04:48:56 PM UTC 24 |
Sep 04 04:49:02 PM UTC 24 |
422557814 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2182757862 |
|
|
Sep 04 04:49:01 PM UTC 24 |
Sep 04 04:49:03 PM UTC 24 |
19372601 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.33585532 |
|
|
Sep 04 04:48:56 PM UTC 24 |
Sep 04 04:49:03 PM UTC 24 |
225979602 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2316374151 |
|
|
Sep 04 04:48:59 PM UTC 24 |
Sep 04 04:49:04 PM UTC 24 |
85631820 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1733391880 |
|
|
Sep 04 04:49:02 PM UTC 24 |
Sep 04 04:49:04 PM UTC 24 |
51996520 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3310374592 |
|
|
Sep 04 04:48:58 PM UTC 24 |
Sep 04 04:49:04 PM UTC 24 |
205670528 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3415440997 |
|
|
Sep 04 04:49:00 PM UTC 24 |
Sep 04 04:49:04 PM UTC 24 |
525395455 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2320389619 |
|
|
Sep 04 04:49:03 PM UTC 24 |
Sep 04 04:49:05 PM UTC 24 |
13329616 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2162347845 |
|
|
Sep 04 04:49:03 PM UTC 24 |
Sep 04 04:49:05 PM UTC 24 |
17403897 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2640251481 |
|
|
Sep 04 04:49:00 PM UTC 24 |
Sep 04 04:49:06 PM UTC 24 |
434298940 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3251353501 |
|
|
Sep 04 04:49:03 PM UTC 24 |
Sep 04 04:49:07 PM UTC 24 |
44311927 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4282911911 |
|
|
Sep 04 04:49:04 PM UTC 24 |
Sep 04 04:49:07 PM UTC 24 |
95477887 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.190928870 |
|
|
Sep 04 04:49:05 PM UTC 24 |
Sep 04 04:49:07 PM UTC 24 |
17348122 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2267023093 |
|
|
Sep 04 04:49:04 PM UTC 24 |
Sep 04 04:49:07 PM UTC 24 |
179810523 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2134596187 |
|
|
Sep 04 04:49:05 PM UTC 24 |
Sep 04 04:49:08 PM UTC 24 |
46253093 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.71905474 |
|
|
Sep 04 04:49:05 PM UTC 24 |
Sep 04 04:49:08 PM UTC 24 |
38710652 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3415208641 |
|
|
Sep 04 04:49:06 PM UTC 24 |
Sep 04 04:49:09 PM UTC 24 |
21676951 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.395820853 |
|
|
Sep 04 04:49:03 PM UTC 24 |
Sep 04 04:49:10 PM UTC 24 |
473911061 ps |