| T576 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2117359257 |
|
|
Sep 09 10:31:54 PM UTC 24 |
Sep 09 10:32:12 PM UTC 24 |
1797101336 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.2495001995 |
|
|
Sep 09 10:32:09 PM UTC 24 |
Sep 09 10:32:13 PM UTC 24 |
29237917 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_errors.1789935180 |
|
|
Sep 09 10:32:00 PM UTC 24 |
Sep 09 10:32:13 PM UTC 24 |
373918866 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.1778071490 |
|
|
Sep 09 10:30:09 PM UTC 24 |
Sep 09 10:32:13 PM UTC 24 |
7481932373 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.95543436 |
|
|
Sep 09 10:32:00 PM UTC 24 |
Sep 09 10:32:13 PM UTC 24 |
132073427 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.1776623151 |
|
|
Sep 09 10:31:51 PM UTC 24 |
Sep 09 10:32:14 PM UTC 24 |
1355131670 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.694594951 |
|
|
Sep 09 10:32:01 PM UTC 24 |
Sep 09 10:32:14 PM UTC 24 |
1269515689 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.364609483 |
|
|
Sep 09 10:32:15 PM UTC 24 |
Sep 09 10:32:17 PM UTC 24 |
88841382 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1895047438 |
|
|
Sep 09 10:32:15 PM UTC 24 |
Sep 09 10:32:17 PM UTC 24 |
68312541 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.260117958 |
|
|
Sep 09 10:32:09 PM UTC 24 |
Sep 09 10:32:18 PM UTC 24 |
80579758 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.299075676 |
|
|
Sep 09 10:31:56 PM UTC 24 |
Sep 09 10:32:19 PM UTC 24 |
2222237191 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.2070825227 |
|
|
Sep 09 10:31:11 PM UTC 24 |
Sep 09 10:32:19 PM UTC 24 |
11674045134 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.751568819 |
|
|
Sep 09 10:32:15 PM UTC 24 |
Sep 09 10:32:19 PM UTC 24 |
44636370 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.2454972703 |
|
|
Sep 09 10:32:04 PM UTC 24 |
Sep 09 10:32:21 PM UTC 24 |
518935285 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.3222099569 |
|
|
Sep 09 10:32:11 PM UTC 24 |
Sep 09 10:32:22 PM UTC 24 |
1798693020 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.4144202839 |
|
|
Sep 09 10:32:10 PM UTC 24 |
Sep 09 10:32:22 PM UTC 24 |
840056821 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.4065071950 |
|
|
Sep 09 10:32:13 PM UTC 24 |
Sep 09 10:32:22 PM UTC 24 |
988993328 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.2059895924 |
|
|
Sep 09 10:31:54 PM UTC 24 |
Sep 09 10:32:24 PM UTC 24 |
4102815604 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.1949230674 |
|
|
Sep 09 10:32:18 PM UTC 24 |
Sep 09 10:32:24 PM UTC 24 |
80969873 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.1818858132 |
|
|
Sep 09 10:32:05 PM UTC 24 |
Sep 09 10:32:25 PM UTC 24 |
408707817 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.3273623299 |
|
|
Sep 09 10:32:13 PM UTC 24 |
Sep 09 10:32:25 PM UTC 24 |
258986387 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_errors.2366570184 |
|
|
Sep 09 10:32:09 PM UTC 24 |
Sep 09 10:32:25 PM UTC 24 |
1775067766 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.696010857 |
|
|
Sep 09 10:32:13 PM UTC 24 |
Sep 09 10:32:25 PM UTC 24 |
1408561190 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.3186029940 |
|
|
Sep 09 10:32:04 PM UTC 24 |
Sep 09 10:32:26 PM UTC 24 |
635400269 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.2182307000 |
|
|
Sep 09 10:32:24 PM UTC 24 |
Sep 09 10:32:27 PM UTC 24 |
61604052 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2168455922 |
|
|
Sep 09 10:32:26 PM UTC 24 |
Sep 09 10:32:28 PM UTC 24 |
44849264 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.3635761643 |
|
|
Sep 09 10:32:18 PM UTC 24 |
Sep 09 10:32:29 PM UTC 24 |
172673072 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.4098750916 |
|
|
Sep 09 10:32:21 PM UTC 24 |
Sep 09 10:32:30 PM UTC 24 |
317683236 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.37637340 |
|
|
Sep 09 10:32:26 PM UTC 24 |
Sep 09 10:32:30 PM UTC 24 |
132754800 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.20284599 |
|
|
Sep 09 10:32:26 PM UTC 24 |
Sep 09 10:32:33 PM UTC 24 |
1463399508 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.2522765076 |
|
|
Sep 09 10:32:22 PM UTC 24 |
Sep 09 10:32:33 PM UTC 24 |
4280529245 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.2488964984 |
|
|
Sep 09 10:32:46 PM UTC 24 |
Sep 09 10:32:51 PM UTC 24 |
305719596 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.2809403763 |
|
|
Sep 09 10:31:58 PM UTC 24 |
Sep 09 10:32:34 PM UTC 24 |
385566749 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.1526184664 |
|
|
Sep 09 10:32:19 PM UTC 24 |
Sep 09 10:32:35 PM UTC 24 |
1834741369 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.1741706650 |
|
|
Sep 09 10:30:47 PM UTC 24 |
Sep 09 10:32:36 PM UTC 24 |
5265849198 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.2922509908 |
|
|
Sep 09 10:32:30 PM UTC 24 |
Sep 09 10:32:37 PM UTC 24 |
1123782556 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.552683406 |
|
|
Sep 09 10:32:36 PM UTC 24 |
Sep 09 10:32:38 PM UTC 24 |
16414889 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.928799682 |
|
|
Sep 09 10:32:36 PM UTC 24 |
Sep 09 10:32:39 PM UTC 24 |
12650477 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.210140054 |
|
|
Sep 09 10:32:26 PM UTC 24 |
Sep 09 10:32:39 PM UTC 24 |
66042029 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.840237155 |
|
|
Sep 09 10:32:21 PM UTC 24 |
Sep 09 10:32:39 PM UTC 24 |
1315841371 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.2594338632 |
|
|
Sep 09 10:32:36 PM UTC 24 |
Sep 09 10:32:39 PM UTC 24 |
262716507 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.2108044050 |
|
|
Sep 09 10:27:24 PM UTC 24 |
Sep 09 10:32:39 PM UTC 24 |
15471000750 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.1885792138 |
|
|
Sep 09 10:32:28 PM UTC 24 |
Sep 09 10:32:40 PM UTC 24 |
1064889119 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.3582226483 |
|
|
Sep 09 10:32:31 PM UTC 24 |
Sep 09 10:32:41 PM UTC 24 |
172267853 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.4021265107 |
|
|
Sep 09 10:32:09 PM UTC 24 |
Sep 09 10:32:42 PM UTC 24 |
299622871 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.2597228608 |
|
|
Sep 09 10:29:55 PM UTC 24 |
Sep 09 10:32:43 PM UTC 24 |
4304381680 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.3773605738 |
|
|
Sep 09 10:32:30 PM UTC 24 |
Sep 09 10:32:44 PM UTC 24 |
1163323642 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.131378915 |
|
|
Sep 09 10:32:42 PM UTC 24 |
Sep 09 10:32:44 PM UTC 24 |
13986168 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.1881856931 |
|
|
Sep 09 10:32:38 PM UTC 24 |
Sep 09 10:32:44 PM UTC 24 |
100614669 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_errors.1320417016 |
|
|
Sep 09 10:32:19 PM UTC 24 |
Sep 09 10:32:44 PM UTC 24 |
801060975 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3453058079 |
|
|
Sep 09 10:32:44 PM UTC 24 |
Sep 09 10:32:46 PM UTC 24 |
13995630 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.1250677162 |
|
|
Sep 09 10:32:31 PM UTC 24 |
Sep 09 10:32:47 PM UTC 24 |
826571156 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.4272615323 |
|
|
Sep 09 10:32:44 PM UTC 24 |
Sep 09 10:32:48 PM UTC 24 |
37680239 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.2874305402 |
|
|
Sep 09 10:32:16 PM UTC 24 |
Sep 09 10:32:48 PM UTC 24 |
975216193 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.1483212664 |
|
|
Sep 09 10:32:23 PM UTC 24 |
Sep 09 10:32:48 PM UTC 24 |
3667014758 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.247262304 |
|
|
Sep 09 10:32:38 PM UTC 24 |
Sep 09 10:32:50 PM UTC 24 |
73814584 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.4246868394 |
|
|
Sep 09 10:33:31 PM UTC 24 |
Sep 09 10:33:38 PM UTC 24 |
191979761 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.1107725598 |
|
|
Sep 09 10:32:40 PM UTC 24 |
Sep 09 10:32:53 PM UTC 24 |
2121209538 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.3995594172 |
|
|
Sep 09 10:32:40 PM UTC 24 |
Sep 09 10:32:53 PM UTC 24 |
306098861 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.2573066494 |
|
|
Sep 09 10:32:52 PM UTC 24 |
Sep 09 10:32:54 PM UTC 24 |
73041825 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.745560262 |
|
|
Sep 09 10:31:37 PM UTC 24 |
Sep 09 10:32:54 PM UTC 24 |
2447337464 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.1572312204 |
|
|
Sep 09 10:32:53 PM UTC 24 |
Sep 09 10:32:55 PM UTC 24 |
28176629 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.1010979110 |
|
|
Sep 09 10:32:46 PM UTC 24 |
Sep 09 10:32:56 PM UTC 24 |
57299059 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3813486795 |
|
|
Sep 09 10:32:54 PM UTC 24 |
Sep 09 10:32:57 PM UTC 24 |
33917267 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.3885866925 |
|
|
Sep 09 10:32:47 PM UTC 24 |
Sep 09 10:32:57 PM UTC 24 |
228204366 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.668160161 |
|
|
Sep 09 10:32:40 PM UTC 24 |
Sep 09 10:32:57 PM UTC 24 |
1652945476 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.944132716 |
|
|
Sep 09 10:32:38 PM UTC 24 |
Sep 09 10:32:58 PM UTC 24 |
985982735 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.2170065493 |
|
|
Sep 09 10:31:56 PM UTC 24 |
Sep 09 10:32:58 PM UTC 24 |
1459785828 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.1090573561 |
|
|
Sep 09 10:30:27 PM UTC 24 |
Sep 09 10:32:59 PM UTC 24 |
18367060014 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_errors.3408248529 |
|
|
Sep 09 10:32:46 PM UTC 24 |
Sep 09 10:32:59 PM UTC 24 |
260417269 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.4076624861 |
|
|
Sep 09 10:32:49 PM UTC 24 |
Sep 09 10:32:59 PM UTC 24 |
831325974 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.248743034 |
|
|
Sep 09 10:32:40 PM UTC 24 |
Sep 09 10:33:00 PM UTC 24 |
661314269 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.218180744 |
|
|
Sep 09 10:32:48 PM UTC 24 |
Sep 09 10:33:01 PM UTC 24 |
11969703689 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.4280599063 |
|
|
Sep 09 10:32:56 PM UTC 24 |
Sep 09 10:33:01 PM UTC 24 |
72738080 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.1403056911 |
|
|
Sep 09 10:32:40 PM UTC 24 |
Sep 09 10:33:01 PM UTC 24 |
364675570 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.2188535 |
|
|
Sep 09 10:33:00 PM UTC 24 |
Sep 09 10:33:02 PM UTC 24 |
44799178 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3945866884 |
|
|
Sep 09 10:33:00 PM UTC 24 |
Sep 09 10:33:03 PM UTC 24 |
46528852 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.705192138 |
|
|
Sep 09 10:33:28 PM UTC 24 |
Sep 09 10:33:40 PM UTC 24 |
1690387420 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.4074877723 |
|
|
Sep 09 10:32:48 PM UTC 24 |
Sep 09 10:33:03 PM UTC 24 |
414302174 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.2986904378 |
|
|
Sep 09 10:33:00 PM UTC 24 |
Sep 09 10:33:04 PM UTC 24 |
30020560 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.869757447 |
|
|
Sep 09 10:33:02 PM UTC 24 |
Sep 09 10:33:05 PM UTC 24 |
121133316 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.3466753337 |
|
|
Sep 09 10:32:57 PM UTC 24 |
Sep 09 10:33:07 PM UTC 24 |
378181941 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.3576058866 |
|
|
Sep 09 10:32:57 PM UTC 24 |
Sep 09 10:33:07 PM UTC 24 |
202548557 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.3658827844 |
|
|
Sep 09 10:32:37 PM UTC 24 |
Sep 09 10:33:08 PM UTC 24 |
1285662187 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.1159800945 |
|
|
Sep 09 10:32:49 PM UTC 24 |
Sep 09 10:33:09 PM UTC 24 |
1467470694 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.2540805447 |
|
|
Sep 09 10:32:58 PM UTC 24 |
Sep 09 10:33:09 PM UTC 24 |
246515127 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.634365599 |
|
|
Sep 09 10:33:02 PM UTC 24 |
Sep 09 10:33:10 PM UTC 24 |
87271096 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.3430702547 |
|
|
Sep 09 10:33:04 PM UTC 24 |
Sep 09 10:33:10 PM UTC 24 |
1308467007 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.3046338434 |
|
|
Sep 09 10:32:56 PM UTC 24 |
Sep 09 10:33:11 PM UTC 24 |
70904492 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.2015611463 |
|
|
Sep 09 10:33:33 PM UTC 24 |
Sep 09 10:33:39 PM UTC 24 |
226804375 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.3286927820 |
|
|
Sep 09 10:32:46 PM UTC 24 |
Sep 09 10:33:12 PM UTC 24 |
310506733 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.257470240 |
|
|
Sep 09 10:33:10 PM UTC 24 |
Sep 09 10:33:12 PM UTC 24 |
51648528 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.955383580 |
|
|
Sep 09 10:33:10 PM UTC 24 |
Sep 09 10:33:13 PM UTC 24 |
37335168 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.3122221433 |
|
|
Sep 09 10:32:58 PM UTC 24 |
Sep 09 10:33:13 PM UTC 24 |
2806779504 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.264538967 |
|
|
Sep 09 10:33:10 PM UTC 24 |
Sep 09 10:33:13 PM UTC 24 |
17106483 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.3411804380 |
|
|
Sep 09 10:32:59 PM UTC 24 |
Sep 09 10:33:14 PM UTC 24 |
355465868 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.1407981339 |
|
|
Sep 09 10:33:03 PM UTC 24 |
Sep 09 10:33:15 PM UTC 24 |
187763055 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.1768052192 |
|
|
Sep 09 10:33:12 PM UTC 24 |
Sep 09 10:33:15 PM UTC 24 |
26201227 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.3116790145 |
|
|
Sep 09 10:32:54 PM UTC 24 |
Sep 09 10:33:15 PM UTC 24 |
169629593 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1727029628 |
|
|
Sep 09 10:32:23 PM UTC 24 |
Sep 09 10:33:15 PM UTC 24 |
4438336414 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.582244635 |
|
|
Sep 09 10:33:05 PM UTC 24 |
Sep 09 10:33:15 PM UTC 24 |
774685102 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.4275248970 |
|
|
Sep 09 10:31:39 PM UTC 24 |
Sep 09 10:33:15 PM UTC 24 |
2745054989 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_errors.3443781032 |
|
|
Sep 09 10:32:57 PM UTC 24 |
Sep 09 10:33:16 PM UTC 24 |
400318414 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.2842709643 |
|
|
Sep 09 10:33:30 PM UTC 24 |
Sep 09 10:33:40 PM UTC 24 |
3297217251 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.1811435670 |
|
|
Sep 09 10:33:04 PM UTC 24 |
Sep 09 10:33:17 PM UTC 24 |
550183397 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_errors.2665297899 |
|
|
Sep 09 10:33:03 PM UTC 24 |
Sep 09 10:33:18 PM UTC 24 |
990300015 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.837311601 |
|
|
Sep 09 10:33:16 PM UTC 24 |
Sep 09 10:33:19 PM UTC 24 |
30029705 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.3027067439 |
|
|
Sep 09 10:33:16 PM UTC 24 |
Sep 09 10:33:19 PM UTC 24 |
62990978 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.1666160446 |
|
|
Sep 09 10:33:12 PM UTC 24 |
Sep 09 10:33:21 PM UTC 24 |
158447586 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.1688001352 |
|
|
Sep 09 10:33:13 PM UTC 24 |
Sep 09 10:33:22 PM UTC 24 |
707609228 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.3405065037 |
|
|
Sep 09 10:33:16 PM UTC 24 |
Sep 09 10:33:22 PM UTC 24 |
168601106 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.4234775484 |
|
|
Sep 09 10:33:18 PM UTC 24 |
Sep 09 10:33:22 PM UTC 24 |
134794717 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.1710578370 |
|
|
Sep 09 10:33:06 PM UTC 24 |
Sep 09 10:33:23 PM UTC 24 |
2748975824 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.1884825914 |
|
|
Sep 09 10:33:23 PM UTC 24 |
Sep 09 10:33:26 PM UTC 24 |
22748237 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.67478519 |
|
|
Sep 09 10:33:19 PM UTC 24 |
Sep 09 10:33:27 PM UTC 24 |
328494417 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.2915813703 |
|
|
Sep 09 10:33:15 PM UTC 24 |
Sep 09 10:33:27 PM UTC 24 |
980434464 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.2816014760 |
|
|
Sep 09 10:33:13 PM UTC 24 |
Sep 09 10:33:28 PM UTC 24 |
416854003 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.3667382429 |
|
|
Sep 09 10:33:13 PM UTC 24 |
Sep 09 10:33:28 PM UTC 24 |
616683488 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.538275017 |
|
|
Sep 09 10:33:26 PM UTC 24 |
Sep 09 10:33:28 PM UTC 24 |
25592958 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.3943941298 |
|
|
Sep 09 10:33:20 PM UTC 24 |
Sep 09 10:33:29 PM UTC 24 |
301291820 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_errors.1551248508 |
|
|
Sep 09 10:33:13 PM UTC 24 |
Sep 09 10:33:30 PM UTC 24 |
870930740 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.3337327944 |
|
|
Sep 09 10:33:15 PM UTC 24 |
Sep 09 10:33:30 PM UTC 24 |
378214271 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.1236035267 |
|
|
Sep 09 10:33:19 PM UTC 24 |
Sep 09 10:33:30 PM UTC 24 |
170387871 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.3615031118 |
|
|
Sep 09 10:33:23 PM UTC 24 |
Sep 09 10:33:30 PM UTC 24 |
498934913 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.1552774640 |
|
|
Sep 09 10:33:18 PM UTC 24 |
Sep 09 10:33:31 PM UTC 24 |
607107910 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.179065084 |
|
|
Sep 09 10:33:20 PM UTC 24 |
Sep 09 10:33:31 PM UTC 24 |
3980277361 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.457942062 |
|
|
Sep 09 10:33:41 PM UTC 24 |
Sep 09 10:33:44 PM UTC 24 |
22759203 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.3376031222 |
|
|
Sep 09 10:33:28 PM UTC 24 |
Sep 09 10:33:31 PM UTC 24 |
59955680 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_errors.631416602 |
|
|
Sep 09 10:33:19 PM UTC 24 |
Sep 09 10:33:31 PM UTC 24 |
4348637897 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.3875196041 |
|
|
Sep 09 10:33:22 PM UTC 24 |
Sep 09 10:33:31 PM UTC 24 |
986897424 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.3052561201 |
|
|
Sep 09 10:33:27 PM UTC 24 |
Sep 09 10:33:33 PM UTC 24 |
331603558 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.1635337832 |
|
|
Sep 09 10:33:02 PM UTC 24 |
Sep 09 10:33:33 PM UTC 24 |
253811132 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.4074576013 |
|
|
Sep 09 10:33:31 PM UTC 24 |
Sep 09 10:33:34 PM UTC 24 |
18129717 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.229802472 |
|
|
Sep 09 10:33:28 PM UTC 24 |
Sep 09 10:33:42 PM UTC 24 |
281951091 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.934730553 |
|
|
Sep 09 10:33:12 PM UTC 24 |
Sep 09 10:33:35 PM UTC 24 |
266873835 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.584403376 |
|
|
Sep 09 10:33:17 PM UTC 24 |
Sep 09 10:33:46 PM UTC 24 |
809925242 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.328696979 |
|
|
Sep 09 10:33:44 PM UTC 24 |
Sep 09 10:33:47 PM UTC 24 |
47541667 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.932864391 |
|
|
Sep 09 10:33:41 PM UTC 24 |
Sep 09 10:33:47 PM UTC 24 |
63644702 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.2589630057 |
|
|
Sep 09 10:33:33 PM UTC 24 |
Sep 09 10:33:47 PM UTC 24 |
148144279 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.2004786732 |
|
|
Sep 09 10:33:31 PM UTC 24 |
Sep 09 10:33:48 PM UTC 24 |
318244366 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.1258702604 |
|
|
Sep 09 10:33:36 PM UTC 24 |
Sep 09 10:33:48 PM UTC 24 |
1265047835 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.3459105425 |
|
|
Sep 09 10:33:34 PM UTC 24 |
Sep 09 10:33:49 PM UTC 24 |
3308929678 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.12167556 |
|
|
Sep 09 10:33:45 PM UTC 24 |
Sep 09 10:33:50 PM UTC 24 |
78681360 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.1061559269 |
|
|
Sep 09 10:33:34 PM UTC 24 |
Sep 09 10:33:50 PM UTC 24 |
344505741 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.3214003313 |
|
|
Sep 09 10:33:37 PM UTC 24 |
Sep 09 10:33:51 PM UTC 24 |
622626933 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2228142524 |
|
|
Sep 09 10:33:31 PM UTC 24 |
Sep 09 10:33:52 PM UTC 24 |
397936285 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.471510307 |
|
|
Sep 09 10:33:47 PM UTC 24 |
Sep 09 10:33:53 PM UTC 24 |
530214918 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.1941592754 |
|
|
Sep 09 10:33:34 PM UTC 24 |
Sep 09 10:33:53 PM UTC 24 |
843272398 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.2597654217 |
|
|
Sep 09 10:33:51 PM UTC 24 |
Sep 09 10:33:54 PM UTC 24 |
27534243 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2272092952 |
|
|
Sep 09 10:33:51 PM UTC 24 |
Sep 09 10:33:54 PM UTC 24 |
86329915 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.2505377334 |
|
|
Sep 09 10:33:33 PM UTC 24 |
Sep 09 10:33:54 PM UTC 24 |
211140890 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.2862054089 |
|
|
Sep 09 10:33:36 PM UTC 24 |
Sep 09 10:33:55 PM UTC 24 |
302428570 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.1871178410 |
|
|
Sep 09 10:33:51 PM UTC 24 |
Sep 09 10:33:56 PM UTC 24 |
66029591 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1350821701 |
|
|
Sep 09 10:32:15 PM UTC 24 |
Sep 09 10:33:56 PM UTC 24 |
12166082935 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.4083009254 |
|
|
Sep 09 10:33:45 PM UTC 24 |
Sep 09 10:33:56 PM UTC 24 |
317838808 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.2747737633 |
|
|
Sep 09 10:34:27 PM UTC 24 |
Sep 09 10:34:43 PM UTC 24 |
793794535 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.188548651 |
|
|
Sep 09 10:33:54 PM UTC 24 |
Sep 09 10:33:59 PM UTC 24 |
282717334 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.123570103 |
|
|
Sep 09 10:33:27 PM UTC 24 |
Sep 09 10:34:01 PM UTC 24 |
314314323 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.1648444505 |
|
|
Sep 09 10:33:08 PM UTC 24 |
Sep 09 10:34:01 PM UTC 24 |
5552855461 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.3409283828 |
|
|
Sep 09 10:33:46 PM UTC 24 |
Sep 09 10:34:01 PM UTC 24 |
417212644 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1779442757 |
|
|
Sep 09 10:33:47 PM UTC 24 |
Sep 09 10:34:02 PM UTC 24 |
357504458 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_errors.2085100474 |
|
|
Sep 09 10:33:45 PM UTC 24 |
Sep 09 10:34:02 PM UTC 24 |
1251395953 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.215515695 |
|
|
Sep 09 10:34:00 PM UTC 24 |
Sep 09 10:34:03 PM UTC 24 |
19923459 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.2900477622 |
|
|
Sep 09 10:33:49 PM UTC 24 |
Sep 09 10:34:03 PM UTC 24 |
238481413 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.2411587017 |
|
|
Sep 09 10:33:54 PM UTC 24 |
Sep 09 10:34:04 PM UTC 24 |
488439148 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3503899340 |
|
|
Sep 09 10:34:02 PM UTC 24 |
Sep 09 10:34:04 PM UTC 24 |
16234239 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.1759446430 |
|
|
Sep 09 10:33:55 PM UTC 24 |
Sep 09 10:34:06 PM UTC 24 |
1097381249 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.2804140305 |
|
|
Sep 09 10:33:55 PM UTC 24 |
Sep 09 10:34:06 PM UTC 24 |
1885290256 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.1713416304 |
|
|
Sep 09 10:34:02 PM UTC 24 |
Sep 09 10:34:07 PM UTC 24 |
51240120 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.781842206 |
|
|
Sep 09 10:33:49 PM UTC 24 |
Sep 09 10:34:07 PM UTC 24 |
3304970882 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.2073275011 |
|
|
Sep 09 10:33:57 PM UTC 24 |
Sep 09 10:34:08 PM UTC 24 |
1336321837 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.2024506707 |
|
|
Sep 09 10:34:27 PM UTC 24 |
Sep 09 10:34:44 PM UTC 24 |
666172440 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.4159903294 |
|
|
Sep 09 10:34:03 PM UTC 24 |
Sep 09 10:34:09 PM UTC 24 |
477917807 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.3347584750 |
|
|
Sep 09 10:33:57 PM UTC 24 |
Sep 09 10:34:12 PM UTC 24 |
786363308 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.895551001 |
|
|
Sep 09 10:34:10 PM UTC 24 |
Sep 09 10:34:12 PM UTC 24 |
30750469 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.2277595043 |
|
|
Sep 09 10:34:10 PM UTC 24 |
Sep 09 10:34:13 PM UTC 24 |
69146469 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.210668523 |
|
|
Sep 09 10:34:03 PM UTC 24 |
Sep 09 10:34:14 PM UTC 24 |
243233793 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.607249347 |
|
|
Sep 09 10:34:13 PM UTC 24 |
Sep 09 10:34:15 PM UTC 24 |
45463845 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.1490862911 |
|
|
Sep 09 10:34:05 PM UTC 24 |
Sep 09 10:34:17 PM UTC 24 |
440688795 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_errors.1747071729 |
|
|
Sep 09 10:33:55 PM UTC 24 |
Sep 09 10:34:19 PM UTC 24 |
1628996564 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.1633336814 |
|
|
Sep 09 10:31:01 PM UTC 24 |
Sep 09 10:34:19 PM UTC 24 |
16212059223 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.3223142458 |
|
|
Sep 09 10:34:07 PM UTC 24 |
Sep 09 10:34:20 PM UTC 24 |
1727554471 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.947860275 |
|
|
Sep 09 10:34:05 PM UTC 24 |
Sep 09 10:34:20 PM UTC 24 |
1270926223 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2369052771 |
|
|
Sep 09 10:32:52 PM UTC 24 |
Sep 09 10:34:20 PM UTC 24 |
4156687509 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.2334059003 |
|
|
Sep 09 10:34:07 PM UTC 24 |
Sep 09 10:34:20 PM UTC 24 |
3560353297 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.338035330 |
|
|
Sep 09 10:33:44 PM UTC 24 |
Sep 09 10:34:21 PM UTC 24 |
1788202017 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.3158956633 |
|
|
Sep 09 10:34:15 PM UTC 24 |
Sep 09 10:34:21 PM UTC 24 |
183035238 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.836596140 |
|
|
Sep 09 10:34:13 PM UTC 24 |
Sep 09 10:34:40 PM UTC 24 |
1301048053 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.2345463654 |
|
|
Sep 09 10:34:33 PM UTC 24 |
Sep 09 10:34:41 PM UTC 24 |
416369245 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.950222276 |
|
|
Sep 09 10:34:20 PM UTC 24 |
Sep 09 10:34:23 PM UTC 24 |
338395915 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.308311187 |
|
|
Sep 09 10:24:50 PM UTC 24 |
Sep 09 10:34:23 PM UTC 24 |
182303247234 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.74931135 |
|
|
Sep 09 10:33:57 PM UTC 24 |
Sep 09 10:34:24 PM UTC 24 |
870622105 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.4256928895 |
|
|
Sep 09 10:33:53 PM UTC 24 |
Sep 09 10:34:25 PM UTC 24 |
540314441 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.404237007 |
|
|
Sep 09 10:33:49 PM UTC 24 |
Sep 09 10:34:25 PM UTC 24 |
599051818 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.920856180 |
|
|
Sep 09 10:34:23 PM UTC 24 |
Sep 09 10:34:25 PM UTC 24 |
59341947 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.1382159862 |
|
|
Sep 09 10:34:23 PM UTC 24 |
Sep 09 10:34:26 PM UTC 24 |
20583787 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.2377464725 |
|
|
Sep 09 10:34:14 PM UTC 24 |
Sep 09 10:34:26 PM UTC 24 |
183591481 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.3416778151 |
|
|
Sep 09 10:34:02 PM UTC 24 |
Sep 09 10:34:26 PM UTC 24 |
130030156 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.1377837886 |
|
|
Sep 09 10:34:06 PM UTC 24 |
Sep 09 10:34:27 PM UTC 24 |
384229873 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3019743260 |
|
|
Sep 09 10:34:25 PM UTC 24 |
Sep 09 10:34:27 PM UTC 24 |
118389849 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.1406366747 |
|
|
Sep 09 10:34:16 PM UTC 24 |
Sep 09 10:34:30 PM UTC 24 |
1019733256 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.3987030031 |
|
|
Sep 09 10:34:27 PM UTC 24 |
Sep 09 10:34:30 PM UTC 24 |
21561088 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.260378210 |
|
|
Sep 09 10:34:21 PM UTC 24 |
Sep 09 10:34:32 PM UTC 24 |
1053678490 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.2249997216 |
|
|
Sep 09 10:34:31 PM UTC 24 |
Sep 09 10:34:34 PM UTC 24 |
12506092 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_errors.4202221955 |
|
|
Sep 09 10:34:03 PM UTC 24 |
Sep 09 10:34:34 PM UTC 24 |
710656237 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.1107605282 |
|
|
Sep 09 10:34:27 PM UTC 24 |
Sep 09 10:34:35 PM UTC 24 |
193332282 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.227757673 |
|
|
Sep 09 10:34:21 PM UTC 24 |
Sep 09 10:34:35 PM UTC 24 |
382335902 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.2397864464 |
|
|
Sep 09 10:34:25 PM UTC 24 |
Sep 09 10:34:36 PM UTC 24 |
250838330 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.7333265 |
|
|
Sep 09 10:34:18 PM UTC 24 |
Sep 09 10:34:37 PM UTC 24 |
4244965984 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.2006256327 |
|
|
Sep 09 10:34:29 PM UTC 24 |
Sep 09 10:34:41 PM UTC 24 |
376740165 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1032722791 |
|
|
Sep 09 10:34:35 PM UTC 24 |
Sep 09 10:34:38 PM UTC 24 |
13471386 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.774809380 |
|
|
Sep 09 10:34:27 PM UTC 24 |
Sep 09 10:34:39 PM UTC 24 |
428240830 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.1434138497 |
|
|
Sep 09 10:34:21 PM UTC 24 |
Sep 09 10:34:40 PM UTC 24 |
1026984927 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.2862150295 |
|
|
Sep 09 10:33:57 PM UTC 24 |
Sep 09 10:34:41 PM UTC 24 |
4060389677 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.4189406056 |
|
|
Sep 09 10:34:37 PM UTC 24 |
Sep 09 10:34:42 PM UTC 24 |
72316995 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.846576765 |
|
|
Sep 09 10:34:42 PM UTC 24 |
Sep 09 10:34:44 PM UTC 24 |
17793531 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2216276930 |
|
|
Sep 09 10:34:43 PM UTC 24 |
Sep 09 10:34:45 PM UTC 24 |
31929641 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.3738201639 |
|
|
Sep 09 10:34:42 PM UTC 24 |
Sep 09 10:34:46 PM UTC 24 |
149866158 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_errors.2643751526 |
|
|
Sep 09 10:34:27 PM UTC 24 |
Sep 09 10:34:47 PM UTC 24 |
1488793328 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.4224989295 |
|
|
Sep 09 10:34:37 PM UTC 24 |
Sep 09 10:34:47 PM UTC 24 |
318582155 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.3256476566 |
|
|
Sep 09 10:32:23 PM UTC 24 |
Sep 09 10:34:47 PM UTC 24 |
17177546689 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.2045938689 |
|
|
Sep 09 10:34:39 PM UTC 24 |
Sep 09 10:34:48 PM UTC 24 |
383033164 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.2737550051 |
|
|
Sep 09 10:32:42 PM UTC 24 |
Sep 09 10:34:48 PM UTC 24 |
28658866157 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.2593048345 |
|
|
Sep 09 10:34:39 PM UTC 24 |
Sep 09 10:34:49 PM UTC 24 |
1137463053 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.1761494324 |
|
|
Sep 09 10:34:08 PM UTC 24 |
Sep 09 10:34:49 PM UTC 24 |
891623615 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.380861198 |
|
|
Sep 09 10:34:45 PM UTC 24 |
Sep 09 10:34:50 PM UTC 24 |
301955511 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_errors.2692031181 |
|
|
Sep 09 10:34:37 PM UTC 24 |
Sep 09 10:34:50 PM UTC 24 |
1253210847 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.1108169621 |
|
|
Sep 09 10:32:05 PM UTC 24 |
Sep 09 10:34:51 PM UTC 24 |
82112062594 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.2102983018 |
|
|
Sep 09 10:33:39 PM UTC 24 |
Sep 09 10:34:52 PM UTC 24 |
1456940652 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2570027180 |
|
|
Sep 09 10:34:42 PM UTC 24 |
Sep 09 10:34:53 PM UTC 24 |
309429966 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.3615391797 |
|
|
Sep 09 10:34:51 PM UTC 24 |
Sep 09 10:34:53 PM UTC 24 |
73048915 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1048023569 |
|
|
Sep 09 10:34:51 PM UTC 24 |
Sep 09 10:34:53 PM UTC 24 |
110272972 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.2493899799 |
|
|
Sep 09 10:32:51 PM UTC 24 |
Sep 09 10:34:54 PM UTC 24 |
15714443277 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.2845590462 |
|
|
Sep 09 10:34:39 PM UTC 24 |
Sep 09 10:34:55 PM UTC 24 |
760336134 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.3859453387 |
|
|
Sep 09 10:34:45 PM UTC 24 |
Sep 09 10:34:55 PM UTC 24 |
83478840 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.3688606294 |
|
|
Sep 09 10:34:40 PM UTC 24 |
Sep 09 10:34:55 PM UTC 24 |
1558785149 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2915006718 |
|
|
Sep 09 10:34:08 PM UTC 24 |
Sep 09 10:34:56 PM UTC 24 |
1941156780 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.4088066061 |
|
|
Sep 09 10:34:52 PM UTC 24 |
Sep 09 10:34:57 PM UTC 24 |
51375001 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.1445074505 |
|
|
Sep 09 10:34:48 PM UTC 24 |
Sep 09 10:34:57 PM UTC 24 |
531270872 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.574012786 |
|
|
Sep 09 10:34:48 PM UTC 24 |
Sep 09 10:34:57 PM UTC 24 |
216270638 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.3657734240 |
|
|
Sep 09 10:34:51 PM UTC 24 |
Sep 09 10:34:59 PM UTC 24 |
284146145 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.3064113128 |
|
|
Sep 09 10:34:52 PM UTC 24 |
Sep 09 10:34:59 PM UTC 24 |
1247227714 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.666478023 |
|
|
Sep 09 10:34:46 PM UTC 24 |
Sep 09 10:34:59 PM UTC 24 |
1073298172 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.4243081581 |
|
|
Sep 09 10:34:58 PM UTC 24 |
Sep 09 10:35:01 PM UTC 24 |
43631717 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.2909760470 |
|
|
Sep 09 10:34:58 PM UTC 24 |
Sep 09 10:35:01 PM UTC 24 |
18386146 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.229911391 |
|
|
Sep 09 10:34:58 PM UTC 24 |
Sep 09 10:35:01 PM UTC 24 |
218405906 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.3448458109 |
|
|
Sep 09 10:34:25 PM UTC 24 |
Sep 09 10:35:03 PM UTC 24 |
326724059 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.1252459138 |
|
|
Sep 09 10:34:48 PM UTC 24 |
Sep 09 10:35:04 PM UTC 24 |
1356876179 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.3448487150 |
|
|
Sep 09 10:34:54 PM UTC 24 |
Sep 09 10:35:05 PM UTC 24 |
400183870 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_errors.4163255873 |
|
|
Sep 09 10:34:46 PM UTC 24 |
Sep 09 10:35:06 PM UTC 24 |
2500187837 ps |