| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.24 | 97.99 | 95.68 | 93.40 | 100.00 | 98.55 | 98.76 | 96.29 |
| T1001 | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2578312930 | Sep 09 09:10:13 PM UTC 24 | Sep 09 09:10:43 PM UTC 24 | 129660957 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.2947810722 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 139357120 ps |
| CPU time | 4.27 seconds |
| Started | Sep 09 10:23:54 PM UTC 24 |
| Finished | Sep 09 10:23:59 PM UTC 24 |
| Peak memory | 236324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947810722 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2947810722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.2981065285 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 644807198 ps |
| CPU time | 9.45 seconds |
| Started | Sep 09 10:23:58 PM UTC 24 |
| Finished | Sep 09 10:24:09 PM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981065285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_s moke.2981065285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2370679849 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 345498100 ps |
| CPU time | 17.58 seconds |
| Started | Sep 09 10:23:57 PM UTC 24 |
| Finished | Sep 09 10:24:16 PM UTC 24 |
| Peak memory | 237596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370679849 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2370679849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.2706905332 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2488371690 ps |
| CPU time | 18.08 seconds |
| Started | Sep 09 10:23:58 PM UTC 24 |
| Finished | Sep 09 10:24:17 PM UTC 24 |
| Peak memory | 237660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706905332 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2706905332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.700848716 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 487504354 ps |
| CPU time | 22.04 seconds |
| Started | Sep 09 10:25:36 PM UTC 24 |
| Finished | Sep 09 10:25:59 PM UTC 24 |
| Peak memory | 237912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700848716 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.700848716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.2750215558 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 150099274 ps |
| CPU time | 7.04 seconds |
| Started | Sep 09 10:23:59 PM UTC 24 |
| Finished | Sep 09 10:24:07 PM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750215558 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2750215558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.1938896172 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4946909400 ps |
| CPU time | 118.53 seconds |
| Started | Sep 09 10:24:00 PM UTC 24 |
| Finished | Sep 09 10:26:01 PM UTC 24 |
| Peak memory | 293608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1938896172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.lc_ctrl_stress_all.1938896172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3915188627 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 347037137 ps |
| CPU time | 3.11 seconds |
| Started | Sep 09 09:09:39 PM UTC 24 |
| Finished | Sep 09 09:09:44 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915188627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3915188627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.1871766979 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 228877724 ps |
| CPU time | 39.7 seconds |
| Started | Sep 09 10:24:31 PM UTC 24 |
| Finished | Sep 09 10:25:12 PM UTC 24 |
| Peak memory | 289892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871766979 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1871766979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.1940718131 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 297424598 ps |
| CPU time | 15.02 seconds |
| Started | Sep 09 10:28:25 PM UTC 24 |
| Finished | Sep 09 10:28:41 PM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940718131 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1940718131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2207183627 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 18845316 ps |
| CPU time | 1.07 seconds |
| Started | Sep 09 10:24:32 PM UTC 24 |
| Finished | Sep 09 10:24:34 PM UTC 24 |
| Peak memory | 218292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207183627 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2. lc_ctrl_volatile_unlock_smoke.2207183627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2330596574 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 4212200838 ps |
| CPU time | 167.31 seconds |
| Started | Sep 09 10:24:51 PM UTC 24 |
| Finished | Sep 09 10:27:41 PM UTC 24 |
| Peak memory | 432700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330596574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.2330596574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3085700182 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 120018235 ps |
| CPU time | 2.86 seconds |
| Started | Sep 09 09:09:41 PM UTC 24 |
| Finished | Sep 09 09:09:45 PM UTC 24 |
| Peak memory | 229776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085700182 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_ intg_err.3085700182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.3915651209 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 512004585 ps |
| CPU time | 35.01 seconds |
| Started | Sep 09 10:24:08 PM UTC 24 |
| Finished | Sep 09 10:24:45 PM UTC 24 |
| Peak memory | 262924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915651209 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3915651209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.2705897112 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 10397272855 ps |
| CPU time | 309.8 seconds |
| Started | Sep 09 10:30:16 PM UTC 24 |
| Finished | Sep 09 10:35:30 PM UTC 24 |
| Peak memory | 262648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2705897112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 18.lc_ctrl_stress_all.2705897112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_errors.2366570184 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1775067766 ps |
| CPU time | 14.69 seconds |
| Started | Sep 09 10:32:09 PM UTC 24 |
| Finished | Sep 09 10:32:25 PM UTC 24 |
| Peak memory | 237668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366570184 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2366570184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.338630202 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 306470305 ps |
| CPU time | 17.05 seconds |
| Started | Sep 09 10:23:59 PM UTC 24 |
| Finished | Sep 09 10:24:17 PM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338630202 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.338630202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4228510263 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 36541435 ps |
| CPU time | 1.43 seconds |
| Started | Sep 09 09:09:41 PM UTC 24 |
| Finished | Sep 09 09:09:43 PM UTC 24 |
| Peak memory | 230512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228510263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw _reset.4228510263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.1898876352 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 13378352 ps |
| CPU time | 1.29 seconds |
| Started | Sep 09 10:24:02 PM UTC 24 |
| Finished | Sep 09 10:24:04 PM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898876352 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1898876352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3301015600 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 111125370 ps |
| CPU time | 3.6 seconds |
| Started | Sep 09 09:10:14 PM UTC 24 |
| Finished | Sep 09 09:10:22 PM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301015600 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl _intg_err.3301015600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.309411561 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2072084090 ps |
| CPU time | 45.22 seconds |
| Started | Sep 09 10:25:17 PM UTC 24 |
| Finished | Sep 09 10:26:04 PM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309411561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.309411561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.959466660 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 104980396 ps |
| CPU time | 2.19 seconds |
| Started | Sep 09 09:09:40 PM UTC 24 |
| Finished | Sep 09 09:09:43 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959466660 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.959466660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.2527993176 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2194121864 ps |
| CPU time | 42.1 seconds |
| Started | Sep 09 10:28:21 PM UTC 24 |
| Finished | Sep 09 10:29:05 PM UTC 24 |
| Peak memory | 262564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527993176 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2527993176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3450214981 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2974258750 ps |
| CPU time | 88.1 seconds |
| Started | Sep 09 10:24:28 PM UTC 24 |
| Finished | Sep 09 10:25:59 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450214981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.3450214981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.2089104611 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 290694661 ps |
| CPU time | 2.77 seconds |
| Started | Sep 09 10:23:58 PM UTC 24 |
| Finished | Sep 09 10:24:02 PM UTC 24 |
| Peak memory | 231804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089104611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl _jtag_prog_failure.2089104611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.3647967644 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 502700875 ps |
| CPU time | 14.61 seconds |
| Started | Sep 09 10:27:48 PM UTC 24 |
| Finished | Sep 09 10:28:03 PM UTC 24 |
| Peak memory | 231936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647967644 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3647967644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.2498846195 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 195761047 ps |
| CPU time | 16.63 seconds |
| Started | Sep 09 10:24:17 PM UTC 24 |
| Finished | Sep 09 10:24:35 PM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498846195 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2498846195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2780495126 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 120691786 ps |
| CPU time | 1.84 seconds |
| Started | Sep 09 09:09:45 PM UTC 24 |
| Finished | Sep 09 09:09:48 PM UTC 24 |
| Peak memory | 227796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780495126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2780495126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1325203014 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 176505825 ps |
| CPU time | 25.43 seconds |
| Started | Sep 09 10:23:54 PM UTC 24 |
| Finished | Sep 09 10:24:21 PM UTC 24 |
| Peak memory | 262512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325203014 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1325203014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2937970805 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 119169902 ps |
| CPU time | 3.08 seconds |
| Started | Sep 09 09:10:10 PM UTC 24 |
| Finished | Sep 09 09:10:14 PM UTC 24 |
| Peak memory | 235792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937970805 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl _intg_err.2937970805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2474326422 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 469781357 ps |
| CPU time | 3.8 seconds |
| Started | Sep 09 09:10:14 PM UTC 24 |
| Finished | Sep 09 09:10:22 PM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474326422 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl _intg_err.2474326422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1488521988 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 268259485 ps |
| CPU time | 1.79 seconds |
| Started | Sep 09 09:09:57 PM UTC 24 |
| Finished | Sep 09 09:10:11 PM UTC 24 |
| Peak memory | 232620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488521988 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_ intg_err.1488521988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.736654048 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 314413914 ps |
| CPU time | 2.64 seconds |
| Started | Sep 09 09:09:38 PM UTC 24 |
| Finished | Sep 09 09:09:42 PM UTC 24 |
| Peak memory | 221508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=736654048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.736654048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4070379100 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 78526486 ps |
| CPU time | 3.59 seconds |
| Started | Sep 09 09:10:16 PM UTC 24 |
| Finished | Sep 09 09:10:38 PM UTC 24 |
| Peak memory | 229068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070379100 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl _intg_err.4070379100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3368612752 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 44332991 ps |
| CPU time | 1.91 seconds |
| Started | Sep 09 09:10:17 PM UTC 24 |
| Finished | Sep 09 09:10:31 PM UTC 24 |
| Peak memory | 222324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368612752 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl _intg_err.3368612752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4177262464 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 107943345 ps |
| CPU time | 2.87 seconds |
| Started | Sep 09 09:09:48 PM UTC 24 |
| Finished | Sep 09 09:09:52 PM UTC 24 |
| Peak memory | 230180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177262464 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_ intg_err.4177262464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.1483800192 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 35965114 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 10:23:58 PM UTC 24 |
| Finished | Sep 09 10:24:00 PM UTC 24 |
| Peak memory | 218316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483800192 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1483800192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.1979304631 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 46702429 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 10:25:05 PM UTC 24 |
| Finished | Sep 09 10:25:08 PM UTC 24 |
| Peak memory | 218320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979304631 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1979304631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2747781111 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 85278369 ps |
| CPU time | 1.25 seconds |
| Started | Sep 09 10:26:57 PM UTC 24 |
| Finished | Sep 09 10:26:59 PM UTC 24 |
| Peak memory | 217020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747781111 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2747781111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.1173865139 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 47716866 ps |
| CPU time | 1.22 seconds |
| Started | Sep 09 10:27:13 PM UTC 24 |
| Finished | Sep 09 10:27:15 PM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173865139 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1173865139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.2953656366 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 4253910424 ps |
| CPU time | 56.28 seconds |
| Started | Sep 09 10:24:19 PM UTC 24 |
| Finished | Sep 09 10:25:17 PM UTC 24 |
| Peak memory | 262496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953656366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr l_jtag_state_failure.2953656366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1979986902 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 119121607 ps |
| CPU time | 2.48 seconds |
| Started | Sep 09 09:09:44 PM UTC 24 |
| Finished | Sep 09 09:09:47 PM UTC 24 |
| Peak memory | 235848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979986902 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_ intg_err.1979986902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.454130865 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 27262407 ps |
| CPU time | 2.31 seconds |
| Started | Sep 09 09:10:10 PM UTC 24 |
| Finished | Sep 09 09:10:14 PM UTC 24 |
| Peak memory | 231728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454130865 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.454130865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3558061354 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 110378696 ps |
| CPU time | 2.52 seconds |
| Started | Sep 09 09:10:11 PM UTC 24 |
| Finished | Sep 09 09:10:16 PM UTC 24 |
| Peak memory | 235852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558061354 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl _intg_err.3558061354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.379021329 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 45258997 ps |
| CPU time | 2.22 seconds |
| Started | Sep 09 09:10:13 PM UTC 24 |
| Finished | Sep 09 09:10:36 PM UTC 24 |
| Peak memory | 234144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379021329 -asse rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_ intg_err.379021329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3361259284 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 64861206 ps |
| CPU time | 2.54 seconds |
| Started | Sep 09 09:09:46 PM UTC 24 |
| Finished | Sep 09 09:09:50 PM UTC 24 |
| Peak memory | 234064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361259284 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_ intg_err.3361259284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3550225736 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 55169129 ps |
| CPU time | 1.99 seconds |
| Started | Sep 09 09:09:54 PM UTC 24 |
| Finished | Sep 09 09:10:00 PM UTC 24 |
| Peak memory | 234672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550225736 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_ intg_err.3550225736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_errors.1789935180 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 373918866 ps |
| CPU time | 12 seconds |
| Started | Sep 09 10:32:00 PM UTC 24 |
| Finished | Sep 09 10:32:13 PM UTC 24 |
| Peak memory | 230244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789935180 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1789935180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1390037643 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 16797810 ps |
| CPU time | 1.51 seconds |
| Started | Sep 09 09:09:41 PM UTC 24 |
| Finished | Sep 09 09:09:43 PM UTC 24 |
| Peak memory | 218704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390037643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_al iasing.1390037643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3258174275 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 79723492 ps |
| CPU time | 1.56 seconds |
| Started | Sep 09 09:09:41 PM UTC 24 |
| Finished | Sep 09 09:09:43 PM UTC 24 |
| Peak memory | 219048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258174275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bi t_bash.3258174275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1512854177 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 97630705 ps |
| CPU time | 1.97 seconds |
| Started | Sep 09 09:09:42 PM UTC 24 |
| Finished | Sep 09 09:09:45 PM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1512854177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1512854177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3327387916 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 17962306 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 09:09:41 PM UTC 24 |
| Finished | Sep 09 09:09:43 PM UTC 24 |
| Peak memory | 218732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327387916 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3327387916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4187308837 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 117259508 ps |
| CPU time | 3.45 seconds |
| Started | Sep 09 09:09:40 PM UTC 24 |
| Finished | Sep 09 09:09:44 PM UTC 24 |
| Peak memory | 219088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4187308837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.lc_ctrl_jtag_alert_test.4187308837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2274949496 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1702127337 ps |
| CPU time | 5.2 seconds |
| Started | Sep 09 09:09:38 PM UTC 24 |
| Finished | Sep 09 09:09:45 PM UTC 24 |
| Peak memory | 219220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2274949496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2274949496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.482659174 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 1227296289 ps |
| CPU time | 23.06 seconds |
| Started | Sep 09 09:09:38 PM UTC 24 |
| Finished | Sep 09 09:10:03 PM UTC 24 |
| Peak memory | 219292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=482659174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.482659174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2011817950 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 248320361 ps |
| CPU time | 6.47 seconds |
| Started | Sep 09 09:09:37 PM UTC 24 |
| Finished | Sep 09 09:09:45 PM UTC 24 |
| Peak memory | 221832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2011817950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2011817950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4107327132 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 225501146 ps |
| CPU time | 2.22 seconds |
| Started | Sep 09 09:09:38 PM UTC 24 |
| Finished | Sep 09 09:09:42 PM UTC 24 |
| Peak memory | 219532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4107327132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 0.lc_ctrl_jtag_csr_rw.4107327132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2758472750 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 47830596 ps |
| CPU time | 1.56 seconds |
| Started | Sep 09 09:09:42 PM UTC 24 |
| Finished | Sep 09 09:09:45 PM UTC 24 |
| Peak memory | 218716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275847 2750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc _ctrl_same_csr_outstanding.2758472750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2641978191 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 14881654 ps |
| CPU time | 1.76 seconds |
| Started | Sep 09 09:09:44 PM UTC 24 |
| Finished | Sep 09 09:09:46 PM UTC 24 |
| Peak memory | 217216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641978191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_al iasing.2641978191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.372205219 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 54464373 ps |
| CPU time | 1.93 seconds |
| Started | Sep 09 09:09:44 PM UTC 24 |
| Finished | Sep 09 09:09:47 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372205219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit _bash.372205219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3760954316 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 48735572 ps |
| CPU time | 1.12 seconds |
| Started | Sep 09 09:09:44 PM UTC 24 |
| Finished | Sep 09 09:09:46 PM UTC 24 |
| Peak memory | 220272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760954316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw _reset.3760954316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3443869417 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 30474758 ps |
| CPU time | 1.68 seconds |
| Started | Sep 09 09:09:44 PM UTC 24 |
| Finished | Sep 09 09:09:46 PM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3443869417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3443869417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3950820139 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 21127567 ps |
| CPU time | 1.31 seconds |
| Started | Sep 09 09:09:44 PM UTC 24 |
| Finished | Sep 09 09:09:46 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950820139 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3950820139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1654440428 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 175866912 ps |
| CPU time | 1.73 seconds |
| Started | Sep 09 09:09:42 PM UTC 24 |
| Finished | Sep 09 09:09:45 PM UTC 24 |
| Peak memory | 218680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1654440428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1654440428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2973985810 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 445281823 ps |
| CPU time | 11.98 seconds |
| Started | Sep 09 09:09:42 PM UTC 24 |
| Finished | Sep 09 09:09:55 PM UTC 24 |
| Peak memory | 218696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2973985810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2973985810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4180073060 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 1598422433 ps |
| CPU time | 17.24 seconds |
| Started | Sep 09 09:09:42 PM UTC 24 |
| Finished | Sep 09 09:10:01 PM UTC 24 |
| Peak memory | 219580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4180073060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.4180073060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1299720577 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 175021293 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 09:09:42 PM UTC 24 |
| Finished | Sep 09 09:09:44 PM UTC 24 |
| Peak memory | 220572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1299720577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1299720577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4052557917 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 337210262 ps |
| CPU time | 2.86 seconds |
| Started | Sep 09 09:09:42 PM UTC 24 |
| Finished | Sep 09 09:09:46 PM UTC 24 |
| Peak memory | 231812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052557917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4052557917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.745285487 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 329342140 ps |
| CPU time | 3.17 seconds |
| Started | Sep 09 09:09:42 PM UTC 24 |
| Finished | Sep 09 09:09:46 PM UTC 24 |
| Peak memory | 219656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=745285487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.lc_ctrl_jtag_csr_rw.745285487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1593482317 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 22716703 ps |
| CPU time | 1.42 seconds |
| Started | Sep 09 09:09:42 PM UTC 24 |
| Finished | Sep 09 09:09:45 PM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1593482317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1593482317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2934702944 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 38165210 ps |
| CPU time | 1.47 seconds |
| Started | Sep 09 09:09:44 PM UTC 24 |
| Finished | Sep 09 09:09:46 PM UTC 24 |
| Peak memory | 228884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293470 2944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc _ctrl_same_csr_outstanding.2934702944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2496934029 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 129067291 ps |
| CPU time | 3.49 seconds |
| Started | Sep 09 09:09:43 PM UTC 24 |
| Finished | Sep 09 09:09:48 PM UTC 24 |
| Peak memory | 232100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496934029 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2496934029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.196116961 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 85220941 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 09:10:11 PM UTC 24 |
| Finished | Sep 09 09:10:15 PM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=196116961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.196116961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1294089836 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 15660252 ps |
| CPU time | 0.97 seconds |
| Started | Sep 09 09:10:11 PM UTC 24 |
| Finished | Sep 09 09:10:15 PM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294089836 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1294089836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.785070993 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 78054997 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 09:10:11 PM UTC 24 |
| Finished | Sep 09 09:10:15 PM UTC 24 |
| Peak memory | 218292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785070 993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc _ctrl_same_csr_outstanding.785070993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1600039256 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 85701746 ps |
| CPU time | 1.59 seconds |
| Started | Sep 09 09:10:12 PM UTC 24 |
| Finished | Sep 09 09:10:15 PM UTC 24 |
| Peak memory | 236948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1600039256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1600039256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2668591459 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 13794821 ps |
| CPU time | 0.95 seconds |
| Started | Sep 09 09:10:11 PM UTC 24 |
| Finished | Sep 09 09:10:15 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668591459 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2668591459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3854346760 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 106354826 ps |
| CPU time | 1.64 seconds |
| Started | Sep 09 09:10:11 PM UTC 24 |
| Finished | Sep 09 09:10:25 PM UTC 24 |
| Peak memory | 228948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385434 6760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.l c_ctrl_same_csr_outstanding.3854346760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1196105469 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 185254751 ps |
| CPU time | 3.9 seconds |
| Started | Sep 09 09:10:11 PM UTC 24 |
| Finished | Sep 09 09:10:17 PM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196105469 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1196105469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.128855910 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 18027862 ps |
| CPU time | 1.52 seconds |
| Started | Sep 09 09:10:13 PM UTC 24 |
| Finished | Sep 09 09:10:36 PM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=128855910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.128855910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3286351813 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 42823825 ps |
| CPU time | 0.88 seconds |
| Started | Sep 09 09:10:12 PM UTC 24 |
| Finished | Sep 09 09:10:35 PM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286351813 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3286351813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2488745582 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 290367032 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 09:10:12 PM UTC 24 |
| Finished | Sep 09 09:10:35 PM UTC 24 |
| Peak memory | 218292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248874 5582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.l c_ctrl_same_csr_outstanding.2488745582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1116143637 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 81981228 ps |
| CPU time | 2.48 seconds |
| Started | Sep 09 09:10:12 PM UTC 24 |
| Finished | Sep 09 09:10:16 PM UTC 24 |
| Peak memory | 229688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116143637 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1116143637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3485798729 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 199218508 ps |
| CPU time | 1.87 seconds |
| Started | Sep 09 09:10:12 PM UTC 24 |
| Finished | Sep 09 09:10:26 PM UTC 24 |
| Peak memory | 232624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485798729 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl _intg_err.3485798729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3385579025 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 64325144 ps |
| CPU time | 1.7 seconds |
| Started | Sep 09 09:10:13 PM UTC 24 |
| Finished | Sep 09 09:10:43 PM UTC 24 |
| Peak memory | 230516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3385579025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3385579025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1243614745 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 28271051 ps |
| CPU time | 1.14 seconds |
| Started | Sep 09 09:10:13 PM UTC 24 |
| Finished | Sep 09 09:10:35 PM UTC 24 |
| Peak memory | 218848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243614745 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1243614745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2067423023 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 15757604 ps |
| CPU time | 1.13 seconds |
| Started | Sep 09 09:10:13 PM UTC 24 |
| Finished | Sep 09 09:10:35 PM UTC 24 |
| Peak memory | 218292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206742 3023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.l c_ctrl_same_csr_outstanding.2067423023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.395093096 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 35977201 ps |
| CPU time | 2.1 seconds |
| Started | Sep 09 09:10:13 PM UTC 24 |
| Finished | Sep 09 09:10:36 PM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395093096 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.395093096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.269351954 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 19335803 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 09:10:14 PM UTC 24 |
| Finished | Sep 09 09:10:20 PM UTC 24 |
| Peak memory | 228460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=269351954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.269351954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.402679683 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 14061951 ps |
| CPU time | 1.21 seconds |
| Started | Sep 09 09:10:13 PM UTC 24 |
| Finished | Sep 09 09:10:43 PM UTC 24 |
| Peak memory | 218076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402679683 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.402679683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2578312930 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 129660957 ps |
| CPU time | 1.85 seconds |
| Started | Sep 09 09:10:13 PM UTC 24 |
| Finished | Sep 09 09:10:43 PM UTC 24 |
| Peak memory | 218756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257831 2930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.l c_ctrl_same_csr_outstanding.2578312930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3512953326 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 147752855 ps |
| CPU time | 3.06 seconds |
| Started | Sep 09 09:10:13 PM UTC 24 |
| Finished | Sep 09 09:10:37 PM UTC 24 |
| Peak memory | 229784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512953326 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3512953326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1135783366 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 84784826 ps |
| CPU time | 2.2 seconds |
| Started | Sep 09 09:10:13 PM UTC 24 |
| Finished | Sep 09 09:10:37 PM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135783366 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl _intg_err.1135783366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2333630559 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 110446049 ps |
| CPU time | 1.49 seconds |
| Started | Sep 09 09:10:14 PM UTC 24 |
| Finished | Sep 09 09:10:20 PM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2333630559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2333630559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3559342911 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 35228095 ps |
| CPU time | 0.93 seconds |
| Started | Sep 09 09:10:14 PM UTC 24 |
| Finished | Sep 09 09:10:19 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559342911 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3559342911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3142305807 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 25391524 ps |
| CPU time | 1.31 seconds |
| Started | Sep 09 09:10:14 PM UTC 24 |
| Finished | Sep 09 09:10:20 PM UTC 24 |
| Peak memory | 220708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314230 5807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.l c_ctrl_same_csr_outstanding.3142305807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.745325457 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 170918210 ps |
| CPU time | 2.39 seconds |
| Started | Sep 09 09:10:14 PM UTC 24 |
| Finished | Sep 09 09:10:21 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745325457 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.745325457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3414983390 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 92322880 ps |
| CPU time | 1.81 seconds |
| Started | Sep 09 09:10:16 PM UTC 24 |
| Finished | Sep 09 09:10:26 PM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3414983390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3414983390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1090451826 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 51008181 ps |
| CPU time | 0.96 seconds |
| Started | Sep 09 09:10:14 PM UTC 24 |
| Finished | Sep 09 09:10:20 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090451826 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1090451826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2340003265 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 43472113 ps |
| CPU time | 1.12 seconds |
| Started | Sep 09 09:10:16 PM UTC 24 |
| Finished | Sep 09 09:10:25 PM UTC 24 |
| Peak memory | 218568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234000 3265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.l c_ctrl_same_csr_outstanding.2340003265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1971965323 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 56891731 ps |
| CPU time | 1.85 seconds |
| Started | Sep 09 09:10:14 PM UTC 24 |
| Finished | Sep 09 09:10:21 PM UTC 24 |
| Peak memory | 228532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971965323 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1971965323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1942702783 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 58151640 ps |
| CPU time | 1.41 seconds |
| Started | Sep 09 09:10:16 PM UTC 24 |
| Finished | Sep 09 09:10:36 PM UTC 24 |
| Peak memory | 234556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1942702783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1942702783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2072703577 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 14239259 ps |
| CPU time | 0.81 seconds |
| Started | Sep 09 09:10:16 PM UTC 24 |
| Finished | Sep 09 09:10:35 PM UTC 24 |
| Peak memory | 218932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072703577 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2072703577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.480461990 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 20861733 ps |
| CPU time | 2.1 seconds |
| Started | Sep 09 09:10:16 PM UTC 24 |
| Finished | Sep 09 09:10:36 PM UTC 24 |
| Peak memory | 219808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480461 990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc _ctrl_same_csr_outstanding.480461990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3597605963 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 22598963 ps |
| CPU time | 1.55 seconds |
| Started | Sep 09 09:10:16 PM UTC 24 |
| Finished | Sep 09 09:10:26 PM UTC 24 |
| Peak memory | 228432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597605963 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3597605963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.840726105 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 123938775 ps |
| CPU time | 2.37 seconds |
| Started | Sep 09 09:10:16 PM UTC 24 |
| Finished | Sep 09 09:10:26 PM UTC 24 |
| Peak memory | 229804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840726105 -asse rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_ intg_err.840726105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2640589885 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 148469572 ps |
| CPU time | 1.17 seconds |
| Started | Sep 09 09:10:17 PM UTC 24 |
| Finished | Sep 09 09:10:20 PM UTC 24 |
| Peak memory | 232568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2640589885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2640589885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.873971409 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 13136985 ps |
| CPU time | 0.93 seconds |
| Started | Sep 09 09:10:17 PM UTC 24 |
| Finished | Sep 09 09:10:20 PM UTC 24 |
| Peak memory | 217648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873971409 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.873971409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2413934117 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 152463998 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 09:10:17 PM UTC 24 |
| Finished | Sep 09 09:10:20 PM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241393 4117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.l c_ctrl_same_csr_outstanding.2413934117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3945278540 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 107017062 ps |
| CPU time | 1.56 seconds |
| Started | Sep 09 09:10:16 PM UTC 24 |
| Finished | Sep 09 09:10:36 PM UTC 24 |
| Peak memory | 229212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945278540 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3945278540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1386678245 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 45682564 ps |
| CPU time | 1.36 seconds |
| Started | Sep 09 09:10:19 PM UTC 24 |
| Finished | Sep 09 09:10:25 PM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1386678245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1386678245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.981594375 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 24133234 ps |
| CPU time | 0.75 seconds |
| Started | Sep 09 09:10:18 PM UTC 24 |
| Finished | Sep 09 09:10:30 PM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981594375 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.981594375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.577664208 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 189591813 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 09:10:18 PM UTC 24 |
| Finished | Sep 09 09:10:30 PM UTC 24 |
| Peak memory | 220540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577664 208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc _ctrl_same_csr_outstanding.577664208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2016795244 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 100124250 ps |
| CPU time | 3.68 seconds |
| Started | Sep 09 09:10:17 PM UTC 24 |
| Finished | Sep 09 09:10:23 PM UTC 24 |
| Peak memory | 229776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016795244 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2016795244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1838525966 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 53049695 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 09:09:47 PM UTC 24 |
| Finished | Sep 09 09:09:49 PM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838525966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_al iasing.1838525966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3695426054 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 142506033 ps |
| CPU time | 1.38 seconds |
| Started | Sep 09 09:09:46 PM UTC 24 |
| Finished | Sep 09 09:09:49 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695426054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bi t_bash.3695426054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.4048812554 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 14240873 ps |
| CPU time | 1.21 seconds |
| Started | Sep 09 09:09:46 PM UTC 24 |
| Finished | Sep 09 09:09:49 PM UTC 24 |
| Peak memory | 220196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048812554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw _reset.4048812554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2328535120 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 78278052 ps |
| CPU time | 1.52 seconds |
| Started | Sep 09 09:09:47 PM UTC 24 |
| Finished | Sep 09 09:09:49 PM UTC 24 |
| Peak memory | 228532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2328535120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2328535120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1754036440 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 32862366 ps |
| CPU time | 1.05 seconds |
| Started | Sep 09 09:09:46 PM UTC 24 |
| Finished | Sep 09 09:09:49 PM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754036440 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1754036440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1182592113 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 264140260 ps |
| CPU time | 1.44 seconds |
| Started | Sep 09 09:09:45 PM UTC 24 |
| Finished | Sep 09 09:09:48 PM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1182592113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1182592113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4248046514 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 741337497 ps |
| CPU time | 6.43 seconds |
| Started | Sep 09 09:09:45 PM UTC 24 |
| Finished | Sep 09 09:09:53 PM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4248046514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.4248046514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2077703127 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 1401871638 ps |
| CPU time | 9.19 seconds |
| Started | Sep 09 09:09:45 PM UTC 24 |
| Finished | Sep 09 09:09:55 PM UTC 24 |
| Peak memory | 219080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2077703127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2077703127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3374581848 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 184643180 ps |
| CPU time | 1.68 seconds |
| Started | Sep 09 09:09:45 PM UTC 24 |
| Finished | Sep 09 09:09:48 PM UTC 24 |
| Peak memory | 220572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3374581848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3374581848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.407307936 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 908874904 ps |
| CPU time | 4.17 seconds |
| Started | Sep 09 09:09:45 PM UTC 24 |
| Finished | Sep 09 09:09:50 PM UTC 24 |
| Peak memory | 219292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=407307936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.lc_ctrl_jtag_csr_rw.407307936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2038985685 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 141481539 ps |
| CPU time | 1.33 seconds |
| Started | Sep 09 09:09:45 PM UTC 24 |
| Finished | Sep 09 09:09:48 PM UTC 24 |
| Peak memory | 220748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2038985685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2038985685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1170871192 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 44479397 ps |
| CPU time | 2.2 seconds |
| Started | Sep 09 09:09:47 PM UTC 24 |
| Finished | Sep 09 09:09:50 PM UTC 24 |
| Peak memory | 219012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117087 1192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc _ctrl_same_csr_outstanding.1170871192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1273815124 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 381165352 ps |
| CPU time | 4.35 seconds |
| Started | Sep 09 09:09:45 PM UTC 24 |
| Finished | Sep 09 09:09:51 PM UTC 24 |
| Peak memory | 229972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273815124 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1273815124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1542966066 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 89028513 ps |
| CPU time | 1.18 seconds |
| Started | Sep 09 09:09:49 PM UTC 24 |
| Finished | Sep 09 09:09:51 PM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542966066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_al iasing.1542966066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3819483312 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 273369488 ps |
| CPU time | 1.41 seconds |
| Started | Sep 09 09:09:49 PM UTC 24 |
| Finished | Sep 09 09:09:52 PM UTC 24 |
| Peak memory | 218676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819483312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bi t_bash.3819483312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.323440290 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 29975110 ps |
| CPU time | 1.34 seconds |
| Started | Sep 09 09:09:48 PM UTC 24 |
| Finished | Sep 09 09:09:51 PM UTC 24 |
| Peak memory | 220208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323440290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_ reset.323440290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3690703956 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 13519282 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 09:09:49 PM UTC 24 |
| Finished | Sep 09 09:09:52 PM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3690703956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3690703956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3347978107 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 16099227 ps |
| CPU time | 1.54 seconds |
| Started | Sep 09 09:09:49 PM UTC 24 |
| Finished | Sep 09 09:09:52 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347978107 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3347978107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1888263070 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 131479793 ps |
| CPU time | 1.51 seconds |
| Started | Sep 09 09:09:48 PM UTC 24 |
| Finished | Sep 09 09:09:51 PM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1888263070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1888263070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.851727212 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 578797296 ps |
| CPU time | 9.39 seconds |
| Started | Sep 09 09:09:48 PM UTC 24 |
| Finished | Sep 09 09:09:58 PM UTC 24 |
| Peak memory | 218912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=851727212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.851727212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1049060593 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 901848780 ps |
| CPU time | 6.79 seconds |
| Started | Sep 09 09:09:48 PM UTC 24 |
| Finished | Sep 09 09:09:56 PM UTC 24 |
| Peak memory | 219488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1049060593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1049060593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2233295512 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 693114392 ps |
| CPU time | 2.15 seconds |
| Started | Sep 09 09:09:48 PM UTC 24 |
| Finished | Sep 09 09:09:51 PM UTC 24 |
| Peak memory | 221828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2233295512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2233295512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.192826914 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 178186438 ps |
| CPU time | 2.31 seconds |
| Started | Sep 09 09:09:48 PM UTC 24 |
| Finished | Sep 09 09:09:51 PM UTC 24 |
| Peak memory | 229848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192826914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_ena bled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.192826914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.697096638 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 154465431 ps |
| CPU time | 1.55 seconds |
| Started | Sep 09 09:09:48 PM UTC 24 |
| Finished | Sep 09 09:09:50 PM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=697096638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.lc_ctrl_jtag_csr_rw.697096638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2550492262 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 23839392 ps |
| CPU time | 1.26 seconds |
| Started | Sep 09 09:09:48 PM UTC 24 |
| Finished | Sep 09 09:09:50 PM UTC 24 |
| Peak memory | 218700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2550492262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2550492262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2779948097 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 159794708 ps |
| CPU time | 1.84 seconds |
| Started | Sep 09 09:09:49 PM UTC 24 |
| Finished | Sep 09 09:09:52 PM UTC 24 |
| Peak memory | 220692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277994 8097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc _ctrl_same_csr_outstanding.2779948097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.526274152 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 37778160 ps |
| CPU time | 2.07 seconds |
| Started | Sep 09 09:09:48 PM UTC 24 |
| Finished | Sep 09 09:09:51 PM UTC 24 |
| Peak memory | 229772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526274152 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.526274152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.350982238 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 41175046 ps |
| CPU time | 1.3 seconds |
| Started | Sep 09 09:09:52 PM UTC 24 |
| Finished | Sep 09 09:09:54 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350982238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_ali asing.350982238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3237746518 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 29072583 ps |
| CPU time | 1.78 seconds |
| Started | Sep 09 09:09:52 PM UTC 24 |
| Finished | Sep 09 09:09:55 PM UTC 24 |
| Peak memory | 219000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237746518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bi t_bash.3237746518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3489767749 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 73426129 ps |
| CPU time | 1.38 seconds |
| Started | Sep 09 09:09:51 PM UTC 24 |
| Finished | Sep 09 09:09:53 PM UTC 24 |
| Peak memory | 230516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489767749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw _reset.3489767749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1219576237 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 54619695 ps |
| CPU time | 1.32 seconds |
| Started | Sep 09 09:09:52 PM UTC 24 |
| Finished | Sep 09 09:09:55 PM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1219576237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1219576237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4188255622 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 26276909 ps |
| CPU time | 1.08 seconds |
| Started | Sep 09 09:09:51 PM UTC 24 |
| Finished | Sep 09 09:09:53 PM UTC 24 |
| Peak memory | 219116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188255622 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.4188255622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1028074203 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 54566779 ps |
| CPU time | 2.01 seconds |
| Started | Sep 09 09:09:51 PM UTC 24 |
| Finished | Sep 09 09:09:54 PM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1028074203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1028074203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3676321185 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 1103459302 ps |
| CPU time | 6.29 seconds |
| Started | Sep 09 09:09:50 PM UTC 24 |
| Finished | Sep 09 09:09:57 PM UTC 24 |
| Peak memory | 219200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3676321185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3676321185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2207011412 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 1933179708 ps |
| CPU time | 10.73 seconds |
| Started | Sep 09 09:09:50 PM UTC 24 |
| Finished | Sep 09 09:10:01 PM UTC 24 |
| Peak memory | 219080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2207011412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2207011412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3496255233 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 603580934 ps |
| CPU time | 2.96 seconds |
| Started | Sep 09 09:09:49 PM UTC 24 |
| Finished | Sep 09 09:09:53 PM UTC 24 |
| Peak memory | 221440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3496255233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3496255233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1929804393 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 110942652 ps |
| CPU time | 3.37 seconds |
| Started | Sep 09 09:09:51 PM UTC 24 |
| Finished | Sep 09 09:09:55 PM UTC 24 |
| Peak memory | 231828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929804393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1929804393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2787242122 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 287837826 ps |
| CPU time | 1.66 seconds |
| Started | Sep 09 09:09:49 PM UTC 24 |
| Finished | Sep 09 09:09:52 PM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2787242122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 4.lc_ctrl_jtag_csr_rw.2787242122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3668148778 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 23981717 ps |
| CPU time | 1.72 seconds |
| Started | Sep 09 09:09:51 PM UTC 24 |
| Finished | Sep 09 09:09:53 PM UTC 24 |
| Peak memory | 218284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3668148778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3668148778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3837601102 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 37635330 ps |
| CPU time | 1.48 seconds |
| Started | Sep 09 09:09:52 PM UTC 24 |
| Finished | Sep 09 09:09:55 PM UTC 24 |
| Peak memory | 218348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383760 1102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc _ctrl_same_csr_outstanding.3837601102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3965277841 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 73929671 ps |
| CPU time | 2.92 seconds |
| Started | Sep 09 09:09:51 PM UTC 24 |
| Finished | Sep 09 09:09:55 PM UTC 24 |
| Peak memory | 229780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965277841 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3965277841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1480087174 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 220963212 ps |
| CPU time | 1.79 seconds |
| Started | Sep 09 09:09:51 PM UTC 24 |
| Finished | Sep 09 09:09:54 PM UTC 24 |
| Peak memory | 228588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480087174 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_ intg_err.1480087174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2583716622 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 17730098 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 09:09:54 PM UTC 24 |
| Finished | Sep 09 09:09:59 PM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2583716622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2583716622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4098686816 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 41220882 ps |
| CPU time | 0.98 seconds |
| Started | Sep 09 09:09:54 PM UTC 24 |
| Finished | Sep 09 09:09:56 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098686816 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.4098686816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.916932765 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 88425285 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 09:09:54 PM UTC 24 |
| Finished | Sep 09 09:09:56 PM UTC 24 |
| Peak memory | 218736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=916932765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.lc_ctrl_jtag_alert_test.916932765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.656122666 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 728917708 ps |
| CPU time | 8.03 seconds |
| Started | Sep 09 09:09:52 PM UTC 24 |
| Finished | Sep 09 09:10:01 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=656122666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.656122666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2081921743 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 5639253170 ps |
| CPU time | 21.57 seconds |
| Started | Sep 09 09:09:52 PM UTC 24 |
| Finished | Sep 09 09:10:15 PM UTC 24 |
| Peak memory | 219432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2081921743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2081921743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2650310412 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 493312616 ps |
| CPU time | 3.28 seconds |
| Started | Sep 09 09:09:52 PM UTC 24 |
| Finished | Sep 09 09:09:57 PM UTC 24 |
| Peak memory | 221440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2650310412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2650310412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.626636594 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 129474313 ps |
| CPU time | 2.52 seconds |
| Started | Sep 09 09:09:52 PM UTC 24 |
| Finished | Sep 09 09:09:56 PM UTC 24 |
| Peak memory | 229848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626636594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_ena bled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.626636594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1120915479 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 746347909 ps |
| CPU time | 2.19 seconds |
| Started | Sep 09 09:09:52 PM UTC 24 |
| Finished | Sep 09 09:09:56 PM UTC 24 |
| Peak memory | 219368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1120915479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 5.lc_ctrl_jtag_csr_rw.1120915479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3836536246 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 36913237 ps |
| CPU time | 1.96 seconds |
| Started | Sep 09 09:09:52 PM UTC 24 |
| Finished | Sep 09 09:09:55 PM UTC 24 |
| Peak memory | 228940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3836536246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3836536246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2450514678 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 118215741 ps |
| CPU time | 1.65 seconds |
| Started | Sep 09 09:09:54 PM UTC 24 |
| Finished | Sep 09 09:10:00 PM UTC 24 |
| Peak memory | 218756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245051 4678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc _ctrl_same_csr_outstanding.2450514678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2172886383 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 76113263 ps |
| CPU time | 2.09 seconds |
| Started | Sep 09 09:09:54 PM UTC 24 |
| Finished | Sep 09 09:09:57 PM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172886383 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2172886383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.341663421 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 78463455 ps |
| CPU time | 1.36 seconds |
| Started | Sep 09 09:09:57 PM UTC 24 |
| Finished | Sep 09 09:10:00 PM UTC 24 |
| Peak memory | 228476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=341663421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.341663421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1615137930 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 12538190 ps |
| CPU time | 1.17 seconds |
| Started | Sep 09 09:09:55 PM UTC 24 |
| Finished | Sep 09 09:10:12 PM UTC 24 |
| Peak memory | 219096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615137930 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1615137930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3607168881 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 235348994 ps |
| CPU time | 1.46 seconds |
| Started | Sep 09 09:09:55 PM UTC 24 |
| Finished | Sep 09 09:10:05 PM UTC 24 |
| Peak memory | 218704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3607168881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3607168881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2071364118 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 1686986467 ps |
| CPU time | 7.44 seconds |
| Started | Sep 09 09:09:55 PM UTC 24 |
| Finished | Sep 09 09:10:11 PM UTC 24 |
| Peak memory | 219392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2071364118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2071364118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3816360473 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 836178283 ps |
| CPU time | 9.71 seconds |
| Started | Sep 09 09:09:55 PM UTC 24 |
| Finished | Sep 09 09:10:13 PM UTC 24 |
| Peak memory | 218736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3816360473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3816360473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4110482939 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 178434276 ps |
| CPU time | 1.41 seconds |
| Started | Sep 09 09:09:54 PM UTC 24 |
| Finished | Sep 09 09:09:59 PM UTC 24 |
| Peak memory | 220744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4110482939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4110482939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3790111593 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 75125652 ps |
| CPU time | 1.54 seconds |
| Started | Sep 09 09:09:55 PM UTC 24 |
| Finished | Sep 09 09:10:05 PM UTC 24 |
| Peak memory | 228468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790111593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3790111593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3331420390 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 531399031 ps |
| CPU time | 2.08 seconds |
| Started | Sep 09 09:09:55 PM UTC 24 |
| Finished | Sep 09 09:10:11 PM UTC 24 |
| Peak memory | 219456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3331420390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 6.lc_ctrl_jtag_csr_rw.3331420390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1777217746 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 15958064 ps |
| CPU time | 1.2 seconds |
| Started | Sep 09 09:09:55 PM UTC 24 |
| Finished | Sep 09 09:10:04 PM UTC 24 |
| Peak memory | 218284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1777217746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1777217746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1433826353 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 22815298 ps |
| CPU time | 1.5 seconds |
| Started | Sep 09 09:09:57 PM UTC 24 |
| Finished | Sep 09 09:10:00 PM UTC 24 |
| Peak memory | 218656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143382 6353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc _ctrl_same_csr_outstanding.1433826353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3470438131 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 141248664 ps |
| CPU time | 4.52 seconds |
| Started | Sep 09 09:09:55 PM UTC 24 |
| Finished | Sep 09 09:10:15 PM UTC 24 |
| Peak memory | 229056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470438131 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3470438131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4229422430 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 281975770 ps |
| CPU time | 3.26 seconds |
| Started | Sep 09 09:09:55 PM UTC 24 |
| Finished | Sep 09 09:10:14 PM UTC 24 |
| Peak memory | 223980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229422430 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_ intg_err.4229422430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2826004681 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 92389505 ps |
| CPU time | 1.29 seconds |
| Started | Sep 09 09:09:58 PM UTC 24 |
| Finished | Sep 09 09:10:10 PM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2826004681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2826004681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1617579261 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 38360776 ps |
| CPU time | 0.82 seconds |
| Started | Sep 09 09:09:57 PM UTC 24 |
| Finished | Sep 09 09:10:10 PM UTC 24 |
| Peak memory | 218340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617579261 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1617579261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2108922237 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 704327135 ps |
| CPU time | 1.44 seconds |
| Started | Sep 09 09:09:57 PM UTC 24 |
| Finished | Sep 09 09:10:10 PM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2108922237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2108922237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.802923715 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 2028738103 ps |
| CPU time | 4.87 seconds |
| Started | Sep 09 09:09:57 PM UTC 24 |
| Finished | Sep 09 09:10:14 PM UTC 24 |
| Peak memory | 219236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=802923715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.802923715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1033272713 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 3826510580 ps |
| CPU time | 9.69 seconds |
| Started | Sep 09 09:09:57 PM UTC 24 |
| Finished | Sep 09 09:10:19 PM UTC 24 |
| Peak memory | 219412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1033272713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1033272713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.824918100 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 359054855 ps |
| CPU time | 2.02 seconds |
| Started | Sep 09 09:09:57 PM UTC 24 |
| Finished | Sep 09 09:10:01 PM UTC 24 |
| Peak memory | 221432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=824918100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.824918100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.64163309 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 652948359 ps |
| CPU time | 3.1 seconds |
| Started | Sep 09 09:09:57 PM UTC 24 |
| Finished | Sep 09 09:10:12 PM UTC 24 |
| Peak memory | 233872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64163309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enab led-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.64163309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.270207739 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 85478211 ps |
| CPU time | 1.4 seconds |
| Started | Sep 09 09:09:57 PM UTC 24 |
| Finished | Sep 09 09:10:00 PM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=270207739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.lc_ctrl_jtag_csr_rw.270207739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1563061236 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 16337569 ps |
| CPU time | 0.95 seconds |
| Started | Sep 09 09:09:57 PM UTC 24 |
| Finished | Sep 09 09:10:10 PM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1563061236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1563061236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2064859991 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 80983199 ps |
| CPU time | 1.37 seconds |
| Started | Sep 09 09:09:58 PM UTC 24 |
| Finished | Sep 09 09:10:10 PM UTC 24 |
| Peak memory | 228528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206485 9991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc _ctrl_same_csr_outstanding.2064859991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3359502885 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 53879468 ps |
| CPU time | 2.65 seconds |
| Started | Sep 09 09:09:57 PM UTC 24 |
| Finished | Sep 09 09:10:12 PM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359502885 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3359502885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1813304819 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 95247023 ps |
| CPU time | 1.43 seconds |
| Started | Sep 09 09:10:02 PM UTC 24 |
| Finished | Sep 09 09:10:12 PM UTC 24 |
| Peak memory | 234616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1813304819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1813304819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1952363388 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 35461764 ps |
| CPU time | 0.84 seconds |
| Started | Sep 09 09:10:01 PM UTC 24 |
| Finished | Sep 09 09:10:12 PM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952363388 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1952363388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2112905952 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 51357169 ps |
| CPU time | 1.68 seconds |
| Started | Sep 09 09:10:00 PM UTC 24 |
| Finished | Sep 09 09:10:10 PM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2112905952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2112905952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2232010858 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 374474464 ps |
| CPU time | 9.42 seconds |
| Started | Sep 09 09:10:00 PM UTC 24 |
| Finished | Sep 09 09:10:18 PM UTC 24 |
| Peak memory | 219276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2232010858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2232010858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4045958554 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 1247363494 ps |
| CPU time | 12.05 seconds |
| Started | Sep 09 09:09:59 PM UTC 24 |
| Finished | Sep 09 09:10:16 PM UTC 24 |
| Peak memory | 218408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4045958554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.4045958554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3347797349 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 134268053 ps |
| CPU time | 2.35 seconds |
| Started | Sep 09 09:09:58 PM UTC 24 |
| Finished | Sep 09 09:10:12 PM UTC 24 |
| Peak memory | 221532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3347797349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3347797349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3243409905 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 64306135 ps |
| CPU time | 2.2 seconds |
| Started | Sep 09 09:10:00 PM UTC 24 |
| Finished | Sep 09 09:10:11 PM UTC 24 |
| Peak memory | 234056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243409905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3243409905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3538901245 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 67240583 ps |
| CPU time | 1.58 seconds |
| Started | Sep 09 09:09:58 PM UTC 24 |
| Finished | Sep 09 09:10:11 PM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3538901245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 8.lc_ctrl_jtag_csr_rw.3538901245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2245847441 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 39228574 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 09:10:00 PM UTC 24 |
| Finished | Sep 09 09:10:09 PM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2245847441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2245847441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3734011443 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 54160502 ps |
| CPU time | 1.5 seconds |
| Started | Sep 09 09:10:02 PM UTC 24 |
| Finished | Sep 09 09:10:12 PM UTC 24 |
| Peak memory | 218704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373401 1443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc _ctrl_same_csr_outstanding.3734011443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.557617431 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 41119979 ps |
| CPU time | 2.44 seconds |
| Started | Sep 09 09:10:01 PM UTC 24 |
| Finished | Sep 09 09:10:06 PM UTC 24 |
| Peak memory | 229824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557617431 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.557617431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2899531394 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 150152229 ps |
| CPU time | 1.61 seconds |
| Started | Sep 09 09:10:01 PM UTC 24 |
| Finished | Sep 09 09:10:05 PM UTC 24 |
| Peak memory | 234732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899531394 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_ intg_err.2899531394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3248739258 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 24857616 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 09:10:10 PM UTC 24 |
| Finished | Sep 09 09:10:13 PM UTC 24 |
| Peak memory | 232568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3248739258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3248739258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.676038378 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 40252283 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 09:10:07 PM UTC 24 |
| Finished | Sep 09 09:10:10 PM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676038378 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.676038378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1559550156 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 80540971 ps |
| CPU time | 1.51 seconds |
| Started | Sep 09 09:10:06 PM UTC 24 |
| Finished | Sep 09 09:10:12 PM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1559550156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1559550156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2360120328 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 195528904 ps |
| CPU time | 2.95 seconds |
| Started | Sep 09 09:10:04 PM UTC 24 |
| Finished | Sep 09 09:10:15 PM UTC 24 |
| Peak memory | 219324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2360120328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2360120328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2316115012 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 4274331750 ps |
| CPU time | 22.2 seconds |
| Started | Sep 09 09:10:04 PM UTC 24 |
| Finished | Sep 09 09:10:34 PM UTC 24 |
| Peak memory | 219452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2316115012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2316115012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3659649216 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 323999424 ps |
| CPU time | 2.4 seconds |
| Started | Sep 09 09:10:03 PM UTC 24 |
| Finished | Sep 09 09:10:13 PM UTC 24 |
| Peak memory | 221384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3659649216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3659649216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.822148791 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 1408703109 ps |
| CPU time | 2.82 seconds |
| Started | Sep 09 09:10:06 PM UTC 24 |
| Finished | Sep 09 09:10:13 PM UTC 24 |
| Peak memory | 231908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822148791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_ena bled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.822148791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1768250728 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 41470650 ps |
| CPU time | 1.52 seconds |
| Started | Sep 09 09:10:03 PM UTC 24 |
| Finished | Sep 09 09:10:12 PM UTC 24 |
| Peak memory | 218268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1768250728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 9.lc_ctrl_jtag_csr_rw.1768250728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.178505020 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 36224966 ps |
| CPU time | 1.12 seconds |
| Started | Sep 09 09:10:05 PM UTC 24 |
| Finished | Sep 09 09:10:10 PM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=178505020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.178505020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.416260306 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 20128342 ps |
| CPU time | 1.33 seconds |
| Started | Sep 09 09:10:08 PM UTC 24 |
| Finished | Sep 09 09:10:10 PM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416260 306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ ctrl_same_csr_outstanding.416260306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.460238257 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 108381892 ps |
| CPU time | 3.21 seconds |
| Started | Sep 09 09:10:06 PM UTC 24 |
| Finished | Sep 09 09:10:13 PM UTC 24 |
| Peak memory | 231748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460238257 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.460238257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3729787399 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 149250147 ps |
| CPU time | 3.1 seconds |
| Started | Sep 09 09:10:06 PM UTC 24 |
| Finished | Sep 09 09:10:13 PM UTC 24 |
| Peak memory | 229776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729787399 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_ intg_err.3729787399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.1584056818 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 8383340738 ps |
| CPU time | 64.57 seconds |
| Started | Sep 09 10:23:59 PM UTC 24 |
| Finished | Sep 09 10:25:05 PM UTC 24 |
| Peak memory | 231948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584056818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jt ag_errors.1584056818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.84417937 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1416090547 ps |
| CPU time | 35.65 seconds |
| Started | Sep 09 10:23:59 PM UTC 24 |
| Finished | Sep 09 10:24:36 PM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84417937 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.84417937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3899100464 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6220467303 ps |
| CPU time | 43.56 seconds |
| Started | Sep 09 10:23:59 PM UTC 24 |
| Finished | Sep 09 10:24:44 PM UTC 24 |
| Peak memory | 229636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899100464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ ctrl_jtag_regwen_during_op.3899100464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.2614127006 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 5935649915 ps |
| CPU time | 98.31 seconds |
| Started | Sep 09 10:23:58 PM UTC 24 |
| Finished | Sep 09 10:25:39 PM UTC 24 |
| Peak memory | 295256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614127006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr l_jtag_state_failure.2614127006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2310165313 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2415939059 ps |
| CPU time | 30.49 seconds |
| Started | Sep 09 10:23:58 PM UTC 24 |
| Finished | Sep 09 10:24:30 PM UTC 24 |
| Peak memory | 262504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310165313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ ctrl_jtag_state_post_trans.2310165313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1249508370 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 57390687 ps |
| CPU time | 1.66 seconds |
| Started | Sep 09 10:23:57 PM UTC 24 |
| Finished | Sep 09 10:24:00 PM UTC 24 |
| Peak memory | 229916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249508370 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1249508370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.2588437531 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1192801902 ps |
| CPU time | 18.05 seconds |
| Started | Sep 09 10:23:58 PM UTC 24 |
| Finished | Sep 09 10:24:17 PM UTC 24 |
| Peak memory | 225472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588437531 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2588437531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.4232475190 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 427481225 ps |
| CPU time | 23.73 seconds |
| Started | Sep 09 10:24:02 PM UTC 24 |
| Finished | Sep 09 10:24:27 PM UTC 24 |
| Peak memory | 296184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232475190 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.4232475190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.288478178 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 366169257 ps |
| CPU time | 24.27 seconds |
| Started | Sep 09 10:23:59 PM UTC 24 |
| Finished | Sep 09 10:24:24 PM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288478178 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.288478178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.4161233801 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 642117870 ps |
| CPU time | 15 seconds |
| Started | Sep 09 10:23:59 PM UTC 24 |
| Finished | Sep 09 10:24:15 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161233801 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_tok en_digest.4161233801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.1240242401 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 425792795 ps |
| CPU time | 3.25 seconds |
| Started | Sep 09 10:23:54 PM UTC 24 |
| Finished | Sep 09 10:23:58 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240242401 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1240242401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3318007077 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 50256389 ps |
| CPU time | 1.16 seconds |
| Started | Sep 09 10:23:54 PM UTC 24 |
| Finished | Sep 09 10:23:56 PM UTC 24 |
| Peak memory | 222352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318007077 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. lc_ctrl_volatile_unlock_smoke.3318007077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.1086106699 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 234217312 ps |
| CPU time | 1.18 seconds |
| Started | Sep 09 10:24:31 PM UTC 24 |
| Finished | Sep 09 10:24:33 PM UTC 24 |
| Peak memory | 218444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086106699 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1086106699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.4238536563 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 38604063 ps |
| CPU time | 1.2 seconds |
| Started | Sep 09 10:24:17 PM UTC 24 |
| Finished | Sep 09 10:24:20 PM UTC 24 |
| Peak memory | 216656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238536563 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.4238536563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.2071075303 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 760110234 ps |
| CPU time | 14.5 seconds |
| Started | Sep 09 10:24:11 PM UTC 24 |
| Finished | Sep 09 10:24:26 PM UTC 24 |
| Peak memory | 232020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071075303 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2071075303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.299910700 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 108225107 ps |
| CPU time | 1.89 seconds |
| Started | Sep 09 10:24:22 PM UTC 24 |
| Finished | Sep 09 10:24:25 PM UTC 24 |
| Peak memory | 229092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299910700 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.299910700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.2738038903 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 16432935358 ps |
| CPU time | 59.67 seconds |
| Started | Sep 09 10:24:20 PM UTC 24 |
| Finished | Sep 09 10:25:21 PM UTC 24 |
| Peak memory | 232072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738038903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jt ag_errors.2738038903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.3823413023 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1384930711 ps |
| CPU time | 41.12 seconds |
| Started | Sep 09 10:24:22 PM UTC 24 |
| Finished | Sep 09 10:25:04 PM UTC 24 |
| Peak memory | 229960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823413023 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_prior ity.3823413023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.779486987 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1141451647 ps |
| CPU time | 8.21 seconds |
| Started | Sep 09 10:24:19 PM UTC 24 |
| Finished | Sep 09 10:24:29 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779486987 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ jtag_prog_failure.779486987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2972740797 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 6801183676 ps |
| CPU time | 21.17 seconds |
| Started | Sep 09 10:24:24 PM UTC 24 |
| Finished | Sep 09 10:24:46 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972740797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ ctrl_jtag_regwen_during_op.2972740797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.3231748449 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 932977543 ps |
| CPU time | 7.58 seconds |
| Started | Sep 09 10:24:19 PM UTC 24 |
| Finished | Sep 09 10:24:28 PM UTC 24 |
| Peak memory | 229516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231748449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_s moke.3231748449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.832225140 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1356084311 ps |
| CPU time | 18.22 seconds |
| Started | Sep 09 10:24:19 PM UTC 24 |
| Finished | Sep 09 10:24:39 PM UTC 24 |
| Peak memory | 259824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832225140 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_c trl_jtag_state_post_trans.832225140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.3261365690 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 167136636 ps |
| CPU time | 5.95 seconds |
| Started | Sep 09 10:24:11 PM UTC 24 |
| Finished | Sep 09 10:24:18 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261365690 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3261365690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.1443965571 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 691961018 ps |
| CPU time | 21.71 seconds |
| Started | Sep 09 10:24:26 PM UTC 24 |
| Finished | Sep 09 10:24:49 PM UTC 24 |
| Peak memory | 232276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443965571 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1443965571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.488190225 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1428723739 ps |
| CPU time | 17.73 seconds |
| Started | Sep 09 10:24:28 PM UTC 24 |
| Finished | Sep 09 10:24:47 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488190225 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_toke n_digest.488190225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.51403903 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 382148740 ps |
| CPU time | 9.73 seconds |
| Started | Sep 09 10:24:26 PM UTC 24 |
| Finished | Sep 09 10:24:37 PM UTC 24 |
| Peak memory | 231948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51403903 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.51403903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.1249742634 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1297668656 ps |
| CPU time | 11.88 seconds |
| Started | Sep 09 10:24:17 PM UTC 24 |
| Finished | Sep 09 10:24:30 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249742634 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1249742634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1988238464 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 163172183 ps |
| CPU time | 11.52 seconds |
| Started | Sep 09 10:24:04 PM UTC 24 |
| Finished | Sep 09 10:24:17 PM UTC 24 |
| Peak memory | 229564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988238464 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1988238464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.1385385443 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 64963505 ps |
| CPU time | 10.02 seconds |
| Started | Sep 09 10:24:11 PM UTC 24 |
| Finished | Sep 09 10:24:22 PM UTC 24 |
| Peak memory | 262512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385385443 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1385385443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.1378610196 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 7161863190 ps |
| CPU time | 81.16 seconds |
| Started | Sep 09 10:24:28 PM UTC 24 |
| Finished | Sep 09 10:25:51 PM UTC 24 |
| Peak memory | 256412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1378610196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.lc_ctrl_stress_all.1378610196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1172750416 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 15524231 ps |
| CPU time | 1.54 seconds |
| Started | Sep 09 10:24:06 PM UTC 24 |
| Finished | Sep 09 10:24:09 PM UTC 24 |
| Peak memory | 222384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172750416 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. lc_ctrl_volatile_unlock_smoke.1172750416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.3574322501 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 19131760 ps |
| CPU time | 1.75 seconds |
| Started | Sep 09 10:27:42 PM UTC 24 |
| Finished | Sep 09 10:27:45 PM UTC 24 |
| Peak memory | 218716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574322501 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3574322501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.1991376241 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 241593825 ps |
| CPU time | 10.42 seconds |
| Started | Sep 09 10:27:32 PM UTC 24 |
| Finished | Sep 09 10:27:44 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991376241 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1991376241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.104076979 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 291134125 ps |
| CPU time | 6.96 seconds |
| Started | Sep 09 10:27:36 PM UTC 24 |
| Finished | Sep 09 10:27:44 PM UTC 24 |
| Peak memory | 229516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104076979 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.104076979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.963902870 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 8170951536 ps |
| CPU time | 74.13 seconds |
| Started | Sep 09 10:27:36 PM UTC 24 |
| Finished | Sep 09 10:28:52 PM UTC 24 |
| Peak memory | 231984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963902870 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt ag_errors.963902870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.3161409935 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 569613797 ps |
| CPU time | 17.64 seconds |
| Started | Sep 09 10:27:35 PM UTC 24 |
| Finished | Sep 09 10:27:54 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161409935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctr l_jtag_prog_failure.3161409935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.2575406700 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1381932443 ps |
| CPU time | 7.26 seconds |
| Started | Sep 09 10:27:33 PM UTC 24 |
| Finished | Sep 09 10:27:42 PM UTC 24 |
| Peak memory | 229484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575406700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_ smoke.2575406700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.3516310424 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 3412717251 ps |
| CPU time | 86.97 seconds |
| Started | Sep 09 10:27:33 PM UTC 24 |
| Finished | Sep 09 10:29:02 PM UTC 24 |
| Peak memory | 287408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516310424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct rl_jtag_state_failure.3516310424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.2090908645 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3121720281 ps |
| CPU time | 17.94 seconds |
| Started | Sep 09 10:27:35 PM UTC 24 |
| Finished | Sep 09 10:27:54 PM UTC 24 |
| Peak memory | 260784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090908645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc _ctrl_jtag_state_post_trans.2090908645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.3032467635 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 17292782 ps |
| CPU time | 2.22 seconds |
| Started | Sep 09 10:27:31 PM UTC 24 |
| Finished | Sep 09 10:27:34 PM UTC 24 |
| Peak memory | 234264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032467635 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3032467635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.1680060001 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4781622264 ps |
| CPU time | 23.77 seconds |
| Started | Sep 09 10:27:39 PM UTC 24 |
| Finished | Sep 09 10:28:05 PM UTC 24 |
| Peak memory | 232016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680060001 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1680060001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.1664487690 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 5060342632 ps |
| CPU time | 12.28 seconds |
| Started | Sep 09 10:27:39 PM UTC 24 |
| Finished | Sep 09 10:27:53 PM UTC 24 |
| Peak memory | 237656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664487690 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_to ken_digest.1664487690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.3738801024 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2805272280 ps |
| CPU time | 6.2 seconds |
| Started | Sep 09 10:27:39 PM UTC 24 |
| Finished | Sep 09 10:27:47 PM UTC 24 |
| Peak memory | 232348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738801024 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token _mux.3738801024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.2634068441 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 405545841 ps |
| CPU time | 10.04 seconds |
| Started | Sep 09 10:27:33 PM UTC 24 |
| Finished | Sep 09 10:27:44 PM UTC 24 |
| Peak memory | 231944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634068441 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2634068441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.4183954414 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 30203783 ps |
| CPU time | 2.22 seconds |
| Started | Sep 09 10:27:26 PM UTC 24 |
| Finished | Sep 09 10:27:29 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183954414 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.4183954414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.1000842815 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 283681830 ps |
| CPU time | 31.14 seconds |
| Started | Sep 09 10:27:29 PM UTC 24 |
| Finished | Sep 09 10:28:02 PM UTC 24 |
| Peak memory | 262832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000842815 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1000842815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.3452234945 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 189756652 ps |
| CPU time | 7.36 seconds |
| Started | Sep 09 10:27:30 PM UTC 24 |
| Finished | Sep 09 10:27:38 PM UTC 24 |
| Peak memory | 260356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452234945 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3452234945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.2715968536 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 9585077586 ps |
| CPU time | 68.84 seconds |
| Started | Sep 09 10:27:41 PM UTC 24 |
| Finished | Sep 09 10:28:52 PM UTC 24 |
| Peak memory | 233996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2715968536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 10.lc_ctrl_stress_all.2715968536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3111755836 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3509223465 ps |
| CPU time | 103.79 seconds |
| Started | Sep 09 10:27:42 PM UTC 24 |
| Finished | Sep 09 10:29:28 PM UTC 24 |
| Peak memory | 279312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111755836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.3111755836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2086474366 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 12914270 ps |
| CPU time | 1.29 seconds |
| Started | Sep 09 10:27:29 PM UTC 24 |
| Finished | Sep 09 10:27:32 PM UTC 24 |
| Peak memory | 218708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086474366 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10 .lc_ctrl_volatile_unlock_smoke.2086474366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.3686376253 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 28916452 ps |
| CPU time | 1.54 seconds |
| Started | Sep 09 10:27:57 PM UTC 24 |
| Finished | Sep 09 10:28:00 PM UTC 24 |
| Peak memory | 218464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686376253 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3686376253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.2309222227 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 707284638 ps |
| CPU time | 21.53 seconds |
| Started | Sep 09 10:27:46 PM UTC 24 |
| Finished | Sep 09 10:28:09 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309222227 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2309222227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.2017040450 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 92138061 ps |
| CPU time | 4 seconds |
| Started | Sep 09 10:27:51 PM UTC 24 |
| Finished | Sep 09 10:27:57 PM UTC 24 |
| Peak memory | 229504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017040450 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2017040450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.3634811819 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 6421177427 ps |
| CPU time | 31.85 seconds |
| Started | Sep 09 10:27:50 PM UTC 24 |
| Finished | Sep 09 10:28:23 PM UTC 24 |
| Peak memory | 237648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634811819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_j tag_errors.3634811819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.399589768 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 61868447 ps |
| CPU time | 2.71 seconds |
| Started | Sep 09 10:27:49 PM UTC 24 |
| Finished | Sep 09 10:27:53 PM UTC 24 |
| Peak memory | 234000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399589768 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl _jtag_prog_failure.399589768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.1517789807 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 2697116063 ps |
| CPU time | 17.03 seconds |
| Started | Sep 09 10:27:48 PM UTC 24 |
| Finished | Sep 09 10:28:06 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517789807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_ smoke.1517789807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.1024821216 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 7086505583 ps |
| CPU time | 54.71 seconds |
| Started | Sep 09 10:27:49 PM UTC 24 |
| Finished | Sep 09 10:28:45 PM UTC 24 |
| Peak memory | 283312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024821216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct rl_jtag_state_failure.1024821216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.4173461399 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 301756911 ps |
| CPU time | 21.76 seconds |
| Started | Sep 09 10:27:49 PM UTC 24 |
| Finished | Sep 09 10:28:12 PM UTC 24 |
| Peak memory | 260784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173461399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc _ctrl_jtag_state_post_trans.4173461399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.1606339115 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 83713893 ps |
| CPU time | 2.26 seconds |
| Started | Sep 09 10:27:46 PM UTC 24 |
| Finished | Sep 09 10:27:50 PM UTC 24 |
| Peak memory | 234004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606339115 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1606339115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.3200564288 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 330156632 ps |
| CPU time | 17.73 seconds |
| Started | Sep 09 10:27:54 PM UTC 24 |
| Finished | Sep 09 10:28:13 PM UTC 24 |
| Peak memory | 237980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200564288 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3200564288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.4209126409 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 332971160 ps |
| CPU time | 14.91 seconds |
| Started | Sep 09 10:27:55 PM UTC 24 |
| Finished | Sep 09 10:28:11 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209126409 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_to ken_digest.4209126409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.693321629 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1117981860 ps |
| CPU time | 14.5 seconds |
| Started | Sep 09 10:27:54 PM UTC 24 |
| Finished | Sep 09 10:28:10 PM UTC 24 |
| Peak memory | 231964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693321629 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_ mux.693321629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.4107839466 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 168987092 ps |
| CPU time | 3.73 seconds |
| Started | Sep 09 10:27:44 PM UTC 24 |
| Finished | Sep 09 10:27:48 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107839466 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.4107839466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.1899379491 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 246774607 ps |
| CPU time | 24.68 seconds |
| Started | Sep 09 10:27:45 PM UTC 24 |
| Finished | Sep 09 10:28:12 PM UTC 24 |
| Peak memory | 262632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899379491 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1899379491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.2755537302 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 91892693 ps |
| CPU time | 12.15 seconds |
| Started | Sep 09 10:27:45 PM UTC 24 |
| Finished | Sep 09 10:27:59 PM UTC 24 |
| Peak memory | 262508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755537302 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2755537302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.2400796963 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 8905153236 ps |
| CPU time | 231.84 seconds |
| Started | Sep 09 10:27:55 PM UTC 24 |
| Finished | Sep 09 10:31:50 PM UTC 24 |
| Peak memory | 262580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2400796963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 11.lc_ctrl_stress_all.2400796963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1297092188 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 126736308 ps |
| CPU time | 1.44 seconds |
| Started | Sep 09 10:27:45 PM UTC 24 |
| Finished | Sep 09 10:27:48 PM UTC 24 |
| Peak memory | 228688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297092188 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11 .lc_ctrl_volatile_unlock_smoke.1297092188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.3224216659 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 83313988 ps |
| CPU time | 1.31 seconds |
| Started | Sep 09 10:28:17 PM UTC 24 |
| Finished | Sep 09 10:28:19 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224216659 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3224216659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.2187511378 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2450324041 ps |
| CPU time | 34.59 seconds |
| Started | Sep 09 10:28:04 PM UTC 24 |
| Finished | Sep 09 10:28:40 PM UTC 24 |
| Peak memory | 237988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187511378 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2187511378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.4058607818 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 154768293 ps |
| CPU time | 3.77 seconds |
| Started | Sep 09 10:28:11 PM UTC 24 |
| Finished | Sep 09 10:28:16 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058607818 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.4058607818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.3045439516 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 19589414014 ps |
| CPU time | 86.37 seconds |
| Started | Sep 09 10:28:10 PM UTC 24 |
| Finished | Sep 09 10:29:38 PM UTC 24 |
| Peak memory | 237576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045439516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_j tag_errors.3045439516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.259705856 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1747157107 ps |
| CPU time | 6.23 seconds |
| Started | Sep 09 10:28:10 PM UTC 24 |
| Finished | Sep 09 10:28:17 PM UTC 24 |
| Peak memory | 231804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259705856 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl _jtag_prog_failure.259705856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.1086903170 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 279029007 ps |
| CPU time | 4.09 seconds |
| Started | Sep 09 10:28:05 PM UTC 24 |
| Finished | Sep 09 10:28:11 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086903170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_ smoke.1086903170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.1208316987 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 1896148587 ps |
| CPU time | 71.74 seconds |
| Started | Sep 09 10:28:06 PM UTC 24 |
| Finished | Sep 09 10:29:20 PM UTC 24 |
| Peak memory | 287088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208316987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct rl_jtag_state_failure.1208316987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.6701687 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 4383527365 ps |
| CPU time | 23.01 seconds |
| Started | Sep 09 10:28:09 PM UTC 24 |
| Finished | Sep 09 10:28:33 PM UTC 24 |
| Peak memory | 260552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6701687 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct rl_jtag_state_post_trans.6701687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.3814107040 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 182126176 ps |
| CPU time | 4.34 seconds |
| Started | Sep 09 10:28:03 PM UTC 24 |
| Finished | Sep 09 10:28:08 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814107040 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3814107040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.740451361 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 269541291 ps |
| CPU time | 16.2 seconds |
| Started | Sep 09 10:28:11 PM UTC 24 |
| Finished | Sep 09 10:28:28 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740451361 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.740451361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.639025208 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 283586210 ps |
| CPU time | 13.87 seconds |
| Started | Sep 09 10:28:12 PM UTC 24 |
| Finished | Sep 09 10:28:27 PM UTC 24 |
| Peak memory | 237516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639025208 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_tok en_digest.639025208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.1576785460 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 292281848 ps |
| CPU time | 16.93 seconds |
| Started | Sep 09 10:28:12 PM UTC 24 |
| Finished | Sep 09 10:28:31 PM UTC 24 |
| Peak memory | 231944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576785460 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token _mux.1576785460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.588978661 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 585358739 ps |
| CPU time | 17.45 seconds |
| Started | Sep 09 10:28:04 PM UTC 24 |
| Finished | Sep 09 10:28:23 PM UTC 24 |
| Peak memory | 237728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588978661 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.588978661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.3933493028 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 73264436 ps |
| CPU time | 3.52 seconds |
| Started | Sep 09 10:27:57 PM UTC 24 |
| Finished | Sep 09 10:28:02 PM UTC 24 |
| Peak memory | 235700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933493028 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3933493028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.3271682710 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 343510414 ps |
| CPU time | 24.59 seconds |
| Started | Sep 09 10:28:02 PM UTC 24 |
| Finished | Sep 09 10:28:27 PM UTC 24 |
| Peak memory | 260452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271682710 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3271682710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.2935359858 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 47320876 ps |
| CPU time | 3.82 seconds |
| Started | Sep 09 10:28:03 PM UTC 24 |
| Finished | Sep 09 10:28:08 PM UTC 24 |
| Peak memory | 234256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935359858 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2935359858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.2688468795 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 12889970090 ps |
| CPU time | 76.31 seconds |
| Started | Sep 09 10:28:14 PM UTC 24 |
| Finished | Sep 09 10:29:32 PM UTC 24 |
| Peak memory | 262568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2688468795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 12.lc_ctrl_stress_all.2688468795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3389809276 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 15959606 ps |
| CPU time | 1.44 seconds |
| Started | Sep 09 10:28:00 PM UTC 24 |
| Finished | Sep 09 10:28:03 PM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389809276 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12 .lc_ctrl_volatile_unlock_smoke.3389809276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.1054925057 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 42762252 ps |
| CPU time | 1.33 seconds |
| Started | Sep 09 10:28:42 PM UTC 24 |
| Finished | Sep 09 10:28:44 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054925057 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1054925057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_errors.2875778249 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 929086436 ps |
| CPU time | 15.49 seconds |
| Started | Sep 09 10:28:25 PM UTC 24 |
| Finished | Sep 09 10:28:41 PM UTC 24 |
| Peak memory | 237668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875778249 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2875778249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.3868468820 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 932465447 ps |
| CPU time | 7.58 seconds |
| Started | Sep 09 10:28:32 PM UTC 24 |
| Finished | Sep 09 10:28:41 PM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868468820 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3868468820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.2212045458 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 6758905359 ps |
| CPU time | 70.71 seconds |
| Started | Sep 09 10:28:30 PM UTC 24 |
| Finished | Sep 09 10:29:42 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212045458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_j tag_errors.2212045458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.1511685427 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 744965366 ps |
| CPU time | 7.42 seconds |
| Started | Sep 09 10:28:28 PM UTC 24 |
| Finished | Sep 09 10:28:37 PM UTC 24 |
| Peak memory | 231812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511685427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctr l_jtag_prog_failure.1511685427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.2401336048 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 186988626 ps |
| CPU time | 4.81 seconds |
| Started | Sep 09 10:28:25 PM UTC 24 |
| Finished | Sep 09 10:28:31 PM UTC 24 |
| Peak memory | 229484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401336048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_ smoke.2401336048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.217395492 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 4398500884 ps |
| CPU time | 52.15 seconds |
| Started | Sep 09 10:28:28 PM UTC 24 |
| Finished | Sep 09 10:29:22 PM UTC 24 |
| Peak memory | 285096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217395492 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctr l_jtag_state_failure.217395492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.2205955016 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 540109982 ps |
| CPU time | 19.15 seconds |
| Started | Sep 09 10:28:28 PM UTC 24 |
| Finished | Sep 09 10:28:49 PM UTC 24 |
| Peak memory | 258332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205955016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc _ctrl_jtag_state_post_trans.2205955016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.479191545 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 861203470 ps |
| CPU time | 3.52 seconds |
| Started | Sep 09 10:28:23 PM UTC 24 |
| Finished | Sep 09 10:28:28 PM UTC 24 |
| Peak memory | 236376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479191545 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.479191545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.901101626 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1345737053 ps |
| CPU time | 20.23 seconds |
| Started | Sep 09 10:28:32 PM UTC 24 |
| Finished | Sep 09 10:28:53 PM UTC 24 |
| Peak memory | 237576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901101626 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.901101626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.3097293618 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 375840533 ps |
| CPU time | 15.26 seconds |
| Started | Sep 09 10:28:37 PM UTC 24 |
| Finished | Sep 09 10:28:53 PM UTC 24 |
| Peak memory | 231816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097293618 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_to ken_digest.3097293618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.2123818718 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 395956797 ps |
| CPU time | 13.8 seconds |
| Started | Sep 09 10:28:34 PM UTC 24 |
| Finished | Sep 09 10:28:49 PM UTC 24 |
| Peak memory | 231944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123818718 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token _mux.2123818718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.2791586911 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 39422405 ps |
| CPU time | 1.6 seconds |
| Started | Sep 09 10:28:18 PM UTC 24 |
| Finished | Sep 09 10:28:21 PM UTC 24 |
| Peak memory | 222316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791586911 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2791586911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.605744552 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 284065088 ps |
| CPU time | 11.42 seconds |
| Started | Sep 09 10:28:23 PM UTC 24 |
| Finished | Sep 09 10:28:36 PM UTC 24 |
| Peak memory | 262524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605744552 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.605744552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.254104001 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 8503085323 ps |
| CPU time | 38.78 seconds |
| Started | Sep 09 10:28:38 PM UTC 24 |
| Finished | Sep 09 10:29:18 PM UTC 24 |
| Peak memory | 260600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=254104001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 13.lc_ctrl_stress_all.254104001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.743795670 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 9499908878 ps |
| CPU time | 174.45 seconds |
| Started | Sep 09 10:28:42 PM UTC 24 |
| Finished | Sep 09 10:31:39 PM UTC 24 |
| Peak memory | 289416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743795670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.743795670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2863657077 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 13836326 ps |
| CPU time | 1.47 seconds |
| Started | Sep 09 10:28:20 PM UTC 24 |
| Finished | Sep 09 10:28:23 PM UTC 24 |
| Peak memory | 222380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863657077 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13 .lc_ctrl_volatile_unlock_smoke.2863657077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.104281423 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 51105119 ps |
| CPU time | 1.41 seconds |
| Started | Sep 09 10:29:03 PM UTC 24 |
| Finished | Sep 09 10:29:06 PM UTC 24 |
| Peak memory | 217376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104281423 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.104281423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_errors.805888357 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2771548123 ps |
| CPU time | 34.2 seconds |
| Started | Sep 09 10:28:46 PM UTC 24 |
| Finished | Sep 09 10:29:22 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805888357 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.805888357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.227511887 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 14617813616 ps |
| CPU time | 22.09 seconds |
| Started | Sep 09 10:28:53 PM UTC 24 |
| Finished | Sep 09 10:29:17 PM UTC 24 |
| Peak memory | 229608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227511887 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.227511887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.2620883914 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1232213025 ps |
| CPU time | 24.47 seconds |
| Started | Sep 09 10:28:52 PM UTC 24 |
| Finished | Sep 09 10:29:18 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620883914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_j tag_errors.2620883914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.1954568680 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 751351398 ps |
| CPU time | 22.99 seconds |
| Started | Sep 09 10:28:50 PM UTC 24 |
| Finished | Sep 09 10:29:14 PM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954568680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctr l_jtag_prog_failure.1954568680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.82809161 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 485300400 ps |
| CPU time | 2.98 seconds |
| Started | Sep 09 10:28:49 PM UTC 24 |
| Finished | Sep 09 10:28:53 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82809161 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.82809161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.1201023761 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 5814682435 ps |
| CPU time | 116.55 seconds |
| Started | Sep 09 10:28:50 PM UTC 24 |
| Finished | Sep 09 10:30:49 PM UTC 24 |
| Peak memory | 295472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201023761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct rl_jtag_state_failure.1201023761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.2842265914 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1847711332 ps |
| CPU time | 22.01 seconds |
| Started | Sep 09 10:28:50 PM UTC 24 |
| Finished | Sep 09 10:29:13 PM UTC 24 |
| Peak memory | 262528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842265914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc _ctrl_jtag_state_post_trans.2842265914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.953395061 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 16600282 ps |
| CPU time | 1.96 seconds |
| Started | Sep 09 10:28:46 PM UTC 24 |
| Finished | Sep 09 10:28:49 PM UTC 24 |
| Peak memory | 231968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953395061 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.953395061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.1326340124 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 571590431 ps |
| CPU time | 24.03 seconds |
| Started | Sep 09 10:28:53 PM UTC 24 |
| Finished | Sep 09 10:29:19 PM UTC 24 |
| Peak memory | 237668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326340124 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1326340124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.3721329940 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 2994237913 ps |
| CPU time | 17.04 seconds |
| Started | Sep 09 10:28:55 PM UTC 24 |
| Finished | Sep 09 10:29:13 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721329940 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_to ken_digest.3721329940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.3580297198 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 296469899 ps |
| CPU time | 9.84 seconds |
| Started | Sep 09 10:28:55 PM UTC 24 |
| Finished | Sep 09 10:29:06 PM UTC 24 |
| Peak memory | 231948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580297198 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token _mux.3580297198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.1005719196 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 1742771506 ps |
| CPU time | 13.41 seconds |
| Started | Sep 09 10:28:46 PM UTC 24 |
| Finished | Sep 09 10:29:01 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005719196 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1005719196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.3777587652 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 327198423 ps |
| CPU time | 3.09 seconds |
| Started | Sep 09 10:28:42 PM UTC 24 |
| Finished | Sep 09 10:28:46 PM UTC 24 |
| Peak memory | 225480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777587652 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3777587652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.3485007662 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 839581070 ps |
| CPU time | 32.23 seconds |
| Started | Sep 09 10:28:45 PM UTC 24 |
| Finished | Sep 09 10:29:19 PM UTC 24 |
| Peak memory | 260528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485007662 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3485007662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.1642080687 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 489582623 ps |
| CPU time | 11.46 seconds |
| Started | Sep 09 10:28:45 PM UTC 24 |
| Finished | Sep 09 10:28:58 PM UTC 24 |
| Peak memory | 262404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642080687 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1642080687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.2011639700 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 6625302095 ps |
| CPU time | 94.46 seconds |
| Started | Sep 09 10:28:59 PM UTC 24 |
| Finished | Sep 09 10:30:35 PM UTC 24 |
| Peak memory | 262644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2011639700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 14.lc_ctrl_stress_all.2011639700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1026433774 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 16117653 ps |
| CPU time | 1.6 seconds |
| Started | Sep 09 10:28:43 PM UTC 24 |
| Finished | Sep 09 10:28:46 PM UTC 24 |
| Peak memory | 222384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026433774 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14 .lc_ctrl_volatile_unlock_smoke.1026433774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.26817396 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 33565132 ps |
| CPU time | 1.48 seconds |
| Started | Sep 09 10:29:23 PM UTC 24 |
| Finished | Sep 09 10:29:26 PM UTC 24 |
| Peak memory | 218584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26817396 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.26817396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_errors.4180600883 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 283521583 ps |
| CPU time | 20.74 seconds |
| Started | Sep 09 10:29:10 PM UTC 24 |
| Finished | Sep 09 10:29:32 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180600883 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.4180600883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.4054448664 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 324008744 ps |
| CPU time | 8.56 seconds |
| Started | Sep 09 10:29:20 PM UTC 24 |
| Finished | Sep 09 10:29:30 PM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054448664 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.4054448664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.4122090029 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3019040963 ps |
| CPU time | 30.04 seconds |
| Started | Sep 09 10:29:18 PM UTC 24 |
| Finished | Sep 09 10:29:49 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122090029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_j tag_errors.4122090029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.1441760966 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1103200730 ps |
| CPU time | 14.06 seconds |
| Started | Sep 09 10:29:16 PM UTC 24 |
| Finished | Sep 09 10:29:31 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441760966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctr l_jtag_prog_failure.1441760966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.3420386818 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 320818240 ps |
| CPU time | 7.48 seconds |
| Started | Sep 09 10:29:15 PM UTC 24 |
| Finished | Sep 09 10:29:23 PM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420386818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_ smoke.3420386818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.1366601536 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 8027271616 ps |
| CPU time | 59.33 seconds |
| Started | Sep 09 10:29:15 PM UTC 24 |
| Finished | Sep 09 10:30:15 PM UTC 24 |
| Peak memory | 291504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366601536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct rl_jtag_state_failure.1366601536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.2821748719 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 657640096 ps |
| CPU time | 29.79 seconds |
| Started | Sep 09 10:29:16 PM UTC 24 |
| Finished | Sep 09 10:29:47 PM UTC 24 |
| Peak memory | 262768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821748719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc _ctrl_jtag_state_post_trans.2821748719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.3696667949 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 48889618 ps |
| CPU time | 3.07 seconds |
| Started | Sep 09 10:29:09 PM UTC 24 |
| Finished | Sep 09 10:29:13 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696667949 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3696667949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.3684062873 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1469674151 ps |
| CPU time | 21.65 seconds |
| Started | Sep 09 10:29:20 PM UTC 24 |
| Finished | Sep 09 10:29:43 PM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684062873 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3684062873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.755088774 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 274413942 ps |
| CPU time | 18.64 seconds |
| Started | Sep 09 10:29:20 PM UTC 24 |
| Finished | Sep 09 10:29:40 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755088774 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_tok en_digest.755088774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.942606510 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 277305143 ps |
| CPU time | 11.23 seconds |
| Started | Sep 09 10:29:20 PM UTC 24 |
| Finished | Sep 09 10:29:32 PM UTC 24 |
| Peak memory | 237936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942606510 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_ mux.942606510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.2518757963 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 459823552 ps |
| CPU time | 10.24 seconds |
| Started | Sep 09 10:29:15 PM UTC 24 |
| Finished | Sep 09 10:29:26 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518757963 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2518757963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.719113209 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 24480855 ps |
| CPU time | 2.16 seconds |
| Started | Sep 09 10:29:06 PM UTC 24 |
| Finished | Sep 09 10:29:09 PM UTC 24 |
| Peak memory | 229824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719113209 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.719113209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.2454316737 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 370309213 ps |
| CPU time | 28.82 seconds |
| Started | Sep 09 10:29:07 PM UTC 24 |
| Finished | Sep 09 10:29:37 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454316737 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2454316737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.1121715571 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 521580826 ps |
| CPU time | 5.13 seconds |
| Started | Sep 09 10:29:08 PM UTC 24 |
| Finished | Sep 09 10:29:14 PM UTC 24 |
| Peak memory | 234332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121715571 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1121715571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.341472499 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 15102825 ps |
| CPU time | 1.18 seconds |
| Started | Sep 09 10:29:07 PM UTC 24 |
| Finished | Sep 09 10:29:09 PM UTC 24 |
| Peak memory | 218176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341472499 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15. lc_ctrl_volatile_unlock_smoke.341472499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.4089787204 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 44426158 ps |
| CPU time | 2.06 seconds |
| Started | Sep 09 10:29:43 PM UTC 24 |
| Finished | Sep 09 10:29:46 PM UTC 24 |
| Peak memory | 219080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089787204 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.4089787204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_errors.3174874980 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 883670158 ps |
| CPU time | 16.35 seconds |
| Started | Sep 09 10:29:30 PM UTC 24 |
| Finished | Sep 09 10:29:48 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174874980 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3174874980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.1630419618 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 283443226 ps |
| CPU time | 7.19 seconds |
| Started | Sep 09 10:29:35 PM UTC 24 |
| Finished | Sep 09 10:29:44 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630419618 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1630419618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.4197580610 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 1581310895 ps |
| CPU time | 52.73 seconds |
| Started | Sep 09 10:29:35 PM UTC 24 |
| Finished | Sep 09 10:30:30 PM UTC 24 |
| Peak memory | 231804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197580610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_j tag_errors.4197580610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.1487250207 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 453643856 ps |
| CPU time | 11.34 seconds |
| Started | Sep 09 10:29:33 PM UTC 24 |
| Finished | Sep 09 10:29:46 PM UTC 24 |
| Peak memory | 235904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487250207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctr l_jtag_prog_failure.1487250207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.600610016 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 204076496 ps |
| CPU time | 8.43 seconds |
| Started | Sep 09 10:29:31 PM UTC 24 |
| Finished | Sep 09 10:29:41 PM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600610016 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_s moke.600610016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.3618841296 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 3941379673 ps |
| CPU time | 68.84 seconds |
| Started | Sep 09 10:29:33 PM UTC 24 |
| Finished | Sep 09 10:30:44 PM UTC 24 |
| Peak memory | 282984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618841296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct rl_jtag_state_failure.3618841296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.738610367 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4889790727 ps |
| CPU time | 22.2 seconds |
| Started | Sep 09 10:29:33 PM UTC 24 |
| Finished | Sep 09 10:29:57 PM UTC 24 |
| Peak memory | 262512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738610367 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ ctrl_jtag_state_post_trans.738610367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.4007264647 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 698561250 ps |
| CPU time | 3.99 seconds |
| Started | Sep 09 10:29:29 PM UTC 24 |
| Finished | Sep 09 10:29:34 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007264647 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.4007264647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.4040626990 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 7596223576 ps |
| CPU time | 12.39 seconds |
| Started | Sep 09 10:29:38 PM UTC 24 |
| Finished | Sep 09 10:29:51 PM UTC 24 |
| Peak memory | 237852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040626990 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.4040626990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.1385842359 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 869786353 ps |
| CPU time | 22.8 seconds |
| Started | Sep 09 10:29:40 PM UTC 24 |
| Finished | Sep 09 10:30:04 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385842359 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_to ken_digest.1385842359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.815229079 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 270649919 ps |
| CPU time | 8.99 seconds |
| Started | Sep 09 10:29:39 PM UTC 24 |
| Finished | Sep 09 10:29:49 PM UTC 24 |
| Peak memory | 231964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815229079 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_ mux.815229079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.933776957 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 323343297 ps |
| CPU time | 14.54 seconds |
| Started | Sep 09 10:29:30 PM UTC 24 |
| Finished | Sep 09 10:29:46 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933776957 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.933776957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.525050718 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 24891106 ps |
| CPU time | 1.52 seconds |
| Started | Sep 09 10:29:24 PM UTC 24 |
| Finished | Sep 09 10:29:27 PM UTC 24 |
| Peak memory | 222324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525050718 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.525050718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.1878888405 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1476335062 ps |
| CPU time | 32.2 seconds |
| Started | Sep 09 10:29:27 PM UTC 24 |
| Finished | Sep 09 10:30:00 PM UTC 24 |
| Peak memory | 262640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878888405 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1878888405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.2060670218 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 286425172 ps |
| CPU time | 11.01 seconds |
| Started | Sep 09 10:29:28 PM UTC 24 |
| Finished | Sep 09 10:29:40 PM UTC 24 |
| Peak memory | 262572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060670218 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2060670218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.2185465533 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 20897409426 ps |
| CPU time | 95.42 seconds |
| Started | Sep 09 10:29:41 PM UTC 24 |
| Finished | Sep 09 10:31:19 PM UTC 24 |
| Peak memory | 291628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2185465533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 16.lc_ctrl_stress_all.2185465533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2187454661 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 48527175 ps |
| CPU time | 1.38 seconds |
| Started | Sep 09 10:29:27 PM UTC 24 |
| Finished | Sep 09 10:29:29 PM UTC 24 |
| Peak memory | 228440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187454661 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16 .lc_ctrl_volatile_unlock_smoke.2187454661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.1038561316 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 24370970 ps |
| CPU time | 1.62 seconds |
| Started | Sep 09 10:29:58 PM UTC 24 |
| Finished | Sep 09 10:30:00 PM UTC 24 |
| Peak memory | 218528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038561316 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1038561316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_errors.3261426744 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1891230766 ps |
| CPU time | 23.6 seconds |
| Started | Sep 09 10:29:47 PM UTC 24 |
| Finished | Sep 09 10:30:12 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261426744 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3261426744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.1472149452 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 875260904 ps |
| CPU time | 14.84 seconds |
| Started | Sep 09 10:29:51 PM UTC 24 |
| Finished | Sep 09 10:30:06 PM UTC 24 |
| Peak memory | 229612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472149452 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1472149452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.1932484626 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1208604724 ps |
| CPU time | 44.17 seconds |
| Started | Sep 09 10:29:51 PM UTC 24 |
| Finished | Sep 09 10:30:36 PM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932484626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_j tag_errors.1932484626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.3936655806 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 1096743362 ps |
| CPU time | 16.73 seconds |
| Started | Sep 09 10:29:49 PM UTC 24 |
| Finished | Sep 09 10:30:07 PM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936655806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctr l_jtag_prog_failure.3936655806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.288776804 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 947801728 ps |
| CPU time | 4.07 seconds |
| Started | Sep 09 10:29:48 PM UTC 24 |
| Finished | Sep 09 10:29:53 PM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288776804 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_s moke.288776804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.4150692747 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 4847587241 ps |
| CPU time | 55.65 seconds |
| Started | Sep 09 10:29:48 PM UTC 24 |
| Finished | Sep 09 10:30:45 PM UTC 24 |
| Peak memory | 262496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150692747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct rl_jtag_state_failure.4150692747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.507181379 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 1211465654 ps |
| CPU time | 19.21 seconds |
| Started | Sep 09 10:29:48 PM UTC 24 |
| Finished | Sep 09 10:30:08 PM UTC 24 |
| Peak memory | 262432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507181379 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ ctrl_jtag_state_post_trans.507181379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.3098371587 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1411224523 ps |
| CPU time | 4.19 seconds |
| Started | Sep 09 10:29:47 PM UTC 24 |
| Finished | Sep 09 10:29:52 PM UTC 24 |
| Peak memory | 231832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098371587 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3098371587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.4105301144 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 331568240 ps |
| CPU time | 15.18 seconds |
| Started | Sep 09 10:29:52 PM UTC 24 |
| Finished | Sep 09 10:30:08 PM UTC 24 |
| Peak memory | 237924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105301144 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.4105301144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.953525742 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 2532523508 ps |
| CPU time | 24.44 seconds |
| Started | Sep 09 10:29:54 PM UTC 24 |
| Finished | Sep 09 10:30:20 PM UTC 24 |
| Peak memory | 237712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953525742 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_tok en_digest.953525742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.3117593944 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 5313709956 ps |
| CPU time | 7.5 seconds |
| Started | Sep 09 10:29:53 PM UTC 24 |
| Finished | Sep 09 10:30:01 PM UTC 24 |
| Peak memory | 232260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117593944 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token _mux.3117593944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.1650153124 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 322051018 ps |
| CPU time | 14.59 seconds |
| Started | Sep 09 10:29:47 PM UTC 24 |
| Finished | Sep 09 10:30:03 PM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650153124 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1650153124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.4194469505 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 56122302 ps |
| CPU time | 3.13 seconds |
| Started | Sep 09 10:29:43 PM UTC 24 |
| Finished | Sep 09 10:29:47 PM UTC 24 |
| Peak memory | 235700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194469505 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.4194469505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.1001139806 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 3308116236 ps |
| CPU time | 24.38 seconds |
| Started | Sep 09 10:29:44 PM UTC 24 |
| Finished | Sep 09 10:30:10 PM UTC 24 |
| Peak memory | 262868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001139806 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1001139806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.4040286522 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 203423273 ps |
| CPU time | 9.91 seconds |
| Started | Sep 09 10:29:44 PM UTC 24 |
| Finished | Sep 09 10:29:56 PM UTC 24 |
| Peak memory | 260524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040286522 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.4040286522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.2597228608 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 4304381680 ps |
| CPU time | 164.06 seconds |
| Started | Sep 09 10:29:55 PM UTC 24 |
| Finished | Sep 09 10:32:43 PM UTC 24 |
| Peak memory | 280996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2597228608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 17.lc_ctrl_stress_all.2597228608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1664109829 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 41512309 ps |
| CPU time | 1.43 seconds |
| Started | Sep 09 10:29:44 PM UTC 24 |
| Finished | Sep 09 10:29:47 PM UTC 24 |
| Peak memory | 222376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664109829 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17 .lc_ctrl_volatile_unlock_smoke.1664109829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.2726521794 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 14356943 ps |
| CPU time | 1.36 seconds |
| Started | Sep 09 10:30:21 PM UTC 24 |
| Finished | Sep 09 10:30:23 PM UTC 24 |
| Peak memory | 218700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726521794 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2726521794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_errors.3645774940 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 271775730 ps |
| CPU time | 12.39 seconds |
| Started | Sep 09 10:30:06 PM UTC 24 |
| Finished | Sep 09 10:30:19 PM UTC 24 |
| Peak memory | 237592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645774940 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3645774940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.3231892342 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 521243563 ps |
| CPU time | 8.95 seconds |
| Started | Sep 09 10:30:12 PM UTC 24 |
| Finished | Sep 09 10:30:22 PM UTC 24 |
| Peak memory | 229632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231892342 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3231892342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.3645945477 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 12752501144 ps |
| CPU time | 99.73 seconds |
| Started | Sep 09 10:30:09 PM UTC 24 |
| Finished | Sep 09 10:31:51 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645945477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_j tag_errors.3645945477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.1584045354 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 6536531027 ps |
| CPU time | 15.46 seconds |
| Started | Sep 09 10:30:09 PM UTC 24 |
| Finished | Sep 09 10:30:26 PM UTC 24 |
| Peak memory | 237916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584045354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctr l_jtag_prog_failure.1584045354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.401606885 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 550095390 ps |
| CPU time | 3.43 seconds |
| Started | Sep 09 10:30:08 PM UTC 24 |
| Finished | Sep 09 10:30:12 PM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401606885 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_s moke.401606885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.1778071490 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 7481932373 ps |
| CPU time | 121.72 seconds |
| Started | Sep 09 10:30:09 PM UTC 24 |
| Finished | Sep 09 10:32:13 PM UTC 24 |
| Peak memory | 295268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778071490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct rl_jtag_state_failure.1778071490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.3991620372 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 3343213991 ps |
| CPU time | 14.07 seconds |
| Started | Sep 09 10:30:09 PM UTC 24 |
| Finished | Sep 09 10:30:24 PM UTC 24 |
| Peak memory | 237920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991620372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc _ctrl_jtag_state_post_trans.3991620372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.1508969591 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 88564121 ps |
| CPU time | 5.75 seconds |
| Started | Sep 09 10:30:04 PM UTC 24 |
| Finished | Sep 09 10:30:11 PM UTC 24 |
| Peak memory | 232280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508969591 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1508969591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.1261988709 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 3660547310 ps |
| CPU time | 13.37 seconds |
| Started | Sep 09 10:30:12 PM UTC 24 |
| Finished | Sep 09 10:30:26 PM UTC 24 |
| Peak memory | 237780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261988709 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1261988709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.3116695294 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 317704737 ps |
| CPU time | 20.43 seconds |
| Started | Sep 09 10:30:13 PM UTC 24 |
| Finished | Sep 09 10:30:35 PM UTC 24 |
| Peak memory | 231804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116695294 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_to ken_digest.3116695294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.207664771 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 185411973 ps |
| CPU time | 7.14 seconds |
| Started | Sep 09 10:30:13 PM UTC 24 |
| Finished | Sep 09 10:30:21 PM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207664771 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_ mux.207664771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.3615652158 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 227629360 ps |
| CPU time | 11.29 seconds |
| Started | Sep 09 10:30:08 PM UTC 24 |
| Finished | Sep 09 10:30:20 PM UTC 24 |
| Peak memory | 237652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615652158 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3615652158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.1318715626 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 245979446 ps |
| CPU time | 5.69 seconds |
| Started | Sep 09 10:30:01 PM UTC 24 |
| Finished | Sep 09 10:30:08 PM UTC 24 |
| Peak memory | 229696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318715626 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1318715626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.434776296 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 193650813 ps |
| CPU time | 20.36 seconds |
| Started | Sep 09 10:30:02 PM UTC 24 |
| Finished | Sep 09 10:30:24 PM UTC 24 |
| Peak memory | 260848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434776296 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.434776296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.2904192345 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 66334107 ps |
| CPU time | 3.76 seconds |
| Started | Sep 09 10:30:03 PM UTC 24 |
| Finished | Sep 09 10:30:08 PM UTC 24 |
| Peak memory | 236300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904192345 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2904192345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.3342772869 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1460830662 ps |
| CPU time | 36.59 seconds |
| Started | Sep 09 10:30:20 PM UTC 24 |
| Finished | Sep 09 10:30:58 PM UTC 24 |
| Peak memory | 262644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342772869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.3342772869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3577738066 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 123446046 ps |
| CPU time | 1.17 seconds |
| Started | Sep 09 10:30:01 PM UTC 24 |
| Finished | Sep 09 10:30:03 PM UTC 24 |
| Peak memory | 218148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577738066 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18 .lc_ctrl_volatile_unlock_smoke.3577738066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.1023339605 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 478956723 ps |
| CPU time | 2.4 seconds |
| Started | Sep 09 10:30:36 PM UTC 24 |
| Finished | Sep 09 10:30:40 PM UTC 24 |
| Peak memory | 218984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023339605 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1023339605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_errors.632823325 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1531127423 ps |
| CPU time | 15.35 seconds |
| Started | Sep 09 10:30:26 PM UTC 24 |
| Finished | Sep 09 10:30:42 PM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632823325 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.632823325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.1793368637 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 132030680 ps |
| CPU time | 3.51 seconds |
| Started | Sep 09 10:30:30 PM UTC 24 |
| Finished | Sep 09 10:30:35 PM UTC 24 |
| Peak memory | 229508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793368637 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1793368637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.1105411558 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 10326361889 ps |
| CPU time | 62.09 seconds |
| Started | Sep 09 10:30:30 PM UTC 24 |
| Finished | Sep 09 10:31:34 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105411558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_j tag_errors.1105411558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.960471114 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 485992326 ps |
| CPU time | 14.98 seconds |
| Started | Sep 09 10:30:27 PM UTC 24 |
| Finished | Sep 09 10:30:43 PM UTC 24 |
| Peak memory | 235904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960471114 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl _jtag_prog_failure.960471114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.348173515 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 476925185 ps |
| CPU time | 13.72 seconds |
| Started | Sep 09 10:30:26 PM UTC 24 |
| Finished | Sep 09 10:30:41 PM UTC 24 |
| Peak memory | 229568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348173515 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_s moke.348173515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.1090573561 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 18367060014 ps |
| CPU time | 149.06 seconds |
| Started | Sep 09 10:30:27 PM UTC 24 |
| Finished | Sep 09 10:32:59 PM UTC 24 |
| Peak memory | 311984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090573561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct rl_jtag_state_failure.1090573561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.4091025037 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 641505706 ps |
| CPU time | 11.79 seconds |
| Started | Sep 09 10:30:27 PM UTC 24 |
| Finished | Sep 09 10:30:40 PM UTC 24 |
| Peak memory | 260504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091025037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc _ctrl_jtag_state_post_trans.4091025037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.3259477221 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 79060673 ps |
| CPU time | 2.63 seconds |
| Started | Sep 09 10:30:26 PM UTC 24 |
| Finished | Sep 09 10:30:29 PM UTC 24 |
| Peak memory | 232280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259477221 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3259477221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.2150790750 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 846995473 ps |
| CPU time | 10.87 seconds |
| Started | Sep 09 10:30:30 PM UTC 24 |
| Finished | Sep 09 10:30:43 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150790750 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2150790750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.1016174113 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2489637963 ps |
| CPU time | 19.67 seconds |
| Started | Sep 09 10:30:34 PM UTC 24 |
| Finished | Sep 09 10:30:55 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016174113 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_to ken_digest.1016174113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.2264645186 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1042183960 ps |
| CPU time | 13.73 seconds |
| Started | Sep 09 10:30:32 PM UTC 24 |
| Finished | Sep 09 10:30:47 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264645186 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token _mux.2264645186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.2509870387 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 3619870937 ps |
| CPU time | 19.41 seconds |
| Started | Sep 09 10:30:26 PM UTC 24 |
| Finished | Sep 09 10:30:46 PM UTC 24 |
| Peak memory | 232260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509870387 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2509870387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.3244018946 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 88943741 ps |
| CPU time | 3.5 seconds |
| Started | Sep 09 10:30:22 PM UTC 24 |
| Finished | Sep 09 10:30:26 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244018946 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3244018946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.3525349998 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 428454108 ps |
| CPU time | 30.86 seconds |
| Started | Sep 09 10:30:23 PM UTC 24 |
| Finished | Sep 09 10:30:55 PM UTC 24 |
| Peak memory | 262556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525349998 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3525349998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.136558687 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 133629674 ps |
| CPU time | 4.31 seconds |
| Started | Sep 09 10:30:24 PM UTC 24 |
| Finished | Sep 09 10:30:29 PM UTC 24 |
| Peak memory | 234652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136558687 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.136558687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.424490932 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 236256339229 ps |
| CPU time | 582.8 seconds |
| Started | Sep 09 10:30:36 PM UTC 24 |
| Finished | Sep 09 10:40:26 PM UTC 24 |
| Peak memory | 274916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=424490932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 19.lc_ctrl_stress_all.424490932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.4105434539 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4028943025 ps |
| CPU time | 36.71 seconds |
| Started | Sep 09 10:30:36 PM UTC 24 |
| Finished | Sep 09 10:31:14 PM UTC 24 |
| Peak memory | 273232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105434539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.4105434539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1027142992 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 31160296 ps |
| CPU time | 1.35 seconds |
| Started | Sep 09 10:30:22 PM UTC 24 |
| Finished | Sep 09 10:30:24 PM UTC 24 |
| Peak memory | 228708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027142992 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19 .lc_ctrl_volatile_unlock_smoke.1027142992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.2604472643 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 27247280 ps |
| CPU time | 1.5 seconds |
| Started | Sep 09 10:24:57 PM UTC 24 |
| Finished | Sep 09 10:24:59 PM UTC 24 |
| Peak memory | 218524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604472643 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2604472643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.548131157 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 17851088 ps |
| CPU time | 1.13 seconds |
| Started | Sep 09 10:24:39 PM UTC 24 |
| Finished | Sep 09 10:24:41 PM UTC 24 |
| Peak memory | 219036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548131157 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.548131157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.2312092766 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 501224957 ps |
| CPU time | 19.43 seconds |
| Started | Sep 09 10:24:37 PM UTC 24 |
| Finished | Sep 09 10:24:58 PM UTC 24 |
| Peak memory | 232280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312092766 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2312092766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.2914894977 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 442819415 ps |
| CPU time | 13.6 seconds |
| Started | Sep 09 10:24:45 PM UTC 24 |
| Finished | Sep 09 10:25:00 PM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914894977 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2914894977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.2910578219 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9393040219 ps |
| CPU time | 46.8 seconds |
| Started | Sep 09 10:24:45 PM UTC 24 |
| Finished | Sep 09 10:25:34 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910578219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jt ag_errors.2910578219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.1847026652 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 709525341 ps |
| CPU time | 21.97 seconds |
| Started | Sep 09 10:24:48 PM UTC 24 |
| Finished | Sep 09 10:25:11 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847026652 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_prior ity.1847026652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.447881717 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 342104362 ps |
| CPU time | 4.11 seconds |
| Started | Sep 09 10:24:44 PM UTC 24 |
| Finished | Sep 09 10:24:49 PM UTC 24 |
| Peak memory | 233924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447881717 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_prog_failure.447881717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1810471625 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 16599288017 ps |
| CPU time | 24.35 seconds |
| Started | Sep 09 10:24:48 PM UTC 24 |
| Finished | Sep 09 10:25:13 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810471625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ ctrl_jtag_regwen_during_op.1810471625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.3462101559 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 901664964 ps |
| CPU time | 9.5 seconds |
| Started | Sep 09 10:24:40 PM UTC 24 |
| Finished | Sep 09 10:24:50 PM UTC 24 |
| Peak memory | 229496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462101559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_s moke.3462101559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.2295177625 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1504889631 ps |
| CPU time | 87.09 seconds |
| Started | Sep 09 10:24:42 PM UTC 24 |
| Finished | Sep 09 10:26:11 PM UTC 24 |
| Peak memory | 289228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295177625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr l_jtag_state_failure.2295177625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.2427032183 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1841105844 ps |
| CPU time | 28.6 seconds |
| Started | Sep 09 10:24:42 PM UTC 24 |
| Finished | Sep 09 10:25:12 PM UTC 24 |
| Peak memory | 237932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427032183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ ctrl_jtag_state_post_trans.2427032183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.3947753403 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 62969101 ps |
| CPU time | 3.7 seconds |
| Started | Sep 09 10:24:36 PM UTC 24 |
| Finished | Sep 09 10:24:41 PM UTC 24 |
| Peak memory | 235972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947753403 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3947753403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.2795554663 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1079820061 ps |
| CPU time | 14.3 seconds |
| Started | Sep 09 10:24:39 PM UTC 24 |
| Finished | Sep 09 10:24:54 PM UTC 24 |
| Peak memory | 225796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795554663 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2795554663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.2000563516 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 280240433 ps |
| CPU time | 52.81 seconds |
| Started | Sep 09 10:24:55 PM UTC 24 |
| Finished | Sep 09 10:25:50 PM UTC 24 |
| Peak memory | 298296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000563516 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2000563516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.2745174041 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1352607656 ps |
| CPU time | 20.28 seconds |
| Started | Sep 09 10:24:48 PM UTC 24 |
| Finished | Sep 09 10:25:09 PM UTC 24 |
| Peak memory | 237676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745174041 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2745174041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.2975884297 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 523606262 ps |
| CPU time | 16.54 seconds |
| Started | Sep 09 10:24:50 PM UTC 24 |
| Finished | Sep 09 10:25:08 PM UTC 24 |
| Peak memory | 231764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975884297 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_tok en_digest.2975884297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.4056648778 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 892085672 ps |
| CPU time | 10.4 seconds |
| Started | Sep 09 10:24:49 PM UTC 24 |
| Finished | Sep 09 10:25:00 PM UTC 24 |
| Peak memory | 232088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056648778 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_ mux.4056648778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.2709790337 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 764809077 ps |
| CPU time | 7.97 seconds |
| Started | Sep 09 10:24:37 PM UTC 24 |
| Finished | Sep 09 10:24:47 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709790337 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2709790337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.3811689506 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 51699209 ps |
| CPU time | 3.92 seconds |
| Started | Sep 09 10:24:32 PM UTC 24 |
| Finished | Sep 09 10:24:37 PM UTC 24 |
| Peak memory | 225872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811689506 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3811689506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.2558874234 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1424572845 ps |
| CPU time | 34.96 seconds |
| Started | Sep 09 10:24:34 PM UTC 24 |
| Finished | Sep 09 10:25:11 PM UTC 24 |
| Peak memory | 262584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558874234 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2558874234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.2694107017 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 95302892 ps |
| CPU time | 8.89 seconds |
| Started | Sep 09 10:24:36 PM UTC 24 |
| Finished | Sep 09 10:24:47 PM UTC 24 |
| Peak memory | 262512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694107017 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2694107017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.308311187 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 182303247234 ps |
| CPU time | 566.11 seconds |
| Started | Sep 09 10:24:50 PM UTC 24 |
| Finished | Sep 09 10:34:23 PM UTC 24 |
| Peak memory | 295636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=308311187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 2.lc_ctrl_stress_all.308311187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.2971549111 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 16514255 ps |
| CPU time | 1.5 seconds |
| Started | Sep 09 10:30:50 PM UTC 24 |
| Finished | Sep 09 10:30:52 PM UTC 24 |
| Peak memory | 218588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971549111 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2971549111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_errors.2426105797 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 859940561 ps |
| CPU time | 18.13 seconds |
| Started | Sep 09 10:30:43 PM UTC 24 |
| Finished | Sep 09 10:31:03 PM UTC 24 |
| Peak memory | 237592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426105797 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2426105797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.3952470818 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 120833391 ps |
| CPU time | 4.18 seconds |
| Started | Sep 09 10:30:45 PM UTC 24 |
| Finished | Sep 09 10:30:50 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952470818 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3952470818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.2212184727 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 881788868 ps |
| CPU time | 3.88 seconds |
| Started | Sep 09 10:30:43 PM UTC 24 |
| Finished | Sep 09 10:30:48 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212184727 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2212184727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.2949730417 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 203445788 ps |
| CPU time | 13.8 seconds |
| Started | Sep 09 10:30:45 PM UTC 24 |
| Finished | Sep 09 10:31:00 PM UTC 24 |
| Peak memory | 237280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949730417 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2949730417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.1792333230 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 241129880 ps |
| CPU time | 11.71 seconds |
| Started | Sep 09 10:30:46 PM UTC 24 |
| Finished | Sep 09 10:30:59 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792333230 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_to ken_digest.1792333230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.1506580164 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 3896716616 ps |
| CPU time | 14.71 seconds |
| Started | Sep 09 10:30:45 PM UTC 24 |
| Finished | Sep 09 10:31:01 PM UTC 24 |
| Peak memory | 231932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506580164 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token _mux.1506580164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.2001124884 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 624346447 ps |
| CPU time | 14.25 seconds |
| Started | Sep 09 10:30:43 PM UTC 24 |
| Finished | Sep 09 10:30:59 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001124884 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2001124884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.321712865 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 32617589 ps |
| CPU time | 3.33 seconds |
| Started | Sep 09 10:30:38 PM UTC 24 |
| Finished | Sep 09 10:30:42 PM UTC 24 |
| Peak memory | 225468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321712865 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.321712865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.2286144203 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 585031484 ps |
| CPU time | 23.16 seconds |
| Started | Sep 09 10:30:41 PM UTC 24 |
| Finished | Sep 09 10:31:05 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286144203 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2286144203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.1465688958 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 93384888 ps |
| CPU time | 7.5 seconds |
| Started | Sep 09 10:30:42 PM UTC 24 |
| Finished | Sep 09 10:30:51 PM UTC 24 |
| Peak memory | 260696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465688958 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1465688958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.1741706650 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 5265849198 ps |
| CPU time | 106.02 seconds |
| Started | Sep 09 10:30:47 PM UTC 24 |
| Finished | Sep 09 10:32:36 PM UTC 24 |
| Peak memory | 283384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1741706650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 20.lc_ctrl_stress_all.1741706650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1654622433 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 17850438 ps |
| CPU time | 1.12 seconds |
| Started | Sep 09 10:30:41 PM UTC 24 |
| Finished | Sep 09 10:30:43 PM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654622433 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20 .lc_ctrl_volatile_unlock_smoke.1654622433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.2852351093 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 56676033 ps |
| CPU time | 1.25 seconds |
| Started | Sep 09 10:31:01 PM UTC 24 |
| Finished | Sep 09 10:31:03 PM UTC 24 |
| Peak memory | 218588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852351093 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2852351093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_errors.1615208796 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 296346406 ps |
| CPU time | 11.7 seconds |
| Started | Sep 09 10:30:56 PM UTC 24 |
| Finished | Sep 09 10:31:08 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615208796 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1615208796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.1859646739 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 37800787 ps |
| CPU time | 1.74 seconds |
| Started | Sep 09 10:30:57 PM UTC 24 |
| Finished | Sep 09 10:31:00 PM UTC 24 |
| Peak memory | 227924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859646739 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1859646739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.115561684 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 286058091 ps |
| CPU time | 2.57 seconds |
| Started | Sep 09 10:30:54 PM UTC 24 |
| Finished | Sep 09 10:30:58 PM UTC 24 |
| Peak memory | 234008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115561684 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.115561684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.2732576352 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1278290773 ps |
| CPU time | 15.52 seconds |
| Started | Sep 09 10:30:57 PM UTC 24 |
| Finished | Sep 09 10:31:14 PM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732576352 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2732576352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.922500262 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1782591232 ps |
| CPU time | 20.41 seconds |
| Started | Sep 09 10:30:59 PM UTC 24 |
| Finished | Sep 09 10:31:21 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922500262 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_tok en_digest.922500262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.3244717896 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 924235673 ps |
| CPU time | 10.25 seconds |
| Started | Sep 09 10:30:59 PM UTC 24 |
| Finished | Sep 09 10:31:11 PM UTC 24 |
| Peak memory | 232196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244717896 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token _mux.3244717896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.3066366470 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 3177491512 ps |
| CPU time | 9.65 seconds |
| Started | Sep 09 10:30:56 PM UTC 24 |
| Finished | Sep 09 10:31:06 PM UTC 24 |
| Peak memory | 232004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066366470 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3066366470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.963621291 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 211133190 ps |
| CPU time | 3.52 seconds |
| Started | Sep 09 10:30:50 PM UTC 24 |
| Finished | Sep 09 10:30:54 PM UTC 24 |
| Peak memory | 235704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963621291 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.963621291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.865333919 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 265383970 ps |
| CPU time | 28.49 seconds |
| Started | Sep 09 10:30:51 PM UTC 24 |
| Finished | Sep 09 10:31:21 PM UTC 24 |
| Peak memory | 258744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865333919 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.865333919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.119123194 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1297449269 ps |
| CPU time | 10.45 seconds |
| Started | Sep 09 10:30:53 PM UTC 24 |
| Finished | Sep 09 10:31:05 PM UTC 24 |
| Peak memory | 262740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119123194 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.119123194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.1633336814 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 16212059223 ps |
| CPU time | 195.42 seconds |
| Started | Sep 09 10:31:01 PM UTC 24 |
| Finished | Sep 09 10:34:19 PM UTC 24 |
| Peak memory | 295412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1633336814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 21.lc_ctrl_stress_all.1633336814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.3560819720 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 4672473001 ps |
| CPU time | 55.52 seconds |
| Started | Sep 09 10:31:01 PM UTC 24 |
| Finished | Sep 09 10:31:58 PM UTC 24 |
| Peak memory | 262712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560819720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.3560819720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2727266478 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 95259797 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 10:30:51 PM UTC 24 |
| Finished | Sep 09 10:30:53 PM UTC 24 |
| Peak memory | 218288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727266478 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21 .lc_ctrl_volatile_unlock_smoke.2727266478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.6219516 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 54034432 ps |
| CPU time | 2.01 seconds |
| Started | Sep 09 10:31:15 PM UTC 24 |
| Finished | Sep 09 10:31:18 PM UTC 24 |
| Peak memory | 218468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6219516 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.6219516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_errors.803242654 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 416751832 ps |
| CPU time | 14.8 seconds |
| Started | Sep 09 10:31:06 PM UTC 24 |
| Finished | Sep 09 10:31:22 PM UTC 24 |
| Peak memory | 231832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803242654 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.803242654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.1279411381 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1032884107 ps |
| CPU time | 8.21 seconds |
| Started | Sep 09 10:31:07 PM UTC 24 |
| Finished | Sep 09 10:31:16 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279411381 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1279411381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.2709088641 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 48800859 ps |
| CPU time | 2.84 seconds |
| Started | Sep 09 10:31:06 PM UTC 24 |
| Finished | Sep 09 10:31:10 PM UTC 24 |
| Peak memory | 231784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709088641 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2709088641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.1621982658 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1326643727 ps |
| CPU time | 13.13 seconds |
| Started | Sep 09 10:31:08 PM UTC 24 |
| Finished | Sep 09 10:31:23 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621982658 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1621982658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.1739163135 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 884306951 ps |
| CPU time | 19 seconds |
| Started | Sep 09 10:31:10 PM UTC 24 |
| Finished | Sep 09 10:31:30 PM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739163135 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_to ken_digest.1739163135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.3481721843 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1331025378 ps |
| CPU time | 11.98 seconds |
| Started | Sep 09 10:31:08 PM UTC 24 |
| Finished | Sep 09 10:31:22 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481721843 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token _mux.3481721843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.865242004 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 1136820462 ps |
| CPU time | 15.72 seconds |
| Started | Sep 09 10:31:07 PM UTC 24 |
| Finished | Sep 09 10:31:24 PM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865242004 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.865242004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.1790953898 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 55418773 ps |
| CPU time | 3.83 seconds |
| Started | Sep 09 10:31:01 PM UTC 24 |
| Finished | Sep 09 10:31:06 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790953898 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1790953898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.3547436657 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 867707389 ps |
| CPU time | 24.44 seconds |
| Started | Sep 09 10:31:03 PM UTC 24 |
| Finished | Sep 09 10:31:29 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547436657 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3547436657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.3949803215 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 146843856 ps |
| CPU time | 8.86 seconds |
| Started | Sep 09 10:31:04 PM UTC 24 |
| Finished | Sep 09 10:31:14 PM UTC 24 |
| Peak memory | 260452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949803215 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3949803215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.2070825227 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 11674045134 ps |
| CPU time | 66.12 seconds |
| Started | Sep 09 10:31:11 PM UTC 24 |
| Finished | Sep 09 10:32:19 PM UTC 24 |
| Peak memory | 262568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2070825227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 22.lc_ctrl_stress_all.2070825227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1049106555 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1363821281 ps |
| CPU time | 43.88 seconds |
| Started | Sep 09 10:31:12 PM UTC 24 |
| Finished | Sep 09 10:31:57 PM UTC 24 |
| Peak memory | 283252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049106555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.1049106555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.637374115 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 74893487 ps |
| CPU time | 1.68 seconds |
| Started | Sep 09 10:31:02 PM UTC 24 |
| Finished | Sep 09 10:31:05 PM UTC 24 |
| Peak memory | 228692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637374115 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22. lc_ctrl_volatile_unlock_smoke.637374115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.4111625059 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 14342048 ps |
| CPU time | 1.26 seconds |
| Started | Sep 09 10:31:25 PM UTC 24 |
| Finished | Sep 09 10:31:28 PM UTC 24 |
| Peak memory | 217316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111625059 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.4111625059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.2947556610 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 578329830 ps |
| CPU time | 15.19 seconds |
| Started | Sep 09 10:31:20 PM UTC 24 |
| Finished | Sep 09 10:31:36 PM UTC 24 |
| Peak memory | 232084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947556610 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2947556610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.1353601588 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 643772997 ps |
| CPU time | 10.89 seconds |
| Started | Sep 09 10:31:23 PM UTC 24 |
| Finished | Sep 09 10:31:35 PM UTC 24 |
| Peak memory | 229580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353601588 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1353601588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.3700528343 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 97896232 ps |
| CPU time | 2.45 seconds |
| Started | Sep 09 10:31:20 PM UTC 24 |
| Finished | Sep 09 10:31:23 PM UTC 24 |
| Peak memory | 233928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700528343 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3700528343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.1131459106 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 278279046 ps |
| CPU time | 12.07 seconds |
| Started | Sep 09 10:31:23 PM UTC 24 |
| Finished | Sep 09 10:31:36 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131459106 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1131459106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.111473132 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 914318465 ps |
| CPU time | 13.04 seconds |
| Started | Sep 09 10:31:23 PM UTC 24 |
| Finished | Sep 09 10:31:37 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111473132 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_tok en_digest.111473132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.1307018819 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 4000136017 ps |
| CPU time | 14.67 seconds |
| Started | Sep 09 10:31:23 PM UTC 24 |
| Finished | Sep 09 10:31:38 PM UTC 24 |
| Peak memory | 237644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307018819 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token _mux.1307018819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.25974473 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 829556420 ps |
| CPU time | 10.74 seconds |
| Started | Sep 09 10:31:21 PM UTC 24 |
| Finished | Sep 09 10:31:33 PM UTC 24 |
| Peak memory | 232012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25974473 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.25974473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.1046989847 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 71813346 ps |
| CPU time | 3.83 seconds |
| Started | Sep 09 10:31:15 PM UTC 24 |
| Finished | Sep 09 10:31:20 PM UTC 24 |
| Peak memory | 225532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046989847 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1046989847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.359126612 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1045075998 ps |
| CPU time | 22.44 seconds |
| Started | Sep 09 10:31:17 PM UTC 24 |
| Finished | Sep 09 10:31:41 PM UTC 24 |
| Peak memory | 262836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359126612 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.359126612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.198431901 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 176226329 ps |
| CPU time | 9.04 seconds |
| Started | Sep 09 10:31:18 PM UTC 24 |
| Finished | Sep 09 10:31:29 PM UTC 24 |
| Peak memory | 262752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198431901 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.198431901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.3420271369 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 566363974 ps |
| CPU time | 38.46 seconds |
| Started | Sep 09 10:31:24 PM UTC 24 |
| Finished | Sep 09 10:32:04 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3420271369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 23.lc_ctrl_stress_all.3420271369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3123334173 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 41369117 ps |
| CPU time | 1.21 seconds |
| Started | Sep 09 10:31:15 PM UTC 24 |
| Finished | Sep 09 10:31:17 PM UTC 24 |
| Peak memory | 218556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123334173 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23 .lc_ctrl_volatile_unlock_smoke.3123334173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.1348381007 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 56166671 ps |
| CPU time | 1.47 seconds |
| Started | Sep 09 10:31:39 PM UTC 24 |
| Finished | Sep 09 10:31:41 PM UTC 24 |
| Peak memory | 218644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348381007 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1348381007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.2394868329 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 724323163 ps |
| CPU time | 26.28 seconds |
| Started | Sep 09 10:31:33 PM UTC 24 |
| Finished | Sep 09 10:32:01 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394868329 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2394868329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.379836466 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 197703776 ps |
| CPU time | 1.68 seconds |
| Started | Sep 09 10:31:36 PM UTC 24 |
| Finished | Sep 09 10:31:38 PM UTC 24 |
| Peak memory | 229396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379836466 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.379836466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.745828491 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 48152285 ps |
| CPU time | 3.46 seconds |
| Started | Sep 09 10:31:32 PM UTC 24 |
| Finished | Sep 09 10:31:37 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745828491 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.745828491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.2399892830 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 685658682 ps |
| CPU time | 26.86 seconds |
| Started | Sep 09 10:31:36 PM UTC 24 |
| Finished | Sep 09 10:32:04 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399892830 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2399892830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.648138465 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1295222289 ps |
| CPU time | 14.2 seconds |
| Started | Sep 09 10:31:37 PM UTC 24 |
| Finished | Sep 09 10:31:52 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648138465 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_tok en_digest.648138465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.1468544860 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 605270855 ps |
| CPU time | 9.49 seconds |
| Started | Sep 09 10:31:36 PM UTC 24 |
| Finished | Sep 09 10:31:46 PM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468544860 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token _mux.1468544860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.3074615390 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 658298347 ps |
| CPU time | 9.45 seconds |
| Started | Sep 09 10:31:33 PM UTC 24 |
| Finished | Sep 09 10:31:44 PM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074615390 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3074615390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.3323181235 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 187611351 ps |
| CPU time | 5.14 seconds |
| Started | Sep 09 10:31:28 PM UTC 24 |
| Finished | Sep 09 10:31:35 PM UTC 24 |
| Peak memory | 225548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323181235 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3323181235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.4249074606 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 228576406 ps |
| CPU time | 32.21 seconds |
| Started | Sep 09 10:31:30 PM UTC 24 |
| Finished | Sep 09 10:32:03 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249074606 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4249074606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.1240350211 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 251029464 ps |
| CPU time | 8.87 seconds |
| Started | Sep 09 10:31:31 PM UTC 24 |
| Finished | Sep 09 10:31:41 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240350211 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1240350211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.745560262 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 2447337464 ps |
| CPU time | 75.62 seconds |
| Started | Sep 09 10:31:37 PM UTC 24 |
| Finished | Sep 09 10:32:54 PM UTC 24 |
| Peak memory | 291308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=745560262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 24.lc_ctrl_stress_all.745560262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.4275248970 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2745054989 ps |
| CPU time | 94.8 seconds |
| Started | Sep 09 10:31:39 PM UTC 24 |
| Finished | Sep 09 10:33:15 PM UTC 24 |
| Peak memory | 281160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275248970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.4275248970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3751113403 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 27539665 ps |
| CPU time | 1.53 seconds |
| Started | Sep 09 10:31:30 PM UTC 24 |
| Finished | Sep 09 10:31:32 PM UTC 24 |
| Peak memory | 222380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751113403 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24 .lc_ctrl_volatile_unlock_smoke.3751113403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.1062860668 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 22361785 ps |
| CPU time | 1.2 seconds |
| Started | Sep 09 10:31:48 PM UTC 24 |
| Finished | Sep 09 10:31:50 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062860668 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1062860668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_errors.1819487211 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1152167708 ps |
| CPU time | 9.5 seconds |
| Started | Sep 09 10:31:42 PM UTC 24 |
| Finished | Sep 09 10:31:52 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819487211 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1819487211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.1170527922 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 300207039 ps |
| CPU time | 2.12 seconds |
| Started | Sep 09 10:31:43 PM UTC 24 |
| Finished | Sep 09 10:31:46 PM UTC 24 |
| Peak memory | 229308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170527922 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1170527922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.3838513375 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 75787054 ps |
| CPU time | 3.7 seconds |
| Started | Sep 09 10:31:42 PM UTC 24 |
| Finished | Sep 09 10:31:46 PM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838513375 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3838513375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.3746688535 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1197146617 ps |
| CPU time | 14.09 seconds |
| Started | Sep 09 10:31:44 PM UTC 24 |
| Finished | Sep 09 10:31:59 PM UTC 24 |
| Peak memory | 237920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746688535 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3746688535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.3759496426 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 743985327 ps |
| CPU time | 9.41 seconds |
| Started | Sep 09 10:31:45 PM UTC 24 |
| Finished | Sep 09 10:31:56 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759496426 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_to ken_digest.3759496426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.558961914 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 237834209 ps |
| CPU time | 9.5 seconds |
| Started | Sep 09 10:31:45 PM UTC 24 |
| Finished | Sep 09 10:31:56 PM UTC 24 |
| Peak memory | 237596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558961914 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_ mux.558961914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.2736575586 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 4730145863 ps |
| CPU time | 9.95 seconds |
| Started | Sep 09 10:31:43 PM UTC 24 |
| Finished | Sep 09 10:31:54 PM UTC 24 |
| Peak memory | 231704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736575586 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2736575586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.426855369 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 50102521 ps |
| CPU time | 2.02 seconds |
| Started | Sep 09 10:31:39 PM UTC 24 |
| Finished | Sep 09 10:31:42 PM UTC 24 |
| Peak memory | 223744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426855369 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.426855369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.3302871503 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 793429638 ps |
| CPU time | 23.48 seconds |
| Started | Sep 09 10:31:40 PM UTC 24 |
| Finished | Sep 09 10:32:05 PM UTC 24 |
| Peak memory | 262832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302871503 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3302871503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.2417221373 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 67313784 ps |
| CPU time | 9.77 seconds |
| Started | Sep 09 10:31:40 PM UTC 24 |
| Finished | Sep 09 10:31:51 PM UTC 24 |
| Peak memory | 262428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417221373 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2417221373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.2883663626 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 54481423924 ps |
| CPU time | 504.86 seconds |
| Started | Sep 09 10:31:46 PM UTC 24 |
| Finished | Sep 09 10:40:17 PM UTC 24 |
| Peak memory | 289192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2883663626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 25.lc_ctrl_stress_all.2883663626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2134781684 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 20246949 ps |
| CPU time | 1.45 seconds |
| Started | Sep 09 10:31:40 PM UTC 24 |
| Finished | Sep 09 10:31:43 PM UTC 24 |
| Peak memory | 222380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134781684 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25 .lc_ctrl_volatile_unlock_smoke.2134781684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.2177150667 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 42498679 ps |
| CPU time | 1.4 seconds |
| Started | Sep 09 10:31:57 PM UTC 24 |
| Finished | Sep 09 10:31:59 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177150667 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2177150667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_errors.4069836906 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 3078667255 ps |
| CPU time | 17.07 seconds |
| Started | Sep 09 10:31:53 PM UTC 24 |
| Finished | Sep 09 10:32:11 PM UTC 24 |
| Peak memory | 232276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069836906 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.4069836906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.2059895924 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 4102815604 ps |
| CPU time | 28.08 seconds |
| Started | Sep 09 10:31:54 PM UTC 24 |
| Finished | Sep 09 10:32:24 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059895924 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2059895924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.45351174 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 47107996 ps |
| CPU time | 3.08 seconds |
| Started | Sep 09 10:31:53 PM UTC 24 |
| Finished | Sep 09 10:31:57 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45351174 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.45351174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2117359257 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 1797101336 ps |
| CPU time | 16.59 seconds |
| Started | Sep 09 10:31:54 PM UTC 24 |
| Finished | Sep 09 10:32:12 PM UTC 24 |
| Peak memory | 237664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117359257 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2117359257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.299075676 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 2222237191 ps |
| CPU time | 21.71 seconds |
| Started | Sep 09 10:31:56 PM UTC 24 |
| Finished | Sep 09 10:32:19 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299075676 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_tok en_digest.299075676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.3437069389 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 207495162 ps |
| CPU time | 11.45 seconds |
| Started | Sep 09 10:31:56 PM UTC 24 |
| Finished | Sep 09 10:32:08 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437069389 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token _mux.3437069389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.999412047 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 983580937 ps |
| CPU time | 12.75 seconds |
| Started | Sep 09 10:31:54 PM UTC 24 |
| Finished | Sep 09 10:32:08 PM UTC 24 |
| Peak memory | 232020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999412047 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.999412047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.1878468538 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 211079694 ps |
| CPU time | 4.93 seconds |
| Started | Sep 09 10:31:50 PM UTC 24 |
| Finished | Sep 09 10:31:56 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878468538 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1878468538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.1776623151 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1355131670 ps |
| CPU time | 21.32 seconds |
| Started | Sep 09 10:31:51 PM UTC 24 |
| Finished | Sep 09 10:32:14 PM UTC 24 |
| Peak memory | 258488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776623151 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1776623151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.1768447002 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 462656641 ps |
| CPU time | 12.15 seconds |
| Started | Sep 09 10:31:53 PM UTC 24 |
| Finished | Sep 09 10:32:06 PM UTC 24 |
| Peak memory | 260444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768447002 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1768447002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.2170065493 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1459785828 ps |
| CPU time | 60.93 seconds |
| Started | Sep 09 10:31:56 PM UTC 24 |
| Finished | Sep 09 10:32:58 PM UTC 24 |
| Peak memory | 262504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2170065493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 26.lc_ctrl_stress_all.2170065493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2618526229 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 39958988 ps |
| CPU time | 1.25 seconds |
| Started | Sep 09 10:31:51 PM UTC 24 |
| Finished | Sep 09 10:31:53 PM UTC 24 |
| Peak memory | 218232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618526229 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26 .lc_ctrl_volatile_unlock_smoke.2618526229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.3594881385 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 17609983 ps |
| CPU time | 1.39 seconds |
| Started | Sep 09 10:32:05 PM UTC 24 |
| Finished | Sep 09 10:32:08 PM UTC 24 |
| Peak memory | 217432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594881385 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3594881385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.3785727202 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 165807566 ps |
| CPU time | 4.24 seconds |
| Started | Sep 09 10:32:02 PM UTC 24 |
| Finished | Sep 09 10:32:08 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785727202 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3785727202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.2655088728 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 44286017 ps |
| CPU time | 1.97 seconds |
| Started | Sep 09 10:32:00 PM UTC 24 |
| Finished | Sep 09 10:32:03 PM UTC 24 |
| Peak memory | 231968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655088728 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2655088728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.3186029940 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 635400269 ps |
| CPU time | 20.85 seconds |
| Started | Sep 09 10:32:04 PM UTC 24 |
| Finished | Sep 09 10:32:26 PM UTC 24 |
| Peak memory | 232208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186029940 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3186029940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.1818858132 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 408707817 ps |
| CPU time | 18.34 seconds |
| Started | Sep 09 10:32:05 PM UTC 24 |
| Finished | Sep 09 10:32:25 PM UTC 24 |
| Peak memory | 237848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818858132 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_to ken_digest.1818858132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.2454972703 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 518935285 ps |
| CPU time | 16.32 seconds |
| Started | Sep 09 10:32:04 PM UTC 24 |
| Finished | Sep 09 10:32:21 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454972703 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token _mux.2454972703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.694594951 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1269515689 ps |
| CPU time | 11.7 seconds |
| Started | Sep 09 10:32:01 PM UTC 24 |
| Finished | Sep 09 10:32:14 PM UTC 24 |
| Peak memory | 237596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694594951 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.694594951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.786053599 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 59602844 ps |
| CPU time | 5.44 seconds |
| Started | Sep 09 10:31:57 PM UTC 24 |
| Finished | Sep 09 10:32:04 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786053599 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.786053599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.2809403763 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 385566749 ps |
| CPU time | 34.34 seconds |
| Started | Sep 09 10:31:58 PM UTC 24 |
| Finished | Sep 09 10:32:34 PM UTC 24 |
| Peak memory | 262504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809403763 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2809403763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.95543436 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 132073427 ps |
| CPU time | 12.41 seconds |
| Started | Sep 09 10:32:00 PM UTC 24 |
| Finished | Sep 09 10:32:13 PM UTC 24 |
| Peak memory | 262712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95543436 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.95543436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.1108169621 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 82112062594 ps |
| CPU time | 162.85 seconds |
| Started | Sep 09 10:32:05 PM UTC 24 |
| Finished | Sep 09 10:34:51 PM UTC 24 |
| Peak memory | 237680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1108169621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 27.lc_ctrl_stress_all.1108169621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1576217244 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 12220906 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 10:31:58 PM UTC 24 |
| Finished | Sep 09 10:32:01 PM UTC 24 |
| Peak memory | 219332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576217244 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27 .lc_ctrl_volatile_unlock_smoke.1576217244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.364609483 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 88841382 ps |
| CPU time | 1.35 seconds |
| Started | Sep 09 10:32:15 PM UTC 24 |
| Finished | Sep 09 10:32:17 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364609483 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.364609483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.3222099569 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1798693020 ps |
| CPU time | 9.55 seconds |
| Started | Sep 09 10:32:11 PM UTC 24 |
| Finished | Sep 09 10:32:22 PM UTC 24 |
| Peak memory | 229504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222099569 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3222099569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.2495001995 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 29237917 ps |
| CPU time | 2.75 seconds |
| Started | Sep 09 10:32:09 PM UTC 24 |
| Finished | Sep 09 10:32:13 PM UTC 24 |
| Peak memory | 232344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495001995 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2495001995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.4065071950 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 988993328 ps |
| CPU time | 8.17 seconds |
| Started | Sep 09 10:32:13 PM UTC 24 |
| Finished | Sep 09 10:32:22 PM UTC 24 |
| Peak memory | 237936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065071950 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.4065071950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.3273623299 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 258986387 ps |
| CPU time | 10.31 seconds |
| Started | Sep 09 10:32:13 PM UTC 24 |
| Finished | Sep 09 10:32:25 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273623299 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_to ken_digest.3273623299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.696010857 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 1408561190 ps |
| CPU time | 10.59 seconds |
| Started | Sep 09 10:32:13 PM UTC 24 |
| Finished | Sep 09 10:32:25 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696010857 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_ mux.696010857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.4144202839 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 840056821 ps |
| CPU time | 11.1 seconds |
| Started | Sep 09 10:32:10 PM UTC 24 |
| Finished | Sep 09 10:32:22 PM UTC 24 |
| Peak memory | 237652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144202839 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.4144202839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.1393699737 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 22365660 ps |
| CPU time | 2.78 seconds |
| Started | Sep 09 10:32:07 PM UTC 24 |
| Finished | Sep 09 10:32:10 PM UTC 24 |
| Peak memory | 225476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393699737 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1393699737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.4021265107 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 299622871 ps |
| CPU time | 32.16 seconds |
| Started | Sep 09 10:32:09 PM UTC 24 |
| Finished | Sep 09 10:32:42 PM UTC 24 |
| Peak memory | 262832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021265107 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.4021265107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.260117958 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 80579758 ps |
| CPU time | 7.84 seconds |
| Started | Sep 09 10:32:09 PM UTC 24 |
| Finished | Sep 09 10:32:18 PM UTC 24 |
| Peak memory | 260440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260117958 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.260117958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.2533920816 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 45371798805 ps |
| CPU time | 235.56 seconds |
| Started | Sep 09 10:32:14 PM UTC 24 |
| Finished | Sep 09 10:36:14 PM UTC 24 |
| Peak memory | 330204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2533920816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 28.lc_ctrl_stress_all.2533920816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1350821701 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 12166082935 ps |
| CPU time | 99.29 seconds |
| Started | Sep 09 10:32:15 PM UTC 24 |
| Finished | Sep 09 10:33:56 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350821701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1350821701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2151068108 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 17241042 ps |
| CPU time | 1.34 seconds |
| Started | Sep 09 10:32:07 PM UTC 24 |
| Finished | Sep 09 10:32:09 PM UTC 24 |
| Peak memory | 228504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151068108 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28 .lc_ctrl_volatile_unlock_smoke.2151068108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.2182307000 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 61604052 ps |
| CPU time | 1.36 seconds |
| Started | Sep 09 10:32:24 PM UTC 24 |
| Finished | Sep 09 10:32:27 PM UTC 24 |
| Peak memory | 218644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182307000 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2182307000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_errors.1320417016 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 801060975 ps |
| CPU time | 23.53 seconds |
| Started | Sep 09 10:32:19 PM UTC 24 |
| Finished | Sep 09 10:32:44 PM UTC 24 |
| Peak memory | 229972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320417016 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1320417016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.4098750916 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 317683236 ps |
| CPU time | 8.37 seconds |
| Started | Sep 09 10:32:21 PM UTC 24 |
| Finished | Sep 09 10:32:30 PM UTC 24 |
| Peak memory | 229540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098750916 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.4098750916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.1949230674 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 80969873 ps |
| CPU time | 4.9 seconds |
| Started | Sep 09 10:32:18 PM UTC 24 |
| Finished | Sep 09 10:32:24 PM UTC 24 |
| Peak memory | 235976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949230674 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1949230674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.840237155 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1315841371 ps |
| CPU time | 17.17 seconds |
| Started | Sep 09 10:32:21 PM UTC 24 |
| Finished | Sep 09 10:32:39 PM UTC 24 |
| Peak memory | 231944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840237155 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.840237155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.1483212664 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 3667014758 ps |
| CPU time | 23.29 seconds |
| Started | Sep 09 10:32:23 PM UTC 24 |
| Finished | Sep 09 10:32:48 PM UTC 24 |
| Peak memory | 237576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483212664 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_to ken_digest.1483212664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.2522765076 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 4280529245 ps |
| CPU time | 9.63 seconds |
| Started | Sep 09 10:32:22 PM UTC 24 |
| Finished | Sep 09 10:32:33 PM UTC 24 |
| Peak memory | 237644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522765076 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token _mux.2522765076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.1526184664 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1834741369 ps |
| CPU time | 14.03 seconds |
| Started | Sep 09 10:32:19 PM UTC 24 |
| Finished | Sep 09 10:32:35 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526184664 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1526184664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.751568819 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 44636370 ps |
| CPU time | 3.76 seconds |
| Started | Sep 09 10:32:15 PM UTC 24 |
| Finished | Sep 09 10:32:19 PM UTC 24 |
| Peak memory | 225464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751568819 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.751568819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.2874305402 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 975216193 ps |
| CPU time | 30.3 seconds |
| Started | Sep 09 10:32:16 PM UTC 24 |
| Finished | Sep 09 10:32:48 PM UTC 24 |
| Peak memory | 262576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874305402 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2874305402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.3635761643 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 172673072 ps |
| CPU time | 9.21 seconds |
| Started | Sep 09 10:32:18 PM UTC 24 |
| Finished | Sep 09 10:32:29 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635761643 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3635761643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.3256476566 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 17177546689 ps |
| CPU time | 141.56 seconds |
| Started | Sep 09 10:32:23 PM UTC 24 |
| Finished | Sep 09 10:34:47 PM UTC 24 |
| Peak memory | 291692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3256476566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 29.lc_ctrl_stress_all.3256476566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1727029628 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 4438336414 ps |
| CPU time | 50.37 seconds |
| Started | Sep 09 10:32:23 PM UTC 24 |
| Finished | Sep 09 10:33:15 PM UTC 24 |
| Peak memory | 261008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727029628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.1727029628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1895047438 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 68312541 ps |
| CPU time | 1.28 seconds |
| Started | Sep 09 10:32:15 PM UTC 24 |
| Finished | Sep 09 10:32:17 PM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895047438 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29 .lc_ctrl_volatile_unlock_smoke.1895047438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.3681952628 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 63899407 ps |
| CPU time | 1.39 seconds |
| Started | Sep 09 10:25:19 PM UTC 24 |
| Finished | Sep 09 10:25:22 PM UTC 24 |
| Peak memory | 218712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681952628 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3681952628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.3551119943 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 300317282 ps |
| CPU time | 12.03 seconds |
| Started | Sep 09 10:25:02 PM UTC 24 |
| Finished | Sep 09 10:25:15 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551119943 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3551119943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.1817537462 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 663396140 ps |
| CPU time | 7.38 seconds |
| Started | Sep 09 10:25:11 PM UTC 24 |
| Finished | Sep 09 10:25:20 PM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817537462 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1817537462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.11143597 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 8327200809 ps |
| CPU time | 49.64 seconds |
| Started | Sep 09 10:25:11 PM UTC 24 |
| Finished | Sep 09 10:26:02 PM UTC 24 |
| Peak memory | 231948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11143597 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag _errors.11143597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2930910611 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2012238758 ps |
| CPU time | 17.02 seconds |
| Started | Sep 09 10:25:12 PM UTC 24 |
| Finished | Sep 09 10:25:31 PM UTC 24 |
| Peak memory | 229608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930910611 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_prior ity.2930910611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.574550533 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 899718030 ps |
| CPU time | 7.75 seconds |
| Started | Sep 09 10:25:10 PM UTC 24 |
| Finished | Sep 09 10:25:19 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574550533 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_prog_failure.574550533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2918388688 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3256351825 ps |
| CPU time | 19.94 seconds |
| Started | Sep 09 10:25:14 PM UTC 24 |
| Finished | Sep 09 10:25:35 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918388688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ ctrl_jtag_regwen_during_op.2918388688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.163760124 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 692401481 ps |
| CPU time | 5.41 seconds |
| Started | Sep 09 10:25:07 PM UTC 24 |
| Finished | Sep 09 10:25:13 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163760124 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_sm oke.163760124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.2544195787 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 5179070644 ps |
| CPU time | 70.38 seconds |
| Started | Sep 09 10:25:09 PM UTC 24 |
| Finished | Sep 09 10:26:21 PM UTC 24 |
| Peak memory | 295592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544195787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr l_jtag_state_failure.2544195787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.2580715762 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 993979953 ps |
| CPU time | 17.77 seconds |
| Started | Sep 09 10:25:09 PM UTC 24 |
| Finished | Sep 09 10:25:28 PM UTC 24 |
| Peak memory | 262512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580715762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ ctrl_jtag_state_post_trans.2580715762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.3923117821 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 303720722 ps |
| CPU time | 4.07 seconds |
| Started | Sep 09 10:25:01 PM UTC 24 |
| Finished | Sep 09 10:25:06 PM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923117821 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3923117821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.443113756 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 921952889 ps |
| CPU time | 14.66 seconds |
| Started | Sep 09 10:25:05 PM UTC 24 |
| Finished | Sep 09 10:25:21 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443113756 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.443113756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.635026307 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 117843020 ps |
| CPU time | 26.75 seconds |
| Started | Sep 09 10:25:18 PM UTC 24 |
| Finished | Sep 09 10:25:46 PM UTC 24 |
| Peak memory | 287776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635026307 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.635026307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.3848056804 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1399455946 ps |
| CPU time | 24.64 seconds |
| Started | Sep 09 10:25:14 PM UTC 24 |
| Finished | Sep 09 10:25:39 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848056804 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3848056804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.3288153327 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 4286309318 ps |
| CPU time | 14.32 seconds |
| Started | Sep 09 10:25:15 PM UTC 24 |
| Finished | Sep 09 10:25:30 PM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288153327 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_tok en_digest.3288153327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.1486733429 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1015941216 ps |
| CPU time | 9.25 seconds |
| Started | Sep 09 10:25:14 PM UTC 24 |
| Finished | Sep 09 10:25:24 PM UTC 24 |
| Peak memory | 237596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486733429 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_ mux.1486733429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.91362301 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 228027924 ps |
| CPU time | 13.85 seconds |
| Started | Sep 09 10:25:03 PM UTC 24 |
| Finished | Sep 09 10:25:18 PM UTC 24 |
| Peak memory | 232012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91362301 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.91362301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.2134274711 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 786445832 ps |
| CPU time | 5.02 seconds |
| Started | Sep 09 10:24:57 PM UTC 24 |
| Finished | Sep 09 10:25:03 PM UTC 24 |
| Peak memory | 225652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134274711 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2134274711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.3795319551 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 812655918 ps |
| CPU time | 19.17 seconds |
| Started | Sep 09 10:25:00 PM UTC 24 |
| Finished | Sep 09 10:25:20 PM UTC 24 |
| Peak memory | 262512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795319551 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3795319551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3138317519 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 56700304 ps |
| CPU time | 10.05 seconds |
| Started | Sep 09 10:25:01 PM UTC 24 |
| Finished | Sep 09 10:25:12 PM UTC 24 |
| Peak memory | 262504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138317519 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3138317519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.530008621 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 28668647333 ps |
| CPU time | 274.73 seconds |
| Started | Sep 09 10:25:16 PM UTC 24 |
| Finished | Sep 09 10:29:54 PM UTC 24 |
| Peak memory | 281392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=530008621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 3.lc_ctrl_stress_all.530008621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1508902645 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 16728223 ps |
| CPU time | 1.34 seconds |
| Started | Sep 09 10:24:59 PM UTC 24 |
| Finished | Sep 09 10:25:01 PM UTC 24 |
| Peak memory | 228512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508902645 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3. lc_ctrl_volatile_unlock_smoke.1508902645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.2594338632 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 262716507 ps |
| CPU time | 2.14 seconds |
| Started | Sep 09 10:32:36 PM UTC 24 |
| Finished | Sep 09 10:32:39 PM UTC 24 |
| Peak memory | 219092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594338632 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2594338632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.2922509908 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1123782556 ps |
| CPU time | 5.77 seconds |
| Started | Sep 09 10:32:30 PM UTC 24 |
| Finished | Sep 09 10:32:37 PM UTC 24 |
| Peak memory | 229528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922509908 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2922509908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.20284599 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1463399508 ps |
| CPU time | 5.22 seconds |
| Started | Sep 09 10:32:26 PM UTC 24 |
| Finished | Sep 09 10:32:33 PM UTC 24 |
| Peak memory | 236244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20284599 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.20284599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.3773605738 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1163323642 ps |
| CPU time | 12.92 seconds |
| Started | Sep 09 10:32:30 PM UTC 24 |
| Finished | Sep 09 10:32:44 PM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773605738 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3773605738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.3582226483 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 172267853 ps |
| CPU time | 8.8 seconds |
| Started | Sep 09 10:32:31 PM UTC 24 |
| Finished | Sep 09 10:32:41 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582226483 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_to ken_digest.3582226483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.1250677162 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 826571156 ps |
| CPU time | 14.3 seconds |
| Started | Sep 09 10:32:31 PM UTC 24 |
| Finished | Sep 09 10:32:47 PM UTC 24 |
| Peak memory | 237580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250677162 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token _mux.1250677162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.1885792138 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 1064889119 ps |
| CPU time | 11.16 seconds |
| Started | Sep 09 10:32:28 PM UTC 24 |
| Finished | Sep 09 10:32:40 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885792138 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1885792138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.37637340 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 132754800 ps |
| CPU time | 3.18 seconds |
| Started | Sep 09 10:32:26 PM UTC 24 |
| Finished | Sep 09 10:32:30 PM UTC 24 |
| Peak memory | 229564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37637340 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.37637340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.3545526105 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1152676434 ps |
| CPU time | 23.46 seconds |
| Started | Sep 09 10:32:26 PM UTC 24 |
| Finished | Sep 09 10:32:51 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545526105 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3545526105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.210140054 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 66042029 ps |
| CPU time | 11.35 seconds |
| Started | Sep 09 10:32:26 PM UTC 24 |
| Finished | Sep 09 10:32:39 PM UTC 24 |
| Peak memory | 262892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210140054 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.210140054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.1294535956 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 56166969577 ps |
| CPU time | 269.96 seconds |
| Started | Sep 09 10:32:33 PM UTC 24 |
| Finished | Sep 09 10:37:07 PM UTC 24 |
| Peak memory | 295392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1294535956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 30.lc_ctrl_stress_all.1294535956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2168455922 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 44849264 ps |
| CPU time | 1.3 seconds |
| Started | Sep 09 10:32:26 PM UTC 24 |
| Finished | Sep 09 10:32:28 PM UTC 24 |
| Peak memory | 218232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168455922 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30 .lc_ctrl_volatile_unlock_smoke.2168455922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.131378915 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 13986168 ps |
| CPU time | 1.41 seconds |
| Started | Sep 09 10:32:42 PM UTC 24 |
| Finished | Sep 09 10:32:44 PM UTC 24 |
| Peak memory | 218588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131378915 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.131378915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.944132716 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 985982735 ps |
| CPU time | 17.87 seconds |
| Started | Sep 09 10:32:38 PM UTC 24 |
| Finished | Sep 09 10:32:58 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944132716 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.944132716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.1107725598 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 2121209538 ps |
| CPU time | 11.96 seconds |
| Started | Sep 09 10:32:40 PM UTC 24 |
| Finished | Sep 09 10:32:53 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107725598 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1107725598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.1881856931 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 100614669 ps |
| CPU time | 4.88 seconds |
| Started | Sep 09 10:32:38 PM UTC 24 |
| Finished | Sep 09 10:32:44 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881856931 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1881856931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.1403056911 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 364675570 ps |
| CPU time | 20.34 seconds |
| Started | Sep 09 10:32:40 PM UTC 24 |
| Finished | Sep 09 10:33:01 PM UTC 24 |
| Peak memory | 237664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403056911 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1403056911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.248743034 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 661314269 ps |
| CPU time | 19.22 seconds |
| Started | Sep 09 10:32:40 PM UTC 24 |
| Finished | Sep 09 10:33:00 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248743034 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_tok en_digest.248743034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.668160161 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 1652945476 ps |
| CPU time | 15.83 seconds |
| Started | Sep 09 10:32:40 PM UTC 24 |
| Finished | Sep 09 10:32:57 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668160161 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_ mux.668160161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.3995594172 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 306098861 ps |
| CPU time | 12.48 seconds |
| Started | Sep 09 10:32:40 PM UTC 24 |
| Finished | Sep 09 10:32:53 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995594172 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3995594172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.928799682 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 12650477 ps |
| CPU time | 1.68 seconds |
| Started | Sep 09 10:32:36 PM UTC 24 |
| Finished | Sep 09 10:32:39 PM UTC 24 |
| Peak memory | 222324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928799682 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.928799682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.3658827844 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1285662187 ps |
| CPU time | 30.19 seconds |
| Started | Sep 09 10:32:37 PM UTC 24 |
| Finished | Sep 09 10:33:08 PM UTC 24 |
| Peak memory | 260452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658827844 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3658827844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.247262304 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 73814584 ps |
| CPU time | 10.38 seconds |
| Started | Sep 09 10:32:38 PM UTC 24 |
| Finished | Sep 09 10:32:50 PM UTC 24 |
| Peak memory | 256428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247262304 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.247262304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.2737550051 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 28658866157 ps |
| CPU time | 124.11 seconds |
| Started | Sep 09 10:32:42 PM UTC 24 |
| Finished | Sep 09 10:34:48 PM UTC 24 |
| Peak memory | 262640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2737550051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 31.lc_ctrl_stress_all.2737550051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.552683406 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 16414889 ps |
| CPU time | 1.45 seconds |
| Started | Sep 09 10:32:36 PM UTC 24 |
| Finished | Sep 09 10:32:38 PM UTC 24 |
| Peak memory | 228712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552683406 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31. lc_ctrl_volatile_unlock_smoke.552683406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.2573066494 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 73041825 ps |
| CPU time | 1.53 seconds |
| Started | Sep 09 10:32:52 PM UTC 24 |
| Finished | Sep 09 10:32:54 PM UTC 24 |
| Peak memory | 218644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573066494 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2573066494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_errors.3408248529 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 260417269 ps |
| CPU time | 12.1 seconds |
| Started | Sep 09 10:32:46 PM UTC 24 |
| Finished | Sep 09 10:32:59 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408248529 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3408248529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.218180744 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 11969703689 ps |
| CPU time | 11.37 seconds |
| Started | Sep 09 10:32:48 PM UTC 24 |
| Finished | Sep 09 10:33:01 PM UTC 24 |
| Peak memory | 229680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218180744 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.218180744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.2488964984 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 305719596 ps |
| CPU time | 3.89 seconds |
| Started | Sep 09 10:32:46 PM UTC 24 |
| Finished | Sep 09 10:32:51 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488964984 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2488964984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.4074877723 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 414302174 ps |
| CPU time | 14.17 seconds |
| Started | Sep 09 10:32:48 PM UTC 24 |
| Finished | Sep 09 10:33:03 PM UTC 24 |
| Peak memory | 237984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074877723 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.4074877723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.4076624861 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 831325974 ps |
| CPU time | 8.73 seconds |
| Started | Sep 09 10:32:49 PM UTC 24 |
| Finished | Sep 09 10:32:59 PM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076624861 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_to ken_digest.4076624861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.1159800945 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 1467470694 ps |
| CPU time | 18.14 seconds |
| Started | Sep 09 10:32:49 PM UTC 24 |
| Finished | Sep 09 10:33:09 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159800945 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token _mux.1159800945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.3885866925 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 228204366 ps |
| CPU time | 8.78 seconds |
| Started | Sep 09 10:32:47 PM UTC 24 |
| Finished | Sep 09 10:32:57 PM UTC 24 |
| Peak memory | 236452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885866925 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3885866925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.4272615323 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 37680239 ps |
| CPU time | 2.48 seconds |
| Started | Sep 09 10:32:44 PM UTC 24 |
| Finished | Sep 09 10:32:48 PM UTC 24 |
| Peak memory | 225532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272615323 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.4272615323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.3286927820 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 310506733 ps |
| CPU time | 25.13 seconds |
| Started | Sep 09 10:32:46 PM UTC 24 |
| Finished | Sep 09 10:33:12 PM UTC 24 |
| Peak memory | 262704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286927820 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3286927820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.1010979110 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 57299059 ps |
| CPU time | 8.92 seconds |
| Started | Sep 09 10:32:46 PM UTC 24 |
| Finished | Sep 09 10:32:56 PM UTC 24 |
| Peak memory | 262576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010979110 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1010979110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.2493899799 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 15714443277 ps |
| CPU time | 121.64 seconds |
| Started | Sep 09 10:32:51 PM UTC 24 |
| Finished | Sep 09 10:34:54 PM UTC 24 |
| Peak memory | 262644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2493899799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 32.lc_ctrl_stress_all.2493899799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2369052771 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4156687509 ps |
| CPU time | 86.37 seconds |
| Started | Sep 09 10:32:52 PM UTC 24 |
| Finished | Sep 09 10:34:20 PM UTC 24 |
| Peak memory | 283208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369052771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.2369052771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3453058079 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 13995630 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 10:32:44 PM UTC 24 |
| Finished | Sep 09 10:32:46 PM UTC 24 |
| Peak memory | 218496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453058079 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32 .lc_ctrl_volatile_unlock_smoke.3453058079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.2188535 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 44799178 ps |
| CPU time | 1.13 seconds |
| Started | Sep 09 10:33:00 PM UTC 24 |
| Finished | Sep 09 10:33:02 PM UTC 24 |
| Peak memory | 217376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188535 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2188535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_errors.3443781032 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 400318414 ps |
| CPU time | 18.06 seconds |
| Started | Sep 09 10:32:57 PM UTC 24 |
| Finished | Sep 09 10:33:16 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443781032 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3443781032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.3466753337 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 378181941 ps |
| CPU time | 8.72 seconds |
| Started | Sep 09 10:32:57 PM UTC 24 |
| Finished | Sep 09 10:33:07 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466753337 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3466753337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.4280599063 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 72738080 ps |
| CPU time | 4.14 seconds |
| Started | Sep 09 10:32:56 PM UTC 24 |
| Finished | Sep 09 10:33:01 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280599063 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.4280599063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.3122221433 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 2806779504 ps |
| CPU time | 13.39 seconds |
| Started | Sep 09 10:32:58 PM UTC 24 |
| Finished | Sep 09 10:33:13 PM UTC 24 |
| Peak memory | 237364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122221433 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3122221433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.3411804380 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 355465868 ps |
| CPU time | 14.77 seconds |
| Started | Sep 09 10:32:59 PM UTC 24 |
| Finished | Sep 09 10:33:14 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411804380 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_to ken_digest.3411804380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.2540805447 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 246515127 ps |
| CPU time | 9.8 seconds |
| Started | Sep 09 10:32:58 PM UTC 24 |
| Finished | Sep 09 10:33:09 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540805447 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token _mux.2540805447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.3576058866 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 202548557 ps |
| CPU time | 9.54 seconds |
| Started | Sep 09 10:32:57 PM UTC 24 |
| Finished | Sep 09 10:33:07 PM UTC 24 |
| Peak memory | 236136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576058866 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3576058866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.1572312204 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 28176629 ps |
| CPU time | 1.42 seconds |
| Started | Sep 09 10:32:53 PM UTC 24 |
| Finished | Sep 09 10:32:55 PM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572312204 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1572312204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.3116790145 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 169629593 ps |
| CPU time | 19.49 seconds |
| Started | Sep 09 10:32:54 PM UTC 24 |
| Finished | Sep 09 10:33:15 PM UTC 24 |
| Peak memory | 258404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116790145 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3116790145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.3046338434 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 70904492 ps |
| CPU time | 14.03 seconds |
| Started | Sep 09 10:32:56 PM UTC 24 |
| Finished | Sep 09 10:33:11 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046338434 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3046338434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.1309169568 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 60021421520 ps |
| CPU time | 143.19 seconds |
| Started | Sep 09 10:32:59 PM UTC 24 |
| Finished | Sep 09 10:35:24 PM UTC 24 |
| Peak memory | 271108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1309169568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 33.lc_ctrl_stress_all.1309169568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3813486795 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 33917267 ps |
| CPU time | 1.33 seconds |
| Started | Sep 09 10:32:54 PM UTC 24 |
| Finished | Sep 09 10:32:57 PM UTC 24 |
| Peak memory | 222336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813486795 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33 .lc_ctrl_volatile_unlock_smoke.3813486795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.257470240 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 51648528 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 10:33:10 PM UTC 24 |
| Finished | Sep 09 10:33:12 PM UTC 24 |
| Peak memory | 217376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257470240 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.257470240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_errors.2665297899 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 990300015 ps |
| CPU time | 13.73 seconds |
| Started | Sep 09 10:33:03 PM UTC 24 |
| Finished | Sep 09 10:33:18 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665297899 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2665297899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.3430702547 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 1308467007 ps |
| CPU time | 5.13 seconds |
| Started | Sep 09 10:33:04 PM UTC 24 |
| Finished | Sep 09 10:33:10 PM UTC 24 |
| Peak memory | 229540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430702547 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3430702547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.869757447 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 121133316 ps |
| CPU time | 2.19 seconds |
| Started | Sep 09 10:33:02 PM UTC 24 |
| Finished | Sep 09 10:33:05 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869757447 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.869757447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.1811435670 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 550183397 ps |
| CPU time | 11.54 seconds |
| Started | Sep 09 10:33:04 PM UTC 24 |
| Finished | Sep 09 10:33:17 PM UTC 24 |
| Peak memory | 237588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811435670 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1811435670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.1710578370 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 2748975824 ps |
| CPU time | 15.9 seconds |
| Started | Sep 09 10:33:06 PM UTC 24 |
| Finished | Sep 09 10:33:23 PM UTC 24 |
| Peak memory | 237656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710578370 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_to ken_digest.1710578370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.582244635 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 774685102 ps |
| CPU time | 8.84 seconds |
| Started | Sep 09 10:33:05 PM UTC 24 |
| Finished | Sep 09 10:33:15 PM UTC 24 |
| Peak memory | 237600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582244635 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_ mux.582244635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.1407981339 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 187763055 ps |
| CPU time | 10.65 seconds |
| Started | Sep 09 10:33:03 PM UTC 24 |
| Finished | Sep 09 10:33:15 PM UTC 24 |
| Peak memory | 237580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407981339 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1407981339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.2986904378 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 30020560 ps |
| CPU time | 2.72 seconds |
| Started | Sep 09 10:33:00 PM UTC 24 |
| Finished | Sep 09 10:33:04 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986904378 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2986904378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.1635337832 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 253811132 ps |
| CPU time | 30.44 seconds |
| Started | Sep 09 10:33:02 PM UTC 24 |
| Finished | Sep 09 10:33:33 PM UTC 24 |
| Peak memory | 260452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635337832 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1635337832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.634365599 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 87271096 ps |
| CPU time | 7.53 seconds |
| Started | Sep 09 10:33:02 PM UTC 24 |
| Finished | Sep 09 10:33:10 PM UTC 24 |
| Peak memory | 262496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634365599 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.634365599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.1648444505 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 5552855461 ps |
| CPU time | 51.72 seconds |
| Started | Sep 09 10:33:08 PM UTC 24 |
| Finished | Sep 09 10:34:01 PM UTC 24 |
| Peak memory | 237656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1648444505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 34.lc_ctrl_stress_all.1648444505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3945866884 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 46528852 ps |
| CPU time | 1.4 seconds |
| Started | Sep 09 10:33:00 PM UTC 24 |
| Finished | Sep 09 10:33:03 PM UTC 24 |
| Peak memory | 222380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945866884 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34 .lc_ctrl_volatile_unlock_smoke.3945866884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.3027067439 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 62990978 ps |
| CPU time | 1.42 seconds |
| Started | Sep 09 10:33:16 PM UTC 24 |
| Finished | Sep 09 10:33:19 PM UTC 24 |
| Peak memory | 218588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027067439 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3027067439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_errors.1551248508 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 870930740 ps |
| CPU time | 15.14 seconds |
| Started | Sep 09 10:33:13 PM UTC 24 |
| Finished | Sep 09 10:33:30 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551248508 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1551248508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.2816014760 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 416854003 ps |
| CPU time | 12.96 seconds |
| Started | Sep 09 10:33:13 PM UTC 24 |
| Finished | Sep 09 10:33:28 PM UTC 24 |
| Peak memory | 229468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816014760 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2816014760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.1768052192 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 26201227 ps |
| CPU time | 2.09 seconds |
| Started | Sep 09 10:33:12 PM UTC 24 |
| Finished | Sep 09 10:33:15 PM UTC 24 |
| Peak memory | 234004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768052192 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1768052192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.3667382429 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 616683488 ps |
| CPU time | 13.36 seconds |
| Started | Sep 09 10:33:13 PM UTC 24 |
| Finished | Sep 09 10:33:28 PM UTC 24 |
| Peak memory | 237664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667382429 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.3667382429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.3337327944 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 378214271 ps |
| CPU time | 14.02 seconds |
| Started | Sep 09 10:33:15 PM UTC 24 |
| Finished | Sep 09 10:33:30 PM UTC 24 |
| Peak memory | 237516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337327944 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_to ken_digest.3337327944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.2915813703 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 980434464 ps |
| CPU time | 11.58 seconds |
| Started | Sep 09 10:33:15 PM UTC 24 |
| Finished | Sep 09 10:33:27 PM UTC 24 |
| Peak memory | 237652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915813703 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token _mux.2915813703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.1688001352 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 707609228 ps |
| CPU time | 7.21 seconds |
| Started | Sep 09 10:33:13 PM UTC 24 |
| Finished | Sep 09 10:33:22 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688001352 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1688001352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.264538967 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 17106483 ps |
| CPU time | 1.75 seconds |
| Started | Sep 09 10:33:10 PM UTC 24 |
| Finished | Sep 09 10:33:13 PM UTC 24 |
| Peak memory | 222320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264538967 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.264538967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.934730553 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 266873835 ps |
| CPU time | 21.98 seconds |
| Started | Sep 09 10:33:12 PM UTC 24 |
| Finished | Sep 09 10:33:35 PM UTC 24 |
| Peak memory | 262436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934730553 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.934730553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.1666160446 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 158447586 ps |
| CPU time | 8.41 seconds |
| Started | Sep 09 10:33:12 PM UTC 24 |
| Finished | Sep 09 10:33:21 PM UTC 24 |
| Peak memory | 260668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666160446 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1666160446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.1249803345 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 22979962076 ps |
| CPU time | 199.66 seconds |
| Started | Sep 09 10:33:16 PM UTC 24 |
| Finished | Sep 09 10:36:39 PM UTC 24 |
| Peak memory | 295664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1249803345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 35.lc_ctrl_stress_all.1249803345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.955383580 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 37335168 ps |
| CPU time | 1.16 seconds |
| Started | Sep 09 10:33:10 PM UTC 24 |
| Finished | Sep 09 10:33:13 PM UTC 24 |
| Peak memory | 228532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955383580 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35. lc_ctrl_volatile_unlock_smoke.955383580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.1884825914 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 22748237 ps |
| CPU time | 1.63 seconds |
| Started | Sep 09 10:33:23 PM UTC 24 |
| Finished | Sep 09 10:33:26 PM UTC 24 |
| Peak memory | 218588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884825914 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1884825914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_errors.631416602 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 4348637897 ps |
| CPU time | 11.8 seconds |
| Started | Sep 09 10:33:19 PM UTC 24 |
| Finished | Sep 09 10:33:31 PM UTC 24 |
| Peak memory | 232268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631416602 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.631416602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.67478519 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 328494417 ps |
| CPU time | 7.04 seconds |
| Started | Sep 09 10:33:19 PM UTC 24 |
| Finished | Sep 09 10:33:27 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67478519 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.67478519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.4234775484 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 134794717 ps |
| CPU time | 3 seconds |
| Started | Sep 09 10:33:18 PM UTC 24 |
| Finished | Sep 09 10:33:22 PM UTC 24 |
| Peak memory | 234000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234775484 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.4234775484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.3943941298 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 301291820 ps |
| CPU time | 8.44 seconds |
| Started | Sep 09 10:33:20 PM UTC 24 |
| Finished | Sep 09 10:33:29 PM UTC 24 |
| Peak memory | 238072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943941298 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3943941298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.3875196041 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 986897424 ps |
| CPU time | 8.29 seconds |
| Started | Sep 09 10:33:22 PM UTC 24 |
| Finished | Sep 09 10:33:31 PM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875196041 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_to ken_digest.3875196041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.179065084 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3980277361 ps |
| CPU time | 9.89 seconds |
| Started | Sep 09 10:33:20 PM UTC 24 |
| Finished | Sep 09 10:33:31 PM UTC 24 |
| Peak memory | 237996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179065084 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_ mux.179065084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.1236035267 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 170387871 ps |
| CPU time | 10.64 seconds |
| Started | Sep 09 10:33:19 PM UTC 24 |
| Finished | Sep 09 10:33:30 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236035267 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1236035267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.3405065037 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 168601106 ps |
| CPU time | 4.3 seconds |
| Started | Sep 09 10:33:16 PM UTC 24 |
| Finished | Sep 09 10:33:22 PM UTC 24 |
| Peak memory | 225532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405065037 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3405065037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.584403376 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 809925242 ps |
| CPU time | 27.82 seconds |
| Started | Sep 09 10:33:17 PM UTC 24 |
| Finished | Sep 09 10:33:46 PM UTC 24 |
| Peak memory | 262524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584403376 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.584403376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.1552774640 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 607107910 ps |
| CPU time | 11.07 seconds |
| Started | Sep 09 10:33:18 PM UTC 24 |
| Finished | Sep 09 10:33:31 PM UTC 24 |
| Peak memory | 262492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552774640 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1552774640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.1732322998 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 7607677279 ps |
| CPU time | 192.4 seconds |
| Started | Sep 09 10:33:22 PM UTC 24 |
| Finished | Sep 09 10:36:38 PM UTC 24 |
| Peak memory | 262892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1732322998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 36.lc_ctrl_stress_all.1732322998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.837311601 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30029705 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 10:33:16 PM UTC 24 |
| Finished | Sep 09 10:33:19 PM UTC 24 |
| Peak memory | 218532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837311601 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36. lc_ctrl_volatile_unlock_smoke.837311601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.4074576013 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 18129717 ps |
| CPU time | 1.47 seconds |
| Started | Sep 09 10:33:31 PM UTC 24 |
| Finished | Sep 09 10:33:34 PM UTC 24 |
| Peak memory | 218540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074576013 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.4074576013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.229802472 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 281951091 ps |
| CPU time | 12.85 seconds |
| Started | Sep 09 10:33:28 PM UTC 24 |
| Finished | Sep 09 10:33:42 PM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229802472 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.229802472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.2842709643 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 3297217251 ps |
| CPU time | 9.03 seconds |
| Started | Sep 09 10:33:30 PM UTC 24 |
| Finished | Sep 09 10:33:40 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842709643 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2842709643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.3376031222 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 59955680 ps |
| CPU time | 2.27 seconds |
| Started | Sep 09 10:33:28 PM UTC 24 |
| Finished | Sep 09 10:33:31 PM UTC 24 |
| Peak memory | 232012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376031222 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3376031222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.2848469638 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 326895371 ps |
| CPU time | 12.89 seconds |
| Started | Sep 09 10:33:30 PM UTC 24 |
| Finished | Sep 09 10:33:44 PM UTC 24 |
| Peak memory | 237788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848469638 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2848469638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.2044326560 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1959470895 ps |
| CPU time | 11.05 seconds |
| Started | Sep 09 10:33:31 PM UTC 24 |
| Finished | Sep 09 10:33:43 PM UTC 24 |
| Peak memory | 237512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044326560 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_to ken_digest.2044326560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.2004786732 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 318244366 ps |
| CPU time | 15.07 seconds |
| Started | Sep 09 10:33:31 PM UTC 24 |
| Finished | Sep 09 10:33:48 PM UTC 24 |
| Peak memory | 232272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004786732 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token _mux.2004786732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.705192138 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1690387420 ps |
| CPU time | 10.94 seconds |
| Started | Sep 09 10:33:28 PM UTC 24 |
| Finished | Sep 09 10:33:40 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705192138 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.705192138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.3615031118 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 498934913 ps |
| CPU time | 5.78 seconds |
| Started | Sep 09 10:33:23 PM UTC 24 |
| Finished | Sep 09 10:33:30 PM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615031118 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3615031118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.123570103 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 314314323 ps |
| CPU time | 32.38 seconds |
| Started | Sep 09 10:33:27 PM UTC 24 |
| Finished | Sep 09 10:34:01 PM UTC 24 |
| Peak memory | 262644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123570103 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.123570103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.3052561201 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 331603558 ps |
| CPU time | 4.79 seconds |
| Started | Sep 09 10:33:27 PM UTC 24 |
| Finished | Sep 09 10:33:33 PM UTC 24 |
| Peak memory | 236300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052561201 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3052561201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.4279654933 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 7464559730 ps |
| CPU time | 201.29 seconds |
| Started | Sep 09 10:33:31 PM UTC 24 |
| Finished | Sep 09 10:36:56 PM UTC 24 |
| Peak memory | 295728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4279654933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 37.lc_ctrl_stress_all.4279654933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2228142524 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 397936285 ps |
| CPU time | 19.41 seconds |
| Started | Sep 09 10:33:31 PM UTC 24 |
| Finished | Sep 09 10:33:52 PM UTC 24 |
| Peak memory | 238420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228142524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.2228142524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.538275017 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 25592958 ps |
| CPU time | 1.19 seconds |
| Started | Sep 09 10:33:26 PM UTC 24 |
| Finished | Sep 09 10:33:28 PM UTC 24 |
| Peak memory | 218712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538275017 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37. lc_ctrl_volatile_unlock_smoke.538275017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.457942062 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 22759203 ps |
| CPU time | 1.35 seconds |
| Started | Sep 09 10:33:41 PM UTC 24 |
| Finished | Sep 09 10:33:44 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457942062 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.457942062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.1941592754 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 843272398 ps |
| CPU time | 17.09 seconds |
| Started | Sep 09 10:33:34 PM UTC 24 |
| Finished | Sep 09 10:33:53 PM UTC 24 |
| Peak memory | 237668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941592754 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1941592754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.3459105425 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3308929678 ps |
| CPU time | 13.59 seconds |
| Started | Sep 09 10:33:34 PM UTC 24 |
| Finished | Sep 09 10:33:49 PM UTC 24 |
| Peak memory | 229612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459105425 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3459105425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.2015611463 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 226804375 ps |
| CPU time | 4.77 seconds |
| Started | Sep 09 10:33:33 PM UTC 24 |
| Finished | Sep 09 10:33:39 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015611463 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2015611463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.2862054089 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 302428570 ps |
| CPU time | 18.28 seconds |
| Started | Sep 09 10:33:36 PM UTC 24 |
| Finished | Sep 09 10:33:55 PM UTC 24 |
| Peak memory | 237724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862054089 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2862054089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.3214003313 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 622626933 ps |
| CPU time | 12.87 seconds |
| Started | Sep 09 10:33:37 PM UTC 24 |
| Finished | Sep 09 10:33:51 PM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214003313 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_to ken_digest.3214003313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.1258702604 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 1265047835 ps |
| CPU time | 11.45 seconds |
| Started | Sep 09 10:33:36 PM UTC 24 |
| Finished | Sep 09 10:33:48 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258702604 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token _mux.1258702604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.1061559269 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 344505741 ps |
| CPU time | 14.4 seconds |
| Started | Sep 09 10:33:34 PM UTC 24 |
| Finished | Sep 09 10:33:50 PM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061559269 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1061559269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.4246868394 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 191979761 ps |
| CPU time | 5.21 seconds |
| Started | Sep 09 10:33:31 PM UTC 24 |
| Finished | Sep 09 10:33:38 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246868394 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.4246868394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.2505377334 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 211140890 ps |
| CPU time | 20.31 seconds |
| Started | Sep 09 10:33:33 PM UTC 24 |
| Finished | Sep 09 10:33:54 PM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505377334 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2505377334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.2589630057 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 148144279 ps |
| CPU time | 12.96 seconds |
| Started | Sep 09 10:33:33 PM UTC 24 |
| Finished | Sep 09 10:33:47 PM UTC 24 |
| Peak memory | 260524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589630057 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2589630057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.2102983018 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 1456940652 ps |
| CPU time | 70.26 seconds |
| Started | Sep 09 10:33:39 PM UTC 24 |
| Finished | Sep 09 10:34:52 PM UTC 24 |
| Peak memory | 280940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2102983018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 38.lc_ctrl_stress_all.2102983018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.3821223167 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 14248508038 ps |
| CPU time | 129.42 seconds |
| Started | Sep 09 10:33:40 PM UTC 24 |
| Finished | Sep 09 10:35:52 PM UTC 24 |
| Peak memory | 281124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821223167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.3821223167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.2597654217 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 27534243 ps |
| CPU time | 1.47 seconds |
| Started | Sep 09 10:33:51 PM UTC 24 |
| Finished | Sep 09 10:33:54 PM UTC 24 |
| Peak memory | 218524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597654217 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2597654217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_errors.2085100474 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 1251395953 ps |
| CPU time | 15.49 seconds |
| Started | Sep 09 10:33:45 PM UTC 24 |
| Finished | Sep 09 10:34:02 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085100474 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2085100474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.471510307 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 530214918 ps |
| CPU time | 4.18 seconds |
| Started | Sep 09 10:33:47 PM UTC 24 |
| Finished | Sep 09 10:33:53 PM UTC 24 |
| Peak memory | 229664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471510307 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.471510307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.12167556 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 78681360 ps |
| CPU time | 3.15 seconds |
| Started | Sep 09 10:33:45 PM UTC 24 |
| Finished | Sep 09 10:33:50 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12167556 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.12167556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1779442757 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 357504458 ps |
| CPU time | 13.28 seconds |
| Started | Sep 09 10:33:47 PM UTC 24 |
| Finished | Sep 09 10:34:02 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779442757 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1779442757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.2900477622 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 238481413 ps |
| CPU time | 13.24 seconds |
| Started | Sep 09 10:33:49 PM UTC 24 |
| Finished | Sep 09 10:34:03 PM UTC 24 |
| Peak memory | 231668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900477622 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_to ken_digest.2900477622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.781842206 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3304970882 ps |
| CPU time | 17.08 seconds |
| Started | Sep 09 10:33:49 PM UTC 24 |
| Finished | Sep 09 10:34:07 PM UTC 24 |
| Peak memory | 237812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781842206 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_ mux.781842206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.3409283828 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 417212644 ps |
| CPU time | 13.63 seconds |
| Started | Sep 09 10:33:46 PM UTC 24 |
| Finished | Sep 09 10:34:01 PM UTC 24 |
| Peak memory | 232068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409283828 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3409283828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.932864391 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 63644702 ps |
| CPU time | 4.61 seconds |
| Started | Sep 09 10:33:41 PM UTC 24 |
| Finished | Sep 09 10:33:47 PM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932864391 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.932864391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.338035330 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 1788202017 ps |
| CPU time | 35.64 seconds |
| Started | Sep 09 10:33:44 PM UTC 24 |
| Finished | Sep 09 10:34:21 PM UTC 24 |
| Peak memory | 262504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338035330 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.338035330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.4083009254 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 317838808 ps |
| CPU time | 9.6 seconds |
| Started | Sep 09 10:33:45 PM UTC 24 |
| Finished | Sep 09 10:33:56 PM UTC 24 |
| Peak memory | 262824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083009254 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.4083009254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.404237007 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 599051818 ps |
| CPU time | 34.65 seconds |
| Started | Sep 09 10:33:49 PM UTC 24 |
| Finished | Sep 09 10:34:25 PM UTC 24 |
| Peak memory | 260780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=404237007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 39.lc_ctrl_stress_all.404237007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.328696979 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 47541667 ps |
| CPU time | 1.41 seconds |
| Started | Sep 09 10:33:44 PM UTC 24 |
| Finished | Sep 09 10:33:47 PM UTC 24 |
| Peak memory | 228692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328696979 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39. lc_ctrl_volatile_unlock_smoke.328696979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.2889339764 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 105500953 ps |
| CPU time | 1.56 seconds |
| Started | Sep 09 10:25:42 PM UTC 24 |
| Finished | Sep 09 10:25:45 PM UTC 24 |
| Peak memory | 218656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889339764 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2889339764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.283744051 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 40354201 ps |
| CPU time | 1.13 seconds |
| Started | Sep 09 10:25:25 PM UTC 24 |
| Finished | Sep 09 10:25:28 PM UTC 24 |
| Peak memory | 218376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283744051 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.283744051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.1945315605 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 3226577691 ps |
| CPU time | 16.9 seconds |
| Started | Sep 09 10:25:23 PM UTC 24 |
| Finished | Sep 09 10:25:41 PM UTC 24 |
| Peak memory | 237660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945315605 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1945315605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.4122606644 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 162204253 ps |
| CPU time | 2.6 seconds |
| Started | Sep 09 10:25:32 PM UTC 24 |
| Finished | Sep 09 10:25:36 PM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122606644 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.4122606644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.2425747270 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3449707051 ps |
| CPU time | 52.41 seconds |
| Started | Sep 09 10:25:31 PM UTC 24 |
| Finished | Sep 09 10:26:25 PM UTC 24 |
| Peak memory | 231948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425747270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jt ag_errors.2425747270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.3507840319 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1126600291 ps |
| CPU time | 4.89 seconds |
| Started | Sep 09 10:25:35 PM UTC 24 |
| Finished | Sep 09 10:25:41 PM UTC 24 |
| Peak memory | 229696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507840319 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_prior ity.3507840319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.2041041539 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 576981184 ps |
| CPU time | 19.58 seconds |
| Started | Sep 09 10:25:31 PM UTC 24 |
| Finished | Sep 09 10:25:52 PM UTC 24 |
| Peak memory | 231808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041041539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl _jtag_prog_failure.2041041539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1903093562 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 851784753 ps |
| CPU time | 21.71 seconds |
| Started | Sep 09 10:25:35 PM UTC 24 |
| Finished | Sep 09 10:25:58 PM UTC 24 |
| Peak memory | 229508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903093562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ ctrl_jtag_regwen_during_op.1903093562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.3104735550 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1176543240 ps |
| CPU time | 11.07 seconds |
| Started | Sep 09 10:25:27 PM UTC 24 |
| Finished | Sep 09 10:25:40 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104735550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_s moke.3104735550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.1601700194 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 2324167496 ps |
| CPU time | 49.47 seconds |
| Started | Sep 09 10:25:28 PM UTC 24 |
| Finished | Sep 09 10:26:19 PM UTC 24 |
| Peak memory | 282980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601700194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr l_jtag_state_failure.1601700194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.4193311415 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 577917894 ps |
| CPU time | 15.37 seconds |
| Started | Sep 09 10:25:28 PM UTC 24 |
| Finished | Sep 09 10:25:45 PM UTC 24 |
| Peak memory | 236244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193311415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ ctrl_jtag_state_post_trans.4193311415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.2573071036 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 200295986 ps |
| CPU time | 3.52 seconds |
| Started | Sep 09 10:25:22 PM UTC 24 |
| Finished | Sep 09 10:25:26 PM UTC 24 |
| Peak memory | 235972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573071036 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2573071036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.1979045371 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1210466215 ps |
| CPU time | 16.22 seconds |
| Started | Sep 09 10:25:24 PM UTC 24 |
| Finished | Sep 09 10:25:42 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979045371 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1979045371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.2165772743 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 770983039 ps |
| CPU time | 40.25 seconds |
| Started | Sep 09 10:25:42 PM UTC 24 |
| Finished | Sep 09 10:26:24 PM UTC 24 |
| Peak memory | 298296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165772743 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2165772743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.2440281620 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1484200457 ps |
| CPU time | 15.09 seconds |
| Started | Sep 09 10:25:40 PM UTC 24 |
| Finished | Sep 09 10:25:56 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440281620 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_tok en_digest.2440281620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.3597988284 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 862891008 ps |
| CPU time | 10.85 seconds |
| Started | Sep 09 10:25:38 PM UTC 24 |
| Finished | Sep 09 10:25:50 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597988284 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_ mux.3597988284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.887317439 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 173067762 ps |
| CPU time | 12.3 seconds |
| Started | Sep 09 10:25:24 PM UTC 24 |
| Finished | Sep 09 10:25:38 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887317439 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.887317439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.474156477 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 143989099 ps |
| CPU time | 2.75 seconds |
| Started | Sep 09 10:25:19 PM UTC 24 |
| Finished | Sep 09 10:25:23 PM UTC 24 |
| Peak memory | 225792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474156477 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.474156477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.888205782 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 487562080 ps |
| CPU time | 27.51 seconds |
| Started | Sep 09 10:25:21 PM UTC 24 |
| Finished | Sep 09 10:25:49 PM UTC 24 |
| Peak memory | 262532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888205782 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.888205782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.3551368297 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 69261026 ps |
| CPU time | 7.04 seconds |
| Started | Sep 09 10:25:22 PM UTC 24 |
| Finished | Sep 09 10:25:30 PM UTC 24 |
| Peak memory | 262480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551368297 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3551368297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.2863458441 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 12232347524 ps |
| CPU time | 203.81 seconds |
| Started | Sep 09 10:25:41 PM UTC 24 |
| Finished | Sep 09 10:29:07 PM UTC 24 |
| Peak memory | 262956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2863458441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 4.lc_ctrl_stress_all.2863458441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.505036469 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 40061116 ps |
| CPU time | 1.26 seconds |
| Started | Sep 09 10:25:21 PM UTC 24 |
| Finished | Sep 09 10:25:23 PM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505036469 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.l c_ctrl_volatile_unlock_smoke.505036469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.215515695 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 19923459 ps |
| CPU time | 1.15 seconds |
| Started | Sep 09 10:34:00 PM UTC 24 |
| Finished | Sep 09 10:34:03 PM UTC 24 |
| Peak memory | 217372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215515695 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.215515695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_errors.1747071729 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 1628996564 ps |
| CPU time | 22.77 seconds |
| Started | Sep 09 10:33:55 PM UTC 24 |
| Finished | Sep 09 10:34:19 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747071729 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1747071729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.2804140305 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 1885290256 ps |
| CPU time | 9.69 seconds |
| Started | Sep 09 10:33:55 PM UTC 24 |
| Finished | Sep 09 10:34:06 PM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804140305 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2804140305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.188548651 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 282717334 ps |
| CPU time | 4.28 seconds |
| Started | Sep 09 10:33:54 PM UTC 24 |
| Finished | Sep 09 10:33:59 PM UTC 24 |
| Peak memory | 234264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188548651 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.188548651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.74931135 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 870622105 ps |
| CPU time | 25.66 seconds |
| Started | Sep 09 10:33:57 PM UTC 24 |
| Finished | Sep 09 10:34:24 PM UTC 24 |
| Peak memory | 237652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74931135 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.74931135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.3347584750 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 786363308 ps |
| CPU time | 13.37 seconds |
| Started | Sep 09 10:33:57 PM UTC 24 |
| Finished | Sep 09 10:34:12 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347584750 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_to ken_digest.3347584750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.2073275011 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 1336321837 ps |
| CPU time | 9.85 seconds |
| Started | Sep 09 10:33:57 PM UTC 24 |
| Finished | Sep 09 10:34:08 PM UTC 24 |
| Peak memory | 231920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073275011 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token _mux.2073275011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.1759446430 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1097381249 ps |
| CPU time | 9.82 seconds |
| Started | Sep 09 10:33:55 PM UTC 24 |
| Finished | Sep 09 10:34:06 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759446430 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1759446430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.1871178410 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 66029591 ps |
| CPU time | 3.13 seconds |
| Started | Sep 09 10:33:51 PM UTC 24 |
| Finished | Sep 09 10:33:56 PM UTC 24 |
| Peak memory | 229948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871178410 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1871178410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.4256928895 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 540314441 ps |
| CPU time | 30.96 seconds |
| Started | Sep 09 10:33:53 PM UTC 24 |
| Finished | Sep 09 10:34:25 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256928895 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.4256928895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.2411587017 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 488439148 ps |
| CPU time | 9.27 seconds |
| Started | Sep 09 10:33:54 PM UTC 24 |
| Finished | Sep 09 10:34:04 PM UTC 24 |
| Peak memory | 262492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411587017 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2411587017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.2862150295 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 4060389677 ps |
| CPU time | 41.82 seconds |
| Started | Sep 09 10:33:57 PM UTC 24 |
| Finished | Sep 09 10:34:41 PM UTC 24 |
| Peak memory | 237664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2862150295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 40.lc_ctrl_stress_all.2862150295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.2713478979 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 2008901962 ps |
| CPU time | 93.65 seconds |
| Started | Sep 09 10:34:00 PM UTC 24 |
| Finished | Sep 09 10:35:36 PM UTC 24 |
| Peak memory | 289616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713478979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.2713478979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2272092952 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 86329915 ps |
| CPU time | 1.46 seconds |
| Started | Sep 09 10:33:51 PM UTC 24 |
| Finished | Sep 09 10:33:54 PM UTC 24 |
| Peak memory | 222380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272092952 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40 .lc_ctrl_volatile_unlock_smoke.2272092952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.895551001 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 30750469 ps |
| CPU time | 1.47 seconds |
| Started | Sep 09 10:34:10 PM UTC 24 |
| Finished | Sep 09 10:34:12 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895551001 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.895551001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_errors.4202221955 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 710656237 ps |
| CPU time | 29.06 seconds |
| Started | Sep 09 10:34:03 PM UTC 24 |
| Finished | Sep 09 10:34:34 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202221955 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.4202221955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.947860275 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 1270926223 ps |
| CPU time | 14.12 seconds |
| Started | Sep 09 10:34:05 PM UTC 24 |
| Finished | Sep 09 10:34:20 PM UTC 24 |
| Peak memory | 229608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947860275 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.947860275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.4159903294 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 477917807 ps |
| CPU time | 4.13 seconds |
| Started | Sep 09 10:34:03 PM UTC 24 |
| Finished | Sep 09 10:34:09 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159903294 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.4159903294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.1377837886 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 384229873 ps |
| CPU time | 19.53 seconds |
| Started | Sep 09 10:34:06 PM UTC 24 |
| Finished | Sep 09 10:34:27 PM UTC 24 |
| Peak memory | 237660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377837886 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1377837886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.2334059003 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 3560353297 ps |
| CPU time | 12.29 seconds |
| Started | Sep 09 10:34:07 PM UTC 24 |
| Finished | Sep 09 10:34:20 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334059003 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_to ken_digest.2334059003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.3223142458 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1727554471 ps |
| CPU time | 11.56 seconds |
| Started | Sep 09 10:34:07 PM UTC 24 |
| Finished | Sep 09 10:34:20 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223142458 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token _mux.3223142458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.1490862911 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 440688795 ps |
| CPU time | 11.54 seconds |
| Started | Sep 09 10:34:05 PM UTC 24 |
| Finished | Sep 09 10:34:17 PM UTC 24 |
| Peak memory | 232196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490862911 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1490862911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.1713416304 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 51240120 ps |
| CPU time | 3.95 seconds |
| Started | Sep 09 10:34:02 PM UTC 24 |
| Finished | Sep 09 10:34:07 PM UTC 24 |
| Peak memory | 225464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713416304 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1713416304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.3416778151 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 130030156 ps |
| CPU time | 22.56 seconds |
| Started | Sep 09 10:34:02 PM UTC 24 |
| Finished | Sep 09 10:34:26 PM UTC 24 |
| Peak memory | 262580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416778151 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3416778151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.210668523 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 243233793 ps |
| CPU time | 9.73 seconds |
| Started | Sep 09 10:34:03 PM UTC 24 |
| Finished | Sep 09 10:34:14 PM UTC 24 |
| Peak memory | 262572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210668523 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.210668523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.1761494324 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 891623615 ps |
| CPU time | 39.22 seconds |
| Started | Sep 09 10:34:08 PM UTC 24 |
| Finished | Sep 09 10:34:49 PM UTC 24 |
| Peak memory | 237672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1761494324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 41.lc_ctrl_stress_all.1761494324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2915006718 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1941156780 ps |
| CPU time | 45.79 seconds |
| Started | Sep 09 10:34:08 PM UTC 24 |
| Finished | Sep 09 10:34:56 PM UTC 24 |
| Peak memory | 289364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915006718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2915006718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3503899340 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 16234239 ps |
| CPU time | 1.46 seconds |
| Started | Sep 09 10:34:02 PM UTC 24 |
| Finished | Sep 09 10:34:04 PM UTC 24 |
| Peak memory | 222384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503899340 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41 .lc_ctrl_volatile_unlock_smoke.3503899340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.920856180 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 59341947 ps |
| CPU time | 1.41 seconds |
| Started | Sep 09 10:34:23 PM UTC 24 |
| Finished | Sep 09 10:34:25 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920856180 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.920856180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.1406366747 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 1019733256 ps |
| CPU time | 12.7 seconds |
| Started | Sep 09 10:34:16 PM UTC 24 |
| Finished | Sep 09 10:34:30 PM UTC 24 |
| Peak memory | 229972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406366747 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1406366747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.950222276 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 338395915 ps |
| CPU time | 2.43 seconds |
| Started | Sep 09 10:34:20 PM UTC 24 |
| Finished | Sep 09 10:34:23 PM UTC 24 |
| Peak memory | 229428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950222276 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.950222276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.3158956633 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 183035238 ps |
| CPU time | 5.27 seconds |
| Started | Sep 09 10:34:15 PM UTC 24 |
| Finished | Sep 09 10:34:21 PM UTC 24 |
| Peak memory | 236052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158956633 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3158956633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.1434138497 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 1026984927 ps |
| CPU time | 17.8 seconds |
| Started | Sep 09 10:34:21 PM UTC 24 |
| Finished | Sep 09 10:34:40 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434138497 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1434138497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.227757673 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 382335902 ps |
| CPU time | 12.67 seconds |
| Started | Sep 09 10:34:21 PM UTC 24 |
| Finished | Sep 09 10:34:35 PM UTC 24 |
| Peak memory | 237512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227757673 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_tok en_digest.227757673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.260378210 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 1053678490 ps |
| CPU time | 9.65 seconds |
| Started | Sep 09 10:34:21 PM UTC 24 |
| Finished | Sep 09 10:34:32 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260378210 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_ mux.260378210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.7333265 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 4244965984 ps |
| CPU time | 17.28 seconds |
| Started | Sep 09 10:34:18 PM UTC 24 |
| Finished | Sep 09 10:34:37 PM UTC 24 |
| Peak memory | 231932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7333265 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.7333265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.2277595043 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 69146469 ps |
| CPU time | 2.72 seconds |
| Started | Sep 09 10:34:10 PM UTC 24 |
| Finished | Sep 09 10:34:13 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277595043 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2277595043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.836596140 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 1301048053 ps |
| CPU time | 26.1 seconds |
| Started | Sep 09 10:34:13 PM UTC 24 |
| Finished | Sep 09 10:34:40 PM UTC 24 |
| Peak memory | 262508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836596140 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.836596140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.2377464725 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 183591481 ps |
| CPU time | 10.71 seconds |
| Started | Sep 09 10:34:14 PM UTC 24 |
| Finished | Sep 09 10:34:26 PM UTC 24 |
| Peak memory | 260784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377464725 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2377464725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.3497417646 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 1800208136 ps |
| CPU time | 75.39 seconds |
| Started | Sep 09 10:34:21 PM UTC 24 |
| Finished | Sep 09 10:35:39 PM UTC 24 |
| Peak memory | 291180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3497417646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 42.lc_ctrl_stress_all.3497417646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.4143751005 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 11329875258 ps |
| CPU time | 140.02 seconds |
| Started | Sep 09 10:34:21 PM UTC 24 |
| Finished | Sep 09 10:36:44 PM UTC 24 |
| Peak memory | 285220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143751005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.4143751005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.607249347 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 45463845 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 10:34:13 PM UTC 24 |
| Finished | Sep 09 10:34:15 PM UTC 24 |
| Peak memory | 228532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607249347 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42. lc_ctrl_volatile_unlock_smoke.607249347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.2249997216 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 12506092 ps |
| CPU time | 1.37 seconds |
| Started | Sep 09 10:34:31 PM UTC 24 |
| Finished | Sep 09 10:34:34 PM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249997216 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2249997216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_errors.2643751526 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 1488793328 ps |
| CPU time | 18.13 seconds |
| Started | Sep 09 10:34:27 PM UTC 24 |
| Finished | Sep 09 10:34:47 PM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643751526 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2643751526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.1107605282 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 193332282 ps |
| CPU time | 6.46 seconds |
| Started | Sep 09 10:34:27 PM UTC 24 |
| Finished | Sep 09 10:34:35 PM UTC 24 |
| Peak memory | 229508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107605282 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1107605282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.3987030031 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 21561088 ps |
| CPU time | 2.27 seconds |
| Started | Sep 09 10:34:27 PM UTC 24 |
| Finished | Sep 09 10:34:30 PM UTC 24 |
| Peak memory | 232028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987030031 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3987030031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.2747737633 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 793794535 ps |
| CPU time | 14.5 seconds |
| Started | Sep 09 10:34:27 PM UTC 24 |
| Finished | Sep 09 10:34:43 PM UTC 24 |
| Peak memory | 232208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747737633 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2747737633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.2006256327 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 376740165 ps |
| CPU time | 10.78 seconds |
| Started | Sep 09 10:34:29 PM UTC 24 |
| Finished | Sep 09 10:34:41 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006256327 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_to ken_digest.2006256327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.2024506707 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 666172440 ps |
| CPU time | 15.08 seconds |
| Started | Sep 09 10:34:27 PM UTC 24 |
| Finished | Sep 09 10:34:44 PM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024506707 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token _mux.2024506707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.774809380 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 428240830 ps |
| CPU time | 10.68 seconds |
| Started | Sep 09 10:34:27 PM UTC 24 |
| Finished | Sep 09 10:34:39 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774809380 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.774809380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.1382159862 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 20583787 ps |
| CPU time | 2.05 seconds |
| Started | Sep 09 10:34:23 PM UTC 24 |
| Finished | Sep 09 10:34:26 PM UTC 24 |
| Peak memory | 223484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382159862 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1382159862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.3448458109 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 326724059 ps |
| CPU time | 36.18 seconds |
| Started | Sep 09 10:34:25 PM UTC 24 |
| Finished | Sep 09 10:35:03 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448458109 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3448458109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.2397864464 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 250838330 ps |
| CPU time | 9.7 seconds |
| Started | Sep 09 10:34:25 PM UTC 24 |
| Finished | Sep 09 10:34:36 PM UTC 24 |
| Peak memory | 262416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397864464 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2397864464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.2990893740 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 15869902604 ps |
| CPU time | 272.69 seconds |
| Started | Sep 09 10:34:29 PM UTC 24 |
| Finished | Sep 09 10:39:06 PM UTC 24 |
| Peak memory | 262640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2990893740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 43.lc_ctrl_stress_all.2990893740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3019743260 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 118389849 ps |
| CPU time | 1.4 seconds |
| Started | Sep 09 10:34:25 PM UTC 24 |
| Finished | Sep 09 10:34:27 PM UTC 24 |
| Peak memory | 222380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019743260 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43 .lc_ctrl_volatile_unlock_smoke.3019743260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.846576765 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 17793531 ps |
| CPU time | 1.55 seconds |
| Started | Sep 09 10:34:42 PM UTC 24 |
| Finished | Sep 09 10:34:44 PM UTC 24 |
| Peak memory | 219064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846576765 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.846576765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_errors.2692031181 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 1253210847 ps |
| CPU time | 12.23 seconds |
| Started | Sep 09 10:34:37 PM UTC 24 |
| Finished | Sep 09 10:34:50 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692031181 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2692031181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.2045938689 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 383033164 ps |
| CPU time | 7.75 seconds |
| Started | Sep 09 10:34:39 PM UTC 24 |
| Finished | Sep 09 10:34:48 PM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045938689 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2045938689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.4189406056 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 72316995 ps |
| CPU time | 4.4 seconds |
| Started | Sep 09 10:34:37 PM UTC 24 |
| Finished | Sep 09 10:34:42 PM UTC 24 |
| Peak memory | 235976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189406056 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.4189406056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.2845590462 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 760336134 ps |
| CPU time | 14.34 seconds |
| Started | Sep 09 10:34:39 PM UTC 24 |
| Finished | Sep 09 10:34:55 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845590462 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2845590462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2570027180 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 309429966 ps |
| CPU time | 10.21 seconds |
| Started | Sep 09 10:34:42 PM UTC 24 |
| Finished | Sep 09 10:34:53 PM UTC 24 |
| Peak memory | 237784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570027180 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_to ken_digest.2570027180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.3688606294 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 1558785149 ps |
| CPU time | 13.71 seconds |
| Started | Sep 09 10:34:40 PM UTC 24 |
| Finished | Sep 09 10:34:55 PM UTC 24 |
| Peak memory | 237580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688606294 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token _mux.3688606294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.2593048345 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 1137463053 ps |
| CPU time | 8.56 seconds |
| Started | Sep 09 10:34:39 PM UTC 24 |
| Finished | Sep 09 10:34:49 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593048345 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2593048345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.2345463654 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 416369245 ps |
| CPU time | 6.84 seconds |
| Started | Sep 09 10:34:33 PM UTC 24 |
| Finished | Sep 09 10:34:41 PM UTC 24 |
| Peak memory | 229880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345463654 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2345463654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.1696887584 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 325824062 ps |
| CPU time | 37.77 seconds |
| Started | Sep 09 10:34:35 PM UTC 24 |
| Finished | Sep 09 10:35:15 PM UTC 24 |
| Peak memory | 262504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696887584 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1696887584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.4224989295 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 318582155 ps |
| CPU time | 9 seconds |
| Started | Sep 09 10:34:37 PM UTC 24 |
| Finished | Sep 09 10:34:47 PM UTC 24 |
| Peak memory | 262828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224989295 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.4224989295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.3894001114 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 3642773848 ps |
| CPU time | 76.64 seconds |
| Started | Sep 09 10:34:42 PM UTC 24 |
| Finished | Sep 09 10:36:00 PM UTC 24 |
| Peak memory | 293364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3894001114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 44.lc_ctrl_stress_all.3894001114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1032722791 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 13471386 ps |
| CPU time | 1.6 seconds |
| Started | Sep 09 10:34:35 PM UTC 24 |
| Finished | Sep 09 10:34:38 PM UTC 24 |
| Peak memory | 228508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032722791 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44 .lc_ctrl_volatile_unlock_smoke.1032722791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.3615391797 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 73048915 ps |
| CPU time | 1.58 seconds |
| Started | Sep 09 10:34:51 PM UTC 24 |
| Finished | Sep 09 10:34:53 PM UTC 24 |
| Peak memory | 218588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615391797 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3615391797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_errors.4163255873 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 2500187837 ps |
| CPU time | 18.74 seconds |
| Started | Sep 09 10:34:46 PM UTC 24 |
| Finished | Sep 09 10:35:06 PM UTC 24 |
| Peak memory | 232276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163255873 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.4163255873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.1445074505 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 531270872 ps |
| CPU time | 8.21 seconds |
| Started | Sep 09 10:34:48 PM UTC 24 |
| Finished | Sep 09 10:34:57 PM UTC 24 |
| Peak memory | 229676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445074505 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1445074505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.380861198 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 301955511 ps |
| CPU time | 3.55 seconds |
| Started | Sep 09 10:34:45 PM UTC 24 |
| Finished | Sep 09 10:34:50 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380861198 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.380861198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.1252459138 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 1356876179 ps |
| CPU time | 14.37 seconds |
| Started | Sep 09 10:34:48 PM UTC 24 |
| Finished | Sep 09 10:35:04 PM UTC 24 |
| Peak memory | 230160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252459138 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1252459138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.1381674589 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 1405701173 ps |
| CPU time | 22.93 seconds |
| Started | Sep 09 10:34:51 PM UTC 24 |
| Finished | Sep 09 10:35:15 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381674589 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_to ken_digest.1381674589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.574012786 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 216270638 ps |
| CPU time | 8.34 seconds |
| Started | Sep 09 10:34:48 PM UTC 24 |
| Finished | Sep 09 10:34:57 PM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574012786 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_ mux.574012786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.666478023 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1073298172 ps |
| CPU time | 11.93 seconds |
| Started | Sep 09 10:34:46 PM UTC 24 |
| Finished | Sep 09 10:34:59 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666478023 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.666478023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.3738201639 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 149866158 ps |
| CPU time | 2.91 seconds |
| Started | Sep 09 10:34:42 PM UTC 24 |
| Finished | Sep 09 10:34:46 PM UTC 24 |
| Peak memory | 225460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738201639 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3738201639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.3348051536 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 356283029 ps |
| CPU time | 29.58 seconds |
| Started | Sep 09 10:34:45 PM UTC 24 |
| Finished | Sep 09 10:35:16 PM UTC 24 |
| Peak memory | 260784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348051536 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3348051536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.3859453387 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 83478840 ps |
| CPU time | 8.58 seconds |
| Started | Sep 09 10:34:45 PM UTC 24 |
| Finished | Sep 09 10:34:55 PM UTC 24 |
| Peak memory | 262576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859453387 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3859453387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.1040539377 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 21819627942 ps |
| CPU time | 132.98 seconds |
| Started | Sep 09 10:34:51 PM UTC 24 |
| Finished | Sep 09 10:37:06 PM UTC 24 |
| Peak memory | 295352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1040539377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 45.lc_ctrl_stress_all.1040539377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2216276930 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 31929641 ps |
| CPU time | 1.14 seconds |
| Started | Sep 09 10:34:43 PM UTC 24 |
| Finished | Sep 09 10:34:45 PM UTC 24 |
| Peak memory | 218292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216276930 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45 .lc_ctrl_volatile_unlock_smoke.2216276930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.2909760470 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 18386146 ps |
| CPU time | 1.52 seconds |
| Started | Sep 09 10:34:58 PM UTC 24 |
| Finished | Sep 09 10:35:01 PM UTC 24 |
| Peak memory | 218528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909760470 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2909760470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.3530948241 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 526769395 ps |
| CPU time | 16.17 seconds |
| Started | Sep 09 10:34:54 PM UTC 24 |
| Finished | Sep 09 10:35:11 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530948241 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3530948241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.2838541956 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 5774686188 ps |
| CPU time | 24.36 seconds |
| Started | Sep 09 10:34:54 PM UTC 24 |
| Finished | Sep 09 10:35:20 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838541956 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2838541956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.4088066061 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 51375001 ps |
| CPU time | 3.48 seconds |
| Started | Sep 09 10:34:52 PM UTC 24 |
| Finished | Sep 09 10:34:57 PM UTC 24 |
| Peak memory | 232276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088066061 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.4088066061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.879376738 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 3027713382 ps |
| CPU time | 29.57 seconds |
| Started | Sep 09 10:34:56 PM UTC 24 |
| Finished | Sep 09 10:35:27 PM UTC 24 |
| Peak memory | 237640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879376738 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.879376738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.954708508 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 1126822600 ps |
| CPU time | 13.4 seconds |
| Started | Sep 09 10:34:56 PM UTC 24 |
| Finished | Sep 09 10:35:11 PM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954708508 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_tok en_digest.954708508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.13823975 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 447922031 ps |
| CPU time | 12.76 seconds |
| Started | Sep 09 10:34:56 PM UTC 24 |
| Finished | Sep 09 10:35:10 PM UTC 24 |
| Peak memory | 232012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13823975 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.13823975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.3448487150 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 400183870 ps |
| CPU time | 9.6 seconds |
| Started | Sep 09 10:34:54 PM UTC 24 |
| Finished | Sep 09 10:35:05 PM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448487150 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3448487150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.3657734240 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 284146145 ps |
| CPU time | 6.62 seconds |
| Started | Sep 09 10:34:51 PM UTC 24 |
| Finished | Sep 09 10:34:59 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657734240 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3657734240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.264725844 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 290757347 ps |
| CPU time | 27.57 seconds |
| Started | Sep 09 10:34:52 PM UTC 24 |
| Finished | Sep 09 10:35:21 PM UTC 24 |
| Peak memory | 258408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264725844 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.264725844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.3064113128 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 1247227714 ps |
| CPU time | 5.3 seconds |
| Started | Sep 09 10:34:52 PM UTC 24 |
| Finished | Sep 09 10:34:59 PM UTC 24 |
| Peak memory | 234524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064113128 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3064113128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.2201285171 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 11817221648 ps |
| CPU time | 84.8 seconds |
| Started | Sep 09 10:34:56 PM UTC 24 |
| Finished | Sep 09 10:36:23 PM UTC 24 |
| Peak memory | 280996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2201285171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 46.lc_ctrl_stress_all.2201285171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1048023569 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 110272972 ps |
| CPU time | 1.5 seconds |
| Started | Sep 09 10:34:51 PM UTC 24 |
| Finished | Sep 09 10:34:53 PM UTC 24 |
| Peak memory | 228528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048023569 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46 .lc_ctrl_volatile_unlock_smoke.1048023569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.3045219327 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 49408401 ps |
| CPU time | 1.2 seconds |
| Started | Sep 09 10:35:11 PM UTC 24 |
| Finished | Sep 09 10:35:13 PM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045219327 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3045219327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.1975267017 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 364109456 ps |
| CPU time | 17.78 seconds |
| Started | Sep 09 10:35:02 PM UTC 24 |
| Finished | Sep 09 10:35:21 PM UTC 24 |
| Peak memory | 231680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975267017 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1975267017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.3706733219 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 360644960 ps |
| CPU time | 6.99 seconds |
| Started | Sep 09 10:35:03 PM UTC 24 |
| Finished | Sep 09 10:35:11 PM UTC 24 |
| Peak memory | 229616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706733219 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3706733219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.2738615260 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 219852496 ps |
| CPU time | 3.79 seconds |
| Started | Sep 09 10:35:02 PM UTC 24 |
| Finished | Sep 09 10:35:06 PM UTC 24 |
| Peak memory | 231896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738615260 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2738615260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.3303449815 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2477270239 ps |
| CPU time | 18.52 seconds |
| Started | Sep 09 10:35:04 PM UTC 24 |
| Finished | Sep 09 10:35:24 PM UTC 24 |
| Peak memory | 232272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303449815 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3303449815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.567778623 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1596917248 ps |
| CPU time | 20.59 seconds |
| Started | Sep 09 10:35:06 PM UTC 24 |
| Finished | Sep 09 10:35:28 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567778623 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_tok en_digest.567778623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.2610718527 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 1163219059 ps |
| CPU time | 7.24 seconds |
| Started | Sep 09 10:35:05 PM UTC 24 |
| Finished | Sep 09 10:35:13 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610718527 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token _mux.2610718527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.891249194 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 757112151 ps |
| CPU time | 7.26 seconds |
| Started | Sep 09 10:35:02 PM UTC 24 |
| Finished | Sep 09 10:35:10 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891249194 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.891249194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.229911391 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 218405906 ps |
| CPU time | 1.82 seconds |
| Started | Sep 09 10:34:58 PM UTC 24 |
| Finished | Sep 09 10:35:01 PM UTC 24 |
| Peak memory | 222320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229911391 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.229911391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.128056505 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 819693512 ps |
| CPU time | 31.66 seconds |
| Started | Sep 09 10:35:00 PM UTC 24 |
| Finished | Sep 09 10:35:33 PM UTC 24 |
| Peak memory | 260456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128056505 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.128056505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.1596622584 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 158940376 ps |
| CPU time | 10.02 seconds |
| Started | Sep 09 10:35:00 PM UTC 24 |
| Finished | Sep 09 10:35:11 PM UTC 24 |
| Peak memory | 260356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596622584 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1596622584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.3067508849 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 19876921451 ps |
| CPU time | 308.25 seconds |
| Started | Sep 09 10:35:07 PM UTC 24 |
| Finished | Sep 09 10:40:20 PM UTC 24 |
| Peak memory | 262644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3067508849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 47.lc_ctrl_stress_all.3067508849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.2777906347 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 4586902863 ps |
| CPU time | 90.34 seconds |
| Started | Sep 09 10:35:07 PM UTC 24 |
| Finished | Sep 09 10:36:40 PM UTC 24 |
| Peak memory | 295564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777906347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.2777906347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.4243081581 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 43631717 ps |
| CPU time | 1.35 seconds |
| Started | Sep 09 10:34:58 PM UTC 24 |
| Finished | Sep 09 10:35:01 PM UTC 24 |
| Peak memory | 218232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243081581 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47 .lc_ctrl_volatile_unlock_smoke.4243081581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.1425139959 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 29477398 ps |
| CPU time | 1.48 seconds |
| Started | Sep 09 10:35:19 PM UTC 24 |
| Finished | Sep 09 10:35:21 PM UTC 24 |
| Peak memory | 219124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425139959 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1425139959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.638315268 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 245232470 ps |
| CPU time | 14.86 seconds |
| Started | Sep 09 10:35:14 PM UTC 24 |
| Finished | Sep 09 10:35:31 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638315268 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.638315268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.4225713361 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 1028242600 ps |
| CPU time | 17.01 seconds |
| Started | Sep 09 10:35:16 PM UTC 24 |
| Finished | Sep 09 10:35:34 PM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225713361 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.4225713361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.3093106222 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 27614459 ps |
| CPU time | 2.18 seconds |
| Started | Sep 09 10:35:13 PM UTC 24 |
| Finished | Sep 09 10:35:16 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093106222 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3093106222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.2506777933 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2711356714 ps |
| CPU time | 27.94 seconds |
| Started | Sep 09 10:35:16 PM UTC 24 |
| Finished | Sep 09 10:35:45 PM UTC 24 |
| Peak memory | 237644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506777933 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2506777933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.2370131595 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 415962071 ps |
| CPU time | 13.38 seconds |
| Started | Sep 09 10:35:18 PM UTC 24 |
| Finished | Sep 09 10:35:32 PM UTC 24 |
| Peak memory | 237508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370131595 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_to ken_digest.2370131595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.1701707825 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 198236041 ps |
| CPU time | 9.06 seconds |
| Started | Sep 09 10:35:18 PM UTC 24 |
| Finished | Sep 09 10:35:28 PM UTC 24 |
| Peak memory | 232196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701707825 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token _mux.1701707825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.315566235 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 1691226338 ps |
| CPU time | 15.72 seconds |
| Started | Sep 09 10:35:14 PM UTC 24 |
| Finished | Sep 09 10:35:32 PM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315566235 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.315566235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.3684195248 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 93577150 ps |
| CPU time | 5.58 seconds |
| Started | Sep 09 10:35:11 PM UTC 24 |
| Finished | Sep 09 10:35:18 PM UTC 24 |
| Peak memory | 229952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684195248 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3684195248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.4235077679 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 720579610 ps |
| CPU time | 23.69 seconds |
| Started | Sep 09 10:35:13 PM UTC 24 |
| Finished | Sep 09 10:35:38 PM UTC 24 |
| Peak memory | 262576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235077679 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.4235077679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.1429620705 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 418243651 ps |
| CPU time | 10.21 seconds |
| Started | Sep 09 10:35:13 PM UTC 24 |
| Finished | Sep 09 10:35:25 PM UTC 24 |
| Peak memory | 262572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429620705 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1429620705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.2177231105 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 26060389256 ps |
| CPU time | 137.97 seconds |
| Started | Sep 09 10:35:18 PM UTC 24 |
| Finished | Sep 09 10:37:38 PM UTC 24 |
| Peak memory | 281000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2177231105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 48.lc_ctrl_stress_all.2177231105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1216293315 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 6620476873 ps |
| CPU time | 108.41 seconds |
| Started | Sep 09 10:35:18 PM UTC 24 |
| Finished | Sep 09 10:37:08 PM UTC 24 |
| Peak memory | 279076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216293315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.1216293315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3792323667 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 16812009 ps |
| CPU time | 1.26 seconds |
| Started | Sep 09 10:35:13 PM UTC 24 |
| Finished | Sep 09 10:35:15 PM UTC 24 |
| Peak memory | 218348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792323667 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48 .lc_ctrl_volatile_unlock_smoke.3792323667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.4199501354 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 12437194 ps |
| CPU time | 1.38 seconds |
| Started | Sep 09 10:35:28 PM UTC 24 |
| Finished | Sep 09 10:35:31 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199501354 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.4199501354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.5013013 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 330303843 ps |
| CPU time | 13.67 seconds |
| Started | Sep 09 10:35:23 PM UTC 24 |
| Finished | Sep 09 10:35:38 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5013013 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.5013013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.2245747112 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 697314600 ps |
| CPU time | 15.05 seconds |
| Started | Sep 09 10:35:26 PM UTC 24 |
| Finished | Sep 09 10:35:43 PM UTC 24 |
| Peak memory | 229632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245747112 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2245747112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.1046022003 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 181140765 ps |
| CPU time | 3.02 seconds |
| Started | Sep 09 10:35:23 PM UTC 24 |
| Finished | Sep 09 10:35:27 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046022003 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1046022003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.2028067162 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1116296246 ps |
| CPU time | 23.52 seconds |
| Started | Sep 09 10:35:26 PM UTC 24 |
| Finished | Sep 09 10:35:51 PM UTC 24 |
| Peak memory | 237664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028067162 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2028067162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.1369687504 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 796942583 ps |
| CPU time | 9.36 seconds |
| Started | Sep 09 10:35:26 PM UTC 24 |
| Finished | Sep 09 10:35:37 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369687504 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_to ken_digest.1369687504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.4028434178 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 531540018 ps |
| CPU time | 13.43 seconds |
| Started | Sep 09 10:35:26 PM UTC 24 |
| Finished | Sep 09 10:35:41 PM UTC 24 |
| Peak memory | 237580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028434178 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token _mux.4028434178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.845520597 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 353476512 ps |
| CPU time | 15.06 seconds |
| Started | Sep 09 10:35:24 PM UTC 24 |
| Finished | Sep 09 10:35:40 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845520597 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.845520597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.360161756 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 17023646 ps |
| CPU time | 1.8 seconds |
| Started | Sep 09 10:35:21 PM UTC 24 |
| Finished | Sep 09 10:35:23 PM UTC 24 |
| Peak memory | 222324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360161756 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.360161756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.3212548056 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 241974490 ps |
| CPU time | 20.6 seconds |
| Started | Sep 09 10:35:23 PM UTC 24 |
| Finished | Sep 09 10:35:44 PM UTC 24 |
| Peak memory | 260452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212548056 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3212548056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.1002490854 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 69577472 ps |
| CPU time | 5.03 seconds |
| Started | Sep 09 10:35:23 PM UTC 24 |
| Finished | Sep 09 10:35:29 PM UTC 24 |
| Peak memory | 236308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002490854 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1002490854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.4089723111 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 6820887194 ps |
| CPU time | 43.78 seconds |
| Started | Sep 09 10:35:28 PM UTC 24 |
| Finished | Sep 09 10:36:14 PM UTC 24 |
| Peak memory | 285304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4089723111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 49.lc_ctrl_stress_all.4089723111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.3537890529 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 907899526 ps |
| CPU time | 38.32 seconds |
| Started | Sep 09 10:35:28 PM UTC 24 |
| Finished | Sep 09 10:36:08 PM UTC 24 |
| Peak memory | 262820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537890529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.3537890529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1399112119 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 20257393 ps |
| CPU time | 1.2 seconds |
| Started | Sep 09 10:35:21 PM UTC 24 |
| Finished | Sep 09 10:35:23 PM UTC 24 |
| Peak memory | 218556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399112119 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49 .lc_ctrl_volatile_unlock_smoke.1399112119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.2324946080 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 46025616 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 10:26:04 PM UTC 24 |
| Finished | Sep 09 10:26:06 PM UTC 24 |
| Peak memory | 217372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324946080 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2324946080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.1045847670 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 9903851 ps |
| CPU time | 1.41 seconds |
| Started | Sep 09 10:25:51 PM UTC 24 |
| Finished | Sep 09 10:25:54 PM UTC 24 |
| Peak memory | 218708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045847670 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1045847670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.3554489438 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1789511136 ps |
| CPU time | 9.45 seconds |
| Started | Sep 09 10:25:51 PM UTC 24 |
| Finished | Sep 09 10:26:01 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554489438 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3554489438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.2985955641 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 749277108 ps |
| CPU time | 19.8 seconds |
| Started | Sep 09 10:25:59 PM UTC 24 |
| Finished | Sep 09 10:26:20 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985955641 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2985955641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.2303832388 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 10129144605 ps |
| CPU time | 75.49 seconds |
| Started | Sep 09 10:25:57 PM UTC 24 |
| Finished | Sep 09 10:27:14 PM UTC 24 |
| Peak memory | 231948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303832388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jt ag_errors.2303832388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.937873726 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 511217616 ps |
| CPU time | 5.77 seconds |
| Started | Sep 09 10:26:00 PM UTC 24 |
| Finished | Sep 09 10:26:07 PM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937873726 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.937873726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.2157038111 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1887066775 ps |
| CPU time | 11.7 seconds |
| Started | Sep 09 10:25:54 PM UTC 24 |
| Finished | Sep 09 10:26:07 PM UTC 24 |
| Peak memory | 232196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157038111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl _jtag_prog_failure.2157038111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3892192785 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1341154977 ps |
| CPU time | 17.57 seconds |
| Started | Sep 09 10:26:00 PM UTC 24 |
| Finished | Sep 09 10:26:19 PM UTC 24 |
| Peak memory | 229492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892192785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ ctrl_jtag_regwen_during_op.3892192785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.3418231612 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 901415056 ps |
| CPU time | 7.03 seconds |
| Started | Sep 09 10:25:52 PM UTC 24 |
| Finished | Sep 09 10:26:00 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418231612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_s moke.3418231612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.3126464787 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1331463782 ps |
| CPU time | 42.55 seconds |
| Started | Sep 09 10:25:52 PM UTC 24 |
| Finished | Sep 09 10:26:36 PM UTC 24 |
| Peak memory | 281196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126464787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr l_jtag_state_failure.3126464787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.667696352 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 403915189 ps |
| CPU time | 14.14 seconds |
| Started | Sep 09 10:25:53 PM UTC 24 |
| Finished | Sep 09 10:26:09 PM UTC 24 |
| Peak memory | 262512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667696352 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_c trl_jtag_state_post_trans.667696352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.1932160606 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 117602314 ps |
| CPU time | 2.74 seconds |
| Started | Sep 09 10:25:49 PM UTC 24 |
| Finished | Sep 09 10:25:52 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932160606 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1932160606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.4088318958 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 699658561 ps |
| CPU time | 12.1 seconds |
| Started | Sep 09 10:25:51 PM UTC 24 |
| Finished | Sep 09 10:26:04 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088318958 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.4088318958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.3459600719 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1327914067 ps |
| CPU time | 15.58 seconds |
| Started | Sep 09 10:26:02 PM UTC 24 |
| Finished | Sep 09 10:26:18 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459600719 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3459600719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.780975450 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 394198758 ps |
| CPU time | 16.67 seconds |
| Started | Sep 09 10:26:03 PM UTC 24 |
| Finished | Sep 09 10:26:21 PM UTC 24 |
| Peak memory | 232008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780975450 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_toke n_digest.780975450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.4043643612 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 190209687 ps |
| CPU time | 9.06 seconds |
| Started | Sep 09 10:26:02 PM UTC 24 |
| Finished | Sep 09 10:26:12 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043643612 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_ mux.4043643612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.400161324 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 625725049 ps |
| CPU time | 13.22 seconds |
| Started | Sep 09 10:25:51 PM UTC 24 |
| Finished | Sep 09 10:26:05 PM UTC 24 |
| Peak memory | 231948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400161324 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.400161324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.2739890753 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 66654423 ps |
| CPU time | 5.31 seconds |
| Started | Sep 09 10:25:43 PM UTC 24 |
| Finished | Sep 09 10:25:49 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739890753 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2739890753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.3886188591 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 728478798 ps |
| CPU time | 26.67 seconds |
| Started | Sep 09 10:25:46 PM UTC 24 |
| Finished | Sep 09 10:26:14 PM UTC 24 |
| Peak memory | 258488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886188591 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3886188591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.1982706285 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 680144254 ps |
| CPU time | 13.02 seconds |
| Started | Sep 09 10:25:47 PM UTC 24 |
| Finished | Sep 09 10:26:02 PM UTC 24 |
| Peak memory | 262572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982706285 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1982706285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.2316708624 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 6136166548 ps |
| CPU time | 60.63 seconds |
| Started | Sep 09 10:26:03 PM UTC 24 |
| Finished | Sep 09 10:27:05 PM UTC 24 |
| Peak memory | 289168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2316708624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 5.lc_ctrl_stress_all.2316708624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.4253569450 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 3197903971 ps |
| CPU time | 76.35 seconds |
| Started | Sep 09 10:26:04 PM UTC 24 |
| Finished | Sep 09 10:27:22 PM UTC 24 |
| Peak memory | 263112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253569450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.4253569450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3504381506 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 18780936 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 10:25:45 PM UTC 24 |
| Finished | Sep 09 10:25:47 PM UTC 24 |
| Peak memory | 218232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504381506 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5. lc_ctrl_volatile_unlock_smoke.3504381506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.1508304330 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 36975480 ps |
| CPU time | 1.5 seconds |
| Started | Sep 09 10:26:25 PM UTC 24 |
| Finished | Sep 09 10:26:27 PM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508304330 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1508304330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.2377126778 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 42360897 ps |
| CPU time | 1.28 seconds |
| Started | Sep 09 10:26:11 PM UTC 24 |
| Finished | Sep 09 10:26:14 PM UTC 24 |
| Peak memory | 216960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377126778 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2377126778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.490368307 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 677019245 ps |
| CPU time | 12.97 seconds |
| Started | Sep 09 10:26:10 PM UTC 24 |
| Finished | Sep 09 10:26:24 PM UTC 24 |
| Peak memory | 237628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490368307 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.490368307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.3602508843 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1656646888 ps |
| CPU time | 11.5 seconds |
| Started | Sep 09 10:26:19 PM UTC 24 |
| Finished | Sep 09 10:26:32 PM UTC 24 |
| Peak memory | 229528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602508843 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3602508843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.3345942521 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 7859575119 ps |
| CPU time | 46.91 seconds |
| Started | Sep 09 10:26:19 PM UTC 24 |
| Finished | Sep 09 10:27:08 PM UTC 24 |
| Peak memory | 237916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345942521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jt ag_errors.3345942521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.581678044 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 119247003 ps |
| CPU time | 4.54 seconds |
| Started | Sep 09 10:26:20 PM UTC 24 |
| Finished | Sep 09 10:26:26 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581678044 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.581678044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.3357909096 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2901415109 ps |
| CPU time | 12.55 seconds |
| Started | Sep 09 10:26:16 PM UTC 24 |
| Finished | Sep 09 10:26:30 PM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357909096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl _jtag_prog_failure.3357909096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.919198624 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 15014931896 ps |
| CPU time | 31.3 seconds |
| Started | Sep 09 10:26:21 PM UTC 24 |
| Finished | Sep 09 10:26:53 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919198624 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_c trl_jtag_regwen_during_op.919198624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.3928849638 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 908685272 ps |
| CPU time | 6.89 seconds |
| Started | Sep 09 10:26:13 PM UTC 24 |
| Finished | Sep 09 10:26:21 PM UTC 24 |
| Peak memory | 229564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928849638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_s moke.3928849638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.1640892668 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 2801456538 ps |
| CPU time | 49.49 seconds |
| Started | Sep 09 10:26:14 PM UTC 24 |
| Finished | Sep 09 10:27:05 PM UTC 24 |
| Peak memory | 262488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640892668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr l_jtag_state_failure.1640892668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.4265739515 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 314465819 ps |
| CPU time | 11.83 seconds |
| Started | Sep 09 10:26:15 PM UTC 24 |
| Finished | Sep 09 10:26:28 PM UTC 24 |
| Peak memory | 260316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265739515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ ctrl_jtag_state_post_trans.4265739515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.3502262835 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 98786052 ps |
| CPU time | 2.54 seconds |
| Started | Sep 09 10:26:09 PM UTC 24 |
| Finished | Sep 09 10:26:13 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502262835 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3502262835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.2068131639 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 364066754 ps |
| CPU time | 20.95 seconds |
| Started | Sep 09 10:26:11 PM UTC 24 |
| Finished | Sep 09 10:26:34 PM UTC 24 |
| Peak memory | 225804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068131639 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2068131639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.823288231 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 712140400 ps |
| CPU time | 14.25 seconds |
| Started | Sep 09 10:26:22 PM UTC 24 |
| Finished | Sep 09 10:26:37 PM UTC 24 |
| Peak memory | 231600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823288231 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.823288231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2340998938 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 441919131 ps |
| CPU time | 17.22 seconds |
| Started | Sep 09 10:26:22 PM UTC 24 |
| Finished | Sep 09 10:26:41 PM UTC 24 |
| Peak memory | 237848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340998938 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_tok en_digest.2340998938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.1515207809 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 352060198 ps |
| CPU time | 8.92 seconds |
| Started | Sep 09 10:26:22 PM UTC 24 |
| Finished | Sep 09 10:26:32 PM UTC 24 |
| Peak memory | 237592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515207809 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_ mux.1515207809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.2315263169 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1141137887 ps |
| CPU time | 9.62 seconds |
| Started | Sep 09 10:26:10 PM UTC 24 |
| Finished | Sep 09 10:26:21 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315263169 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2315263169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.4038816404 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 90739407 ps |
| CPU time | 4.52 seconds |
| Started | Sep 09 10:26:05 PM UTC 24 |
| Finished | Sep 09 10:26:11 PM UTC 24 |
| Peak memory | 230004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038816404 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.4038816404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.2823655719 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1026211292 ps |
| CPU time | 20.35 seconds |
| Started | Sep 09 10:26:08 PM UTC 24 |
| Finished | Sep 09 10:26:29 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823655719 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2823655719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.3485387674 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 239729319 ps |
| CPU time | 9.1 seconds |
| Started | Sep 09 10:26:08 PM UTC 24 |
| Finished | Sep 09 10:26:18 PM UTC 24 |
| Peak memory | 260460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485387674 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3485387674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.171241261 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 16163353144 ps |
| CPU time | 32.86 seconds |
| Started | Sep 09 10:26:22 PM UTC 24 |
| Finished | Sep 09 10:26:56 PM UTC 24 |
| Peak memory | 262568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=171241261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 6.lc_ctrl_stress_all.171241261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1973465974 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2830295504 ps |
| CPU time | 67.64 seconds |
| Started | Sep 09 10:26:22 PM UTC 24 |
| Finished | Sep 09 10:27:32 PM UTC 24 |
| Peak memory | 272928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973465974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.1973465974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1559157330 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 14943982 ps |
| CPU time | 1.58 seconds |
| Started | Sep 09 10:26:07 PM UTC 24 |
| Finished | Sep 09 10:26:09 PM UTC 24 |
| Peak memory | 222388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559157330 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6. lc_ctrl_volatile_unlock_smoke.1559157330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.3620565034 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 16509699 ps |
| CPU time | 1.13 seconds |
| Started | Sep 09 10:26:52 PM UTC 24 |
| Finished | Sep 09 10:26:54 PM UTC 24 |
| Peak memory | 218524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620565034 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3620565034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.575096448 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 41659392 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 10:26:33 PM UTC 24 |
| Finished | Sep 09 10:26:35 PM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575096448 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.575096448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.2873338093 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1771981746 ps |
| CPU time | 26.33 seconds |
| Started | Sep 09 10:26:29 PM UTC 24 |
| Finished | Sep 09 10:26:57 PM UTC 24 |
| Peak memory | 231556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873338093 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2873338093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.3028804697 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 357661301 ps |
| CPU time | 8.65 seconds |
| Started | Sep 09 10:26:37 PM UTC 24 |
| Finished | Sep 09 10:26:47 PM UTC 24 |
| Peak memory | 229608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028804697 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3028804697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.1194432036 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 16507894354 ps |
| CPU time | 58.79 seconds |
| Started | Sep 09 10:26:37 PM UTC 24 |
| Finished | Sep 09 10:27:38 PM UTC 24 |
| Peak memory | 237788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194432036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jt ag_errors.1194432036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.3833557319 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1482961419 ps |
| CPU time | 16.76 seconds |
| Started | Sep 09 10:26:37 PM UTC 24 |
| Finished | Sep 09 10:26:55 PM UTC 24 |
| Peak memory | 229964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833557319 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_prior ity.3833557319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.3151833643 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 708713181 ps |
| CPU time | 3.48 seconds |
| Started | Sep 09 10:26:36 PM UTC 24 |
| Finished | Sep 09 10:26:41 PM UTC 24 |
| Peak memory | 231928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151833643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl _jtag_prog_failure.3151833643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2062681135 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 18962033454 ps |
| CPU time | 34 seconds |
| Started | Sep 09 10:26:39 PM UTC 24 |
| Finished | Sep 09 10:27:14 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062681135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ ctrl_jtag_regwen_during_op.2062681135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.1616196305 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2483303479 ps |
| CPU time | 7.94 seconds |
| Started | Sep 09 10:26:33 PM UTC 24 |
| Finished | Sep 09 10:26:42 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616196305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_s moke.1616196305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.3763920304 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 3505137987 ps |
| CPU time | 69.88 seconds |
| Started | Sep 09 10:26:35 PM UTC 24 |
| Finished | Sep 09 10:27:46 PM UTC 24 |
| Peak memory | 283304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763920304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr l_jtag_state_failure.3763920304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.3505909271 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3726609882 ps |
| CPU time | 17.15 seconds |
| Started | Sep 09 10:26:35 PM UTC 24 |
| Finished | Sep 09 10:26:53 PM UTC 24 |
| Peak memory | 258400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505909271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ ctrl_jtag_state_post_trans.3505909271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.3741554157 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 244303668 ps |
| CPU time | 3.75 seconds |
| Started | Sep 09 10:26:29 PM UTC 24 |
| Finished | Sep 09 10:26:34 PM UTC 24 |
| Peak memory | 235696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741554157 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3741554157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.1367324460 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 707112017 ps |
| CPU time | 20.05 seconds |
| Started | Sep 09 10:26:30 PM UTC 24 |
| Finished | Sep 09 10:26:52 PM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367324460 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1367324460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.1090874708 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1676249547 ps |
| CPU time | 17.41 seconds |
| Started | Sep 09 10:26:40 PM UTC 24 |
| Finished | Sep 09 10:26:58 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090874708 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1090874708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.2016643214 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1268066326 ps |
| CPU time | 16.56 seconds |
| Started | Sep 09 10:26:41 PM UTC 24 |
| Finished | Sep 09 10:26:59 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016643214 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_tok en_digest.2016643214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.1448056992 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1730544636 ps |
| CPU time | 13.19 seconds |
| Started | Sep 09 10:26:41 PM UTC 24 |
| Finished | Sep 09 10:26:55 PM UTC 24 |
| Peak memory | 237672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448056992 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_ mux.1448056992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.367904434 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 569623614 ps |
| CPU time | 18.89 seconds |
| Started | Sep 09 10:26:30 PM UTC 24 |
| Finished | Sep 09 10:26:51 PM UTC 24 |
| Peak memory | 232208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367904434 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.367904434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3641567021 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 157521365 ps |
| CPU time | 10.3 seconds |
| Started | Sep 09 10:26:25 PM UTC 24 |
| Finished | Sep 09 10:26:36 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641567021 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3641567021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.589364329 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 618471860 ps |
| CPU time | 30.67 seconds |
| Started | Sep 09 10:26:27 PM UTC 24 |
| Finished | Sep 09 10:26:59 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589364329 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.589364329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3146456879 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 182473452 ps |
| CPU time | 10.01 seconds |
| Started | Sep 09 10:26:28 PM UTC 24 |
| Finished | Sep 09 10:26:39 PM UTC 24 |
| Peak memory | 256744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146456879 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3146456879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.751528002 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 9203094532 ps |
| CPU time | 218.97 seconds |
| Started | Sep 09 10:26:42 PM UTC 24 |
| Finished | Sep 09 10:30:25 PM UTC 24 |
| Peak memory | 281064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=751528002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 7.lc_ctrl_stress_all.751528002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1424822494 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 15098753 ps |
| CPU time | 1.07 seconds |
| Started | Sep 09 10:26:26 PM UTC 24 |
| Finished | Sep 09 10:26:28 PM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424822494 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7. lc_ctrl_volatile_unlock_smoke.1424822494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.423394819 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 16712023 ps |
| CPU time | 1.28 seconds |
| Started | Sep 09 10:27:07 PM UTC 24 |
| Finished | Sep 09 10:27:09 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423394819 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.423394819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.1529475391 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2012001112 ps |
| CPU time | 14.59 seconds |
| Started | Sep 09 10:26:54 PM UTC 24 |
| Finished | Sep 09 10:27:10 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529475391 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1529475391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.3008960596 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 851148787 ps |
| CPU time | 4.24 seconds |
| Started | Sep 09 10:27:00 PM UTC 24 |
| Finished | Sep 09 10:27:05 PM UTC 24 |
| Peak memory | 229892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008960596 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3008960596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.2611743956 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 45321843267 ps |
| CPU time | 105.65 seconds |
| Started | Sep 09 10:27:00 PM UTC 24 |
| Finished | Sep 09 10:28:48 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611743956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jt ag_errors.2611743956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.1803468268 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 848269460 ps |
| CPU time | 6.54 seconds |
| Started | Sep 09 10:27:00 PM UTC 24 |
| Finished | Sep 09 10:27:08 PM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803468268 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_prior ity.1803468268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.3151337642 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 67539453 ps |
| CPU time | 3.09 seconds |
| Started | Sep 09 10:26:58 PM UTC 24 |
| Finished | Sep 09 10:27:02 PM UTC 24 |
| Peak memory | 231804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151337642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl _jtag_prog_failure.3151337642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2556441507 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2880629947 ps |
| CPU time | 26.66 seconds |
| Started | Sep 09 10:27:00 PM UTC 24 |
| Finished | Sep 09 10:27:28 PM UTC 24 |
| Peak memory | 229632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556441507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ ctrl_jtag_regwen_during_op.2556441507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.767337443 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 755866463 ps |
| CPU time | 6.43 seconds |
| Started | Sep 09 10:26:57 PM UTC 24 |
| Finished | Sep 09 10:27:04 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767337443 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_sm oke.767337443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.525299780 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2783883551 ps |
| CPU time | 51.6 seconds |
| Started | Sep 09 10:26:57 PM UTC 24 |
| Finished | Sep 09 10:27:50 PM UTC 24 |
| Peak memory | 282980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525299780 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl _jtag_state_failure.525299780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3106655008 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 607447020 ps |
| CPU time | 19.93 seconds |
| Started | Sep 09 10:26:58 PM UTC 24 |
| Finished | Sep 09 10:27:19 PM UTC 24 |
| Peak memory | 258412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106655008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ ctrl_jtag_state_post_trans.3106655008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.1202402473 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 156762306 ps |
| CPU time | 2.83 seconds |
| Started | Sep 09 10:26:54 PM UTC 24 |
| Finished | Sep 09 10:26:58 PM UTC 24 |
| Peak memory | 233992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202402473 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1202402473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.1616981180 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 821171485 ps |
| CPU time | 15.6 seconds |
| Started | Sep 09 10:26:56 PM UTC 24 |
| Finished | Sep 09 10:27:12 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616981180 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1616981180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3083083948 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 365136160 ps |
| CPU time | 13.02 seconds |
| Started | Sep 09 10:27:00 PM UTC 24 |
| Finished | Sep 09 10:27:14 PM UTC 24 |
| Peak memory | 232084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083083948 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3083083948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.3371038088 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 704291588 ps |
| CPU time | 15.24 seconds |
| Started | Sep 09 10:27:05 PM UTC 24 |
| Finished | Sep 09 10:27:22 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371038088 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_tok en_digest.3371038088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.827444839 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1058802930 ps |
| CPU time | 10.68 seconds |
| Started | Sep 09 10:27:03 PM UTC 24 |
| Finished | Sep 09 10:27:15 PM UTC 24 |
| Peak memory | 237604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827444839 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.827444839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.2844244158 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1118661709 ps |
| CPU time | 12.26 seconds |
| Started | Sep 09 10:26:54 PM UTC 24 |
| Finished | Sep 09 10:27:08 PM UTC 24 |
| Peak memory | 231896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844244158 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2844244158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.216080160 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 25011977 ps |
| CPU time | 2.49 seconds |
| Started | Sep 09 10:26:52 PM UTC 24 |
| Finished | Sep 09 10:26:55 PM UTC 24 |
| Peak memory | 225476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216080160 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.216080160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.1905474657 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 206168290 ps |
| CPU time | 26.51 seconds |
| Started | Sep 09 10:26:53 PM UTC 24 |
| Finished | Sep 09 10:27:21 PM UTC 24 |
| Peak memory | 262584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905474657 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1905474657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.3040786722 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 197468724 ps |
| CPU time | 9.52 seconds |
| Started | Sep 09 10:26:54 PM UTC 24 |
| Finished | Sep 09 10:27:05 PM UTC 24 |
| Peak memory | 262508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040786722 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3040786722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.782810004 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 30514887207 ps |
| CPU time | 154.38 seconds |
| Started | Sep 09 10:27:05 PM UTC 24 |
| Finished | Sep 09 10:29:42 PM UTC 24 |
| Peak memory | 272796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=782810004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 8.lc_ctrl_stress_all.782810004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3679842807 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 44313322 ps |
| CPU time | 1.32 seconds |
| Started | Sep 09 10:26:52 PM UTC 24 |
| Finished | Sep 09 10:26:54 PM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679842807 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8. lc_ctrl_volatile_unlock_smoke.3679842807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.817958483 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 21301560 ps |
| CPU time | 1.36 seconds |
| Started | Sep 09 10:27:26 PM UTC 24 |
| Finished | Sep 09 10:27:29 PM UTC 24 |
| Peak memory | 219124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817958483 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.817958483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.549768880 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 656373019 ps |
| CPU time | 12.87 seconds |
| Started | Sep 09 10:27:11 PM UTC 24 |
| Finished | Sep 09 10:27:25 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549768880 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.549768880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3567953978 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 455134514 ps |
| CPU time | 13.72 seconds |
| Started | Sep 09 10:27:17 PM UTC 24 |
| Finished | Sep 09 10:27:32 PM UTC 24 |
| Peak memory | 229592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567953978 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3567953978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.3547455335 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 1353876778 ps |
| CPU time | 36.59 seconds |
| Started | Sep 09 10:27:17 PM UTC 24 |
| Finished | Sep 09 10:27:55 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547455335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jt ag_errors.3547455335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.1160376357 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 100862840 ps |
| CPU time | 4.64 seconds |
| Started | Sep 09 10:27:20 PM UTC 24 |
| Finished | Sep 09 10:27:26 PM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160376357 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_prior ity.1160376357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.2844639050 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 202707215 ps |
| CPU time | 7.06 seconds |
| Started | Sep 09 10:27:16 PM UTC 24 |
| Finished | Sep 09 10:27:24 PM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844639050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl _jtag_prog_failure.2844639050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.523075135 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4152716467 ps |
| CPU time | 33.91 seconds |
| Started | Sep 09 10:27:21 PM UTC 24 |
| Finished | Sep 09 10:27:56 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523075135 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_c trl_jtag_regwen_during_op.523075135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.2598317620 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1149859841 ps |
| CPU time | 12.04 seconds |
| Started | Sep 09 10:27:15 PM UTC 24 |
| Finished | Sep 09 10:27:29 PM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598317620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_s moke.2598317620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.212194022 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 14304046574 ps |
| CPU time | 66.31 seconds |
| Started | Sep 09 10:27:16 PM UTC 24 |
| Finished | Sep 09 10:28:23 PM UTC 24 |
| Peak memory | 291504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212194022 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl _jtag_state_failure.212194022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1883337770 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1958648834 ps |
| CPU time | 22.06 seconds |
| Started | Sep 09 10:27:16 PM UTC 24 |
| Finished | Sep 09 10:27:39 PM UTC 24 |
| Peak memory | 262452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883337770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ ctrl_jtag_state_post_trans.1883337770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.20414127 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 75053767 ps |
| CPU time | 4.31 seconds |
| Started | Sep 09 10:27:11 PM UTC 24 |
| Finished | Sep 09 10:27:16 PM UTC 24 |
| Peak memory | 236052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20414127 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.20414127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.3639033829 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 162422541 ps |
| CPU time | 9.44 seconds |
| Started | Sep 09 10:27:11 PM UTC 24 |
| Finished | Sep 09 10:27:21 PM UTC 24 |
| Peak memory | 235924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639033829 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3639033829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.2455937503 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 199145642 ps |
| CPU time | 15 seconds |
| Started | Sep 09 10:27:22 PM UTC 24 |
| Finished | Sep 09 10:27:39 PM UTC 24 |
| Peak memory | 237596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455937503 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2455937503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2605885148 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 920412226 ps |
| CPU time | 21.36 seconds |
| Started | Sep 09 10:27:23 PM UTC 24 |
| Finished | Sep 09 10:27:45 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605885148 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_tok en_digest.2605885148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.822812009 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1099497808 ps |
| CPU time | 11.45 seconds |
| Started | Sep 09 10:27:22 PM UTC 24 |
| Finished | Sep 09 10:27:35 PM UTC 24 |
| Peak memory | 237596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822812009 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.822812009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.1972540354 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 676651034 ps |
| CPU time | 19.35 seconds |
| Started | Sep 09 10:27:11 PM UTC 24 |
| Finished | Sep 09 10:27:31 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972540354 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1972540354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.1052368710 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 25086662 ps |
| CPU time | 2.3 seconds |
| Started | Sep 09 10:27:07 PM UTC 24 |
| Finished | Sep 09 10:27:10 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052368710 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1052368710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.4219179002 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 219966152 ps |
| CPU time | 25.25 seconds |
| Started | Sep 09 10:27:08 PM UTC 24 |
| Finished | Sep 09 10:27:35 PM UTC 24 |
| Peak memory | 262496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219179002 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.4219179002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.3940822665 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 209140442 ps |
| CPU time | 9.99 seconds |
| Started | Sep 09 10:27:09 PM UTC 24 |
| Finished | Sep 09 10:27:20 PM UTC 24 |
| Peak memory | 262488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940822665 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3940822665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.2108044050 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 15471000750 ps |
| CPU time | 311.39 seconds |
| Started | Sep 09 10:27:24 PM UTC 24 |
| Finished | Sep 09 10:32:39 PM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2108044050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 9.lc_ctrl_stress_all.2108044050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1405717486 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 7580300242 ps |
| CPU time | 77.07 seconds |
| Started | Sep 09 10:27:25 PM UTC 24 |
| Finished | Sep 09 10:28:44 PM UTC 24 |
| Peak memory | 263232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405717486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.1405717486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1047104110 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 32428501 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 10:27:08 PM UTC 24 |
| Finished | Sep 09 10:27:10 PM UTC 24 |
| Peak memory | 218292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047104110 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9. lc_ctrl_volatile_unlock_smoke.1047104110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_volatile_unlock_smoke/latest |
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