| T816 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.2738615260 |
|
|
Sep 09 10:35:02 PM UTC 24 |
Sep 09 10:35:06 PM UTC 24 |
219852496 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.891249194 |
|
|
Sep 09 10:35:02 PM UTC 24 |
Sep 09 10:35:10 PM UTC 24 |
757112151 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.13823975 |
|
|
Sep 09 10:34:56 PM UTC 24 |
Sep 09 10:35:10 PM UTC 24 |
447922031 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.954708508 |
|
|
Sep 09 10:34:56 PM UTC 24 |
Sep 09 10:35:11 PM UTC 24 |
1126822600 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.3706733219 |
|
|
Sep 09 10:35:03 PM UTC 24 |
Sep 09 10:35:11 PM UTC 24 |
360644960 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.1596622584 |
|
|
Sep 09 10:35:00 PM UTC 24 |
Sep 09 10:35:11 PM UTC 24 |
158940376 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.3530948241 |
|
|
Sep 09 10:34:54 PM UTC 24 |
Sep 09 10:35:11 PM UTC 24 |
526769395 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.2610718527 |
|
|
Sep 09 10:35:05 PM UTC 24 |
Sep 09 10:35:13 PM UTC 24 |
1163219059 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.3045219327 |
|
|
Sep 09 10:35:11 PM UTC 24 |
Sep 09 10:35:13 PM UTC 24 |
49408401 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.1696887584 |
|
|
Sep 09 10:34:35 PM UTC 24 |
Sep 09 10:35:15 PM UTC 24 |
325824062 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.1381674589 |
|
|
Sep 09 10:34:51 PM UTC 24 |
Sep 09 10:35:15 PM UTC 24 |
1405701173 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.4028434178 |
|
|
Sep 09 10:35:26 PM UTC 24 |
Sep 09 10:35:41 PM UTC 24 |
531540018 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3792323667 |
|
|
Sep 09 10:35:13 PM UTC 24 |
Sep 09 10:35:15 PM UTC 24 |
16812009 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.3348051536 |
|
|
Sep 09 10:34:45 PM UTC 24 |
Sep 09 10:35:16 PM UTC 24 |
356283029 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.3093106222 |
|
|
Sep 09 10:35:13 PM UTC 24 |
Sep 09 10:35:16 PM UTC 24 |
27614459 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.3684195248 |
|
|
Sep 09 10:35:11 PM UTC 24 |
Sep 09 10:35:18 PM UTC 24 |
93577150 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.2245747112 |
|
|
Sep 09 10:35:26 PM UTC 24 |
Sep 09 10:35:43 PM UTC 24 |
697314600 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.2838541956 |
|
|
Sep 09 10:34:54 PM UTC 24 |
Sep 09 10:35:20 PM UTC 24 |
5774686188 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.1975267017 |
|
|
Sep 09 10:35:02 PM UTC 24 |
Sep 09 10:35:21 PM UTC 24 |
364109456 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.264725844 |
|
|
Sep 09 10:34:52 PM UTC 24 |
Sep 09 10:35:21 PM UTC 24 |
290757347 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.1425139959 |
|
|
Sep 09 10:35:19 PM UTC 24 |
Sep 09 10:35:21 PM UTC 24 |
29477398 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1399112119 |
|
|
Sep 09 10:35:21 PM UTC 24 |
Sep 09 10:35:23 PM UTC 24 |
20257393 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.360161756 |
|
|
Sep 09 10:35:21 PM UTC 24 |
Sep 09 10:35:23 PM UTC 24 |
17023646 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.3303449815 |
|
|
Sep 09 10:35:04 PM UTC 24 |
Sep 09 10:35:24 PM UTC 24 |
2477270239 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.1309169568 |
|
|
Sep 09 10:32:59 PM UTC 24 |
Sep 09 10:35:24 PM UTC 24 |
60021421520 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.1429620705 |
|
|
Sep 09 10:35:13 PM UTC 24 |
Sep 09 10:35:25 PM UTC 24 |
418243651 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.3212548056 |
|
|
Sep 09 10:35:23 PM UTC 24 |
Sep 09 10:35:44 PM UTC 24 |
241974490 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.1046022003 |
|
|
Sep 09 10:35:23 PM UTC 24 |
Sep 09 10:35:27 PM UTC 24 |
181140765 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.879376738 |
|
|
Sep 09 10:34:56 PM UTC 24 |
Sep 09 10:35:27 PM UTC 24 |
3027713382 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.567778623 |
|
|
Sep 09 10:35:06 PM UTC 24 |
Sep 09 10:35:28 PM UTC 24 |
1596917248 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.1701707825 |
|
|
Sep 09 10:35:18 PM UTC 24 |
Sep 09 10:35:28 PM UTC 24 |
198236041 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.1002490854 |
|
|
Sep 09 10:35:23 PM UTC 24 |
Sep 09 10:35:29 PM UTC 24 |
69577472 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.2705897112 |
|
|
Sep 09 10:30:16 PM UTC 24 |
Sep 09 10:35:30 PM UTC 24 |
10397272855 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.4199501354 |
|
|
Sep 09 10:35:28 PM UTC 24 |
Sep 09 10:35:31 PM UTC 24 |
12437194 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.638315268 |
|
|
Sep 09 10:35:14 PM UTC 24 |
Sep 09 10:35:31 PM UTC 24 |
245232470 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.315566235 |
|
|
Sep 09 10:35:14 PM UTC 24 |
Sep 09 10:35:32 PM UTC 24 |
1691226338 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.2370131595 |
|
|
Sep 09 10:35:18 PM UTC 24 |
Sep 09 10:35:32 PM UTC 24 |
415962071 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.128056505 |
|
|
Sep 09 10:35:00 PM UTC 24 |
Sep 09 10:35:33 PM UTC 24 |
819693512 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.4225713361 |
|
|
Sep 09 10:35:16 PM UTC 24 |
Sep 09 10:35:34 PM UTC 24 |
1028242600 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.2713478979 |
|
|
Sep 09 10:34:00 PM UTC 24 |
Sep 09 10:35:36 PM UTC 24 |
2008901962 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.1369687504 |
|
|
Sep 09 10:35:26 PM UTC 24 |
Sep 09 10:35:37 PM UTC 24 |
796942583 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.5013013 |
|
|
Sep 09 10:35:23 PM UTC 24 |
Sep 09 10:35:38 PM UTC 24 |
330303843 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.4235077679 |
|
|
Sep 09 10:35:13 PM UTC 24 |
Sep 09 10:35:38 PM UTC 24 |
720579610 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.3497417646 |
|
|
Sep 09 10:34:21 PM UTC 24 |
Sep 09 10:35:39 PM UTC 24 |
1800208136 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.845520597 |
|
|
Sep 09 10:35:24 PM UTC 24 |
Sep 09 10:35:40 PM UTC 24 |
353476512 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.2506777933 |
|
|
Sep 09 10:35:16 PM UTC 24 |
Sep 09 10:35:45 PM UTC 24 |
2711356714 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.2028067162 |
|
|
Sep 09 10:35:26 PM UTC 24 |
Sep 09 10:35:51 PM UTC 24 |
1116296246 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.3821223167 |
|
|
Sep 09 10:33:40 PM UTC 24 |
Sep 09 10:35:52 PM UTC 24 |
14248508038 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.3894001114 |
|
|
Sep 09 10:34:42 PM UTC 24 |
Sep 09 10:36:00 PM UTC 24 |
3642773848 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.3537890529 |
|
|
Sep 09 10:35:28 PM UTC 24 |
Sep 09 10:36:08 PM UTC 24 |
907899526 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.4089723111 |
|
|
Sep 09 10:35:28 PM UTC 24 |
Sep 09 10:36:14 PM UTC 24 |
6820887194 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.2533920816 |
|
|
Sep 09 10:32:14 PM UTC 24 |
Sep 09 10:36:14 PM UTC 24 |
45371798805 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.2201285171 |
|
|
Sep 09 10:34:56 PM UTC 24 |
Sep 09 10:36:23 PM UTC 24 |
11817221648 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.1732322998 |
|
|
Sep 09 10:33:22 PM UTC 24 |
Sep 09 10:36:38 PM UTC 24 |
7607677279 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.1249803345 |
|
|
Sep 09 10:33:16 PM UTC 24 |
Sep 09 10:36:39 PM UTC 24 |
22979962076 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.2777906347 |
|
|
Sep 09 10:35:07 PM UTC 24 |
Sep 09 10:36:40 PM UTC 24 |
4586902863 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.4143751005 |
|
|
Sep 09 10:34:21 PM UTC 24 |
Sep 09 10:36:44 PM UTC 24 |
11329875258 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.4279654933 |
|
|
Sep 09 10:33:31 PM UTC 24 |
Sep 09 10:36:56 PM UTC 24 |
7464559730 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.1040539377 |
|
|
Sep 09 10:34:51 PM UTC 24 |
Sep 09 10:37:06 PM UTC 24 |
21819627942 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.1294535956 |
|
|
Sep 09 10:32:33 PM UTC 24 |
Sep 09 10:37:07 PM UTC 24 |
56166969577 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1216293315 |
|
|
Sep 09 10:35:18 PM UTC 24 |
Sep 09 10:37:08 PM UTC 24 |
6620476873 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.2177231105 |
|
|
Sep 09 10:35:18 PM UTC 24 |
Sep 09 10:37:38 PM UTC 24 |
26060389256 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.2990893740 |
|
|
Sep 09 10:34:29 PM UTC 24 |
Sep 09 10:39:06 PM UTC 24 |
15869902604 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.2883663626 |
|
|
Sep 09 10:31:46 PM UTC 24 |
Sep 09 10:40:17 PM UTC 24 |
54481423924 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.3067508849 |
|
|
Sep 09 10:35:07 PM UTC 24 |
Sep 09 10:40:20 PM UTC 24 |
19876921451 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.424490932 |
|
|
Sep 09 10:30:36 PM UTC 24 |
Sep 09 10:40:26 PM UTC 24 |
236256339229 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4107327132 |
|
|
Sep 09 09:09:38 PM UTC 24 |
Sep 09 09:09:42 PM UTC 24 |
225501146 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.736654048 |
|
|
Sep 09 09:09:38 PM UTC 24 |
Sep 09 09:09:42 PM UTC 24 |
314413914 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.959466660 |
|
|
Sep 09 09:09:40 PM UTC 24 |
Sep 09 09:09:43 PM UTC 24 |
104980396 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3327387916 |
|
|
Sep 09 09:09:41 PM UTC 24 |
Sep 09 09:09:43 PM UTC 24 |
17962306 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4228510263 |
|
|
Sep 09 09:09:41 PM UTC 24 |
Sep 09 09:09:43 PM UTC 24 |
36541435 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3258174275 |
|
|
Sep 09 09:09:41 PM UTC 24 |
Sep 09 09:09:43 PM UTC 24 |
79723492 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1390037643 |
|
|
Sep 09 09:09:41 PM UTC 24 |
Sep 09 09:09:43 PM UTC 24 |
16797810 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3915188627 |
|
|
Sep 09 09:09:39 PM UTC 24 |
Sep 09 09:09:44 PM UTC 24 |
347037137 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4187308837 |
|
|
Sep 09 09:09:40 PM UTC 24 |
Sep 09 09:09:44 PM UTC 24 |
117259508 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1299720577 |
|
|
Sep 09 09:09:42 PM UTC 24 |
Sep 09 09:09:44 PM UTC 24 |
175021293 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3085700182 |
|
|
Sep 09 09:09:41 PM UTC 24 |
Sep 09 09:09:45 PM UTC 24 |
120018235 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2758472750 |
|
|
Sep 09 09:09:42 PM UTC 24 |
Sep 09 09:09:45 PM UTC 24 |
47830596 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2274949496 |
|
|
Sep 09 09:09:38 PM UTC 24 |
Sep 09 09:09:45 PM UTC 24 |
1702127337 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1593482317 |
|
|
Sep 09 09:09:42 PM UTC 24 |
Sep 09 09:09:45 PM UTC 24 |
22716703 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2011817950 |
|
|
Sep 09 09:09:37 PM UTC 24 |
Sep 09 09:09:45 PM UTC 24 |
248320361 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1512854177 |
|
|
Sep 09 09:09:42 PM UTC 24 |
Sep 09 09:09:45 PM UTC 24 |
97630705 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1654440428 |
|
|
Sep 09 09:09:42 PM UTC 24 |
Sep 09 09:09:45 PM UTC 24 |
175866912 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3760954316 |
|
|
Sep 09 09:09:44 PM UTC 24 |
Sep 09 09:09:46 PM UTC 24 |
48735572 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3950820139 |
|
|
Sep 09 09:09:44 PM UTC 24 |
Sep 09 09:09:46 PM UTC 24 |
21127567 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4052557917 |
|
|
Sep 09 09:09:42 PM UTC 24 |
Sep 09 09:09:46 PM UTC 24 |
337210262 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2934702944 |
|
|
Sep 09 09:09:44 PM UTC 24 |
Sep 09 09:09:46 PM UTC 24 |
38165210 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.745285487 |
|
|
Sep 09 09:09:42 PM UTC 24 |
Sep 09 09:09:46 PM UTC 24 |
329342140 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2641978191 |
|
|
Sep 09 09:09:44 PM UTC 24 |
Sep 09 09:09:46 PM UTC 24 |
14881654 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3443869417 |
|
|
Sep 09 09:09:44 PM UTC 24 |
Sep 09 09:09:46 PM UTC 24 |
30474758 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.372205219 |
|
|
Sep 09 09:09:44 PM UTC 24 |
Sep 09 09:09:47 PM UTC 24 |
54464373 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1979986902 |
|
|
Sep 09 09:09:44 PM UTC 24 |
Sep 09 09:09:47 PM UTC 24 |
119121607 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2038985685 |
|
|
Sep 09 09:09:45 PM UTC 24 |
Sep 09 09:09:48 PM UTC 24 |
141481539 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3374581848 |
|
|
Sep 09 09:09:45 PM UTC 24 |
Sep 09 09:09:48 PM UTC 24 |
184643180 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1182592113 |
|
|
Sep 09 09:09:45 PM UTC 24 |
Sep 09 09:09:48 PM UTC 24 |
264140260 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2496934029 |
|
|
Sep 09 09:09:43 PM UTC 24 |
Sep 09 09:09:48 PM UTC 24 |
129067291 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2780495126 |
|
|
Sep 09 09:09:45 PM UTC 24 |
Sep 09 09:09:48 PM UTC 24 |
120691786 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1754036440 |
|
|
Sep 09 09:09:46 PM UTC 24 |
Sep 09 09:09:49 PM UTC 24 |
32862366 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.4048812554 |
|
|
Sep 09 09:09:46 PM UTC 24 |
Sep 09 09:09:49 PM UTC 24 |
14240873 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1838525966 |
|
|
Sep 09 09:09:47 PM UTC 24 |
Sep 09 09:09:49 PM UTC 24 |
53049695 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3695426054 |
|
|
Sep 09 09:09:46 PM UTC 24 |
Sep 09 09:09:49 PM UTC 24 |
142506033 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2328535120 |
|
|
Sep 09 09:09:47 PM UTC 24 |
Sep 09 09:09:49 PM UTC 24 |
78278052 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1170871192 |
|
|
Sep 09 09:09:47 PM UTC 24 |
Sep 09 09:09:50 PM UTC 24 |
44479397 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3361259284 |
|
|
Sep 09 09:09:46 PM UTC 24 |
Sep 09 09:09:50 PM UTC 24 |
64861206 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2550492262 |
|
|
Sep 09 09:09:48 PM UTC 24 |
Sep 09 09:09:50 PM UTC 24 |
23839392 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.407307936 |
|
|
Sep 09 09:09:45 PM UTC 24 |
Sep 09 09:09:50 PM UTC 24 |
908874904 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.697096638 |
|
|
Sep 09 09:09:48 PM UTC 24 |
Sep 09 09:09:50 PM UTC 24 |
154465431 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1888263070 |
|
|
Sep 09 09:09:48 PM UTC 24 |
Sep 09 09:09:51 PM UTC 24 |
131479793 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.323440290 |
|
|
Sep 09 09:09:48 PM UTC 24 |
Sep 09 09:09:51 PM UTC 24 |
29975110 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3237746518 |
|
|
Sep 09 09:09:52 PM UTC 24 |
Sep 09 09:09:55 PM UTC 24 |
29072583 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1273815124 |
|
|
Sep 09 09:09:45 PM UTC 24 |
Sep 09 09:09:51 PM UTC 24 |
381165352 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2233295512 |
|
|
Sep 09 09:09:48 PM UTC 24 |
Sep 09 09:09:51 PM UTC 24 |
693114392 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.526274152 |
|
|
Sep 09 09:09:48 PM UTC 24 |
Sep 09 09:09:51 PM UTC 24 |
37778160 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.192826914 |
|
|
Sep 09 09:09:48 PM UTC 24 |
Sep 09 09:09:51 PM UTC 24 |
178186438 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1542966066 |
|
|
Sep 09 09:09:49 PM UTC 24 |
Sep 09 09:09:51 PM UTC 24 |
89028513 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3690703956 |
|
|
Sep 09 09:09:49 PM UTC 24 |
Sep 09 09:09:52 PM UTC 24 |
13519282 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3819483312 |
|
|
Sep 09 09:09:49 PM UTC 24 |
Sep 09 09:09:52 PM UTC 24 |
273369488 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3347978107 |
|
|
Sep 09 09:09:49 PM UTC 24 |
Sep 09 09:09:52 PM UTC 24 |
16099227 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4177262464 |
|
|
Sep 09 09:09:48 PM UTC 24 |
Sep 09 09:09:52 PM UTC 24 |
107943345 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2787242122 |
|
|
Sep 09 09:09:49 PM UTC 24 |
Sep 09 09:09:52 PM UTC 24 |
287837826 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2779948097 |
|
|
Sep 09 09:09:49 PM UTC 24 |
Sep 09 09:09:52 PM UTC 24 |
159794708 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4248046514 |
|
|
Sep 09 09:09:45 PM UTC 24 |
Sep 09 09:09:53 PM UTC 24 |
741337497 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4188255622 |
|
|
Sep 09 09:09:51 PM UTC 24 |
Sep 09 09:09:53 PM UTC 24 |
26276909 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3496255233 |
|
|
Sep 09 09:09:49 PM UTC 24 |
Sep 09 09:09:53 PM UTC 24 |
603580934 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3489767749 |
|
|
Sep 09 09:09:51 PM UTC 24 |
Sep 09 09:09:53 PM UTC 24 |
73426129 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3668148778 |
|
|
Sep 09 09:09:51 PM UTC 24 |
Sep 09 09:09:53 PM UTC 24 |
23981717 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1480087174 |
|
|
Sep 09 09:09:51 PM UTC 24 |
Sep 09 09:09:54 PM UTC 24 |
220963212 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1028074203 |
|
|
Sep 09 09:09:51 PM UTC 24 |
Sep 09 09:09:54 PM UTC 24 |
54566779 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.350982238 |
|
|
Sep 09 09:09:52 PM UTC 24 |
Sep 09 09:09:54 PM UTC 24 |
41175046 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1219576237 |
|
|
Sep 09 09:09:52 PM UTC 24 |
Sep 09 09:09:55 PM UTC 24 |
54619695 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3837601102 |
|
|
Sep 09 09:09:52 PM UTC 24 |
Sep 09 09:09:55 PM UTC 24 |
37635330 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3965277841 |
|
|
Sep 09 09:09:51 PM UTC 24 |
Sep 09 09:09:55 PM UTC 24 |
73929671 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1929804393 |
|
|
Sep 09 09:09:51 PM UTC 24 |
Sep 09 09:09:55 PM UTC 24 |
110942652 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2973985810 |
|
|
Sep 09 09:09:42 PM UTC 24 |
Sep 09 09:09:55 PM UTC 24 |
445281823 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2077703127 |
|
|
Sep 09 09:09:45 PM UTC 24 |
Sep 09 09:09:55 PM UTC 24 |
1401871638 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3836536246 |
|
|
Sep 09 09:09:52 PM UTC 24 |
Sep 09 09:09:55 PM UTC 24 |
36913237 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1120915479 |
|
|
Sep 09 09:09:52 PM UTC 24 |
Sep 09 09:09:56 PM UTC 24 |
746347909 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1049060593 |
|
|
Sep 09 09:09:48 PM UTC 24 |
Sep 09 09:09:56 PM UTC 24 |
901848780 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4098686816 |
|
|
Sep 09 09:09:54 PM UTC 24 |
Sep 09 09:09:56 PM UTC 24 |
41220882 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.916932765 |
|
|
Sep 09 09:09:54 PM UTC 24 |
Sep 09 09:09:56 PM UTC 24 |
88425285 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.626636594 |
|
|
Sep 09 09:09:52 PM UTC 24 |
Sep 09 09:09:56 PM UTC 24 |
129474313 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2650310412 |
|
|
Sep 09 09:09:52 PM UTC 24 |
Sep 09 09:09:57 PM UTC 24 |
493312616 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2172886383 |
|
|
Sep 09 09:09:54 PM UTC 24 |
Sep 09 09:09:57 PM UTC 24 |
76113263 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3676321185 |
|
|
Sep 09 09:09:50 PM UTC 24 |
Sep 09 09:09:57 PM UTC 24 |
1103459302 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.851727212 |
|
|
Sep 09 09:09:48 PM UTC 24 |
Sep 09 09:09:58 PM UTC 24 |
578797296 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2583716622 |
|
|
Sep 09 09:09:54 PM UTC 24 |
Sep 09 09:09:59 PM UTC 24 |
17730098 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4110482939 |
|
|
Sep 09 09:09:54 PM UTC 24 |
Sep 09 09:09:59 PM UTC 24 |
178434276 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2450514678 |
|
|
Sep 09 09:09:54 PM UTC 24 |
Sep 09 09:10:00 PM UTC 24 |
118215741 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3550225736 |
|
|
Sep 09 09:09:54 PM UTC 24 |
Sep 09 09:10:00 PM UTC 24 |
55169129 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.341663421 |
|
|
Sep 09 09:09:57 PM UTC 24 |
Sep 09 09:10:00 PM UTC 24 |
78463455 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.270207739 |
|
|
Sep 09 09:09:57 PM UTC 24 |
Sep 09 09:10:00 PM UTC 24 |
85478211 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1433826353 |
|
|
Sep 09 09:09:57 PM UTC 24 |
Sep 09 09:10:00 PM UTC 24 |
22815298 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4180073060 |
|
|
Sep 09 09:09:42 PM UTC 24 |
Sep 09 09:10:01 PM UTC 24 |
1598422433 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.824918100 |
|
|
Sep 09 09:09:57 PM UTC 24 |
Sep 09 09:10:01 PM UTC 24 |
359054855 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2207011412 |
|
|
Sep 09 09:09:50 PM UTC 24 |
Sep 09 09:10:01 PM UTC 24 |
1933179708 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.656122666 |
|
|
Sep 09 09:09:52 PM UTC 24 |
Sep 09 09:10:01 PM UTC 24 |
728917708 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.482659174 |
|
|
Sep 09 09:09:38 PM UTC 24 |
Sep 09 09:10:03 PM UTC 24 |
1227296289 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1777217746 |
|
|
Sep 09 09:09:55 PM UTC 24 |
Sep 09 09:10:04 PM UTC 24 |
15958064 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3607168881 |
|
|
Sep 09 09:09:55 PM UTC 24 |
Sep 09 09:10:05 PM UTC 24 |
235348994 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3790111593 |
|
|
Sep 09 09:09:55 PM UTC 24 |
Sep 09 09:10:05 PM UTC 24 |
75125652 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2899531394 |
|
|
Sep 09 09:10:01 PM UTC 24 |
Sep 09 09:10:05 PM UTC 24 |
150152229 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.557617431 |
|
|
Sep 09 09:10:01 PM UTC 24 |
Sep 09 09:10:06 PM UTC 24 |
41119979 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2245847441 |
|
|
Sep 09 09:10:00 PM UTC 24 |
Sep 09 09:10:09 PM UTC 24 |
39228574 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1563061236 |
|
|
Sep 09 09:09:57 PM UTC 24 |
Sep 09 09:10:10 PM UTC 24 |
16337569 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1617579261 |
|
|
Sep 09 09:09:57 PM UTC 24 |
Sep 09 09:10:10 PM UTC 24 |
38360776 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.178505020 |
|
|
Sep 09 09:10:05 PM UTC 24 |
Sep 09 09:10:10 PM UTC 24 |
36224966 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.676038378 |
|
|
Sep 09 09:10:07 PM UTC 24 |
Sep 09 09:10:10 PM UTC 24 |
40252283 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2112905952 |
|
|
Sep 09 09:10:00 PM UTC 24 |
Sep 09 09:10:10 PM UTC 24 |
51357169 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.416260306 |
|
|
Sep 09 09:10:08 PM UTC 24 |
Sep 09 09:10:10 PM UTC 24 |
20128342 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.873971409 |
|
|
Sep 09 09:10:17 PM UTC 24 |
Sep 09 09:10:20 PM UTC 24 |
13136985 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2108922237 |
|
|
Sep 09 09:09:57 PM UTC 24 |
Sep 09 09:10:10 PM UTC 24 |
704327135 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2826004681 |
|
|
Sep 09 09:09:58 PM UTC 24 |
Sep 09 09:10:10 PM UTC 24 |
92389505 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2064859991 |
|
|
Sep 09 09:09:58 PM UTC 24 |
Sep 09 09:10:10 PM UTC 24 |
80983199 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3243409905 |
|
|
Sep 09 09:10:00 PM UTC 24 |
Sep 09 09:10:11 PM UTC 24 |
64306135 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2071364118 |
|
|
Sep 09 09:09:55 PM UTC 24 |
Sep 09 09:10:11 PM UTC 24 |
1686986467 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1488521988 |
|
|
Sep 09 09:09:57 PM UTC 24 |
Sep 09 09:10:11 PM UTC 24 |
268259485 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3538901245 |
|
|
Sep 09 09:09:58 PM UTC 24 |
Sep 09 09:10:11 PM UTC 24 |
67240583 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3331420390 |
|
|
Sep 09 09:09:55 PM UTC 24 |
Sep 09 09:10:11 PM UTC 24 |
531399031 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1559550156 |
|
|
Sep 09 09:10:06 PM UTC 24 |
Sep 09 09:10:12 PM UTC 24 |
80540971 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1952363388 |
|
|
Sep 09 09:10:01 PM UTC 24 |
Sep 09 09:10:12 PM UTC 24 |
35461764 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3347797349 |
|
|
Sep 09 09:09:58 PM UTC 24 |
Sep 09 09:10:12 PM UTC 24 |
134268053 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3359502885 |
|
|
Sep 09 09:09:57 PM UTC 24 |
Sep 09 09:10:12 PM UTC 24 |
53879468 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1615137930 |
|
|
Sep 09 09:09:55 PM UTC 24 |
Sep 09 09:10:12 PM UTC 24 |
12538190 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.64163309 |
|
|
Sep 09 09:09:57 PM UTC 24 |
Sep 09 09:10:12 PM UTC 24 |
652948359 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1813304819 |
|
|
Sep 09 09:10:02 PM UTC 24 |
Sep 09 09:10:12 PM UTC 24 |
95247023 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3734011443 |
|
|
Sep 09 09:10:02 PM UTC 24 |
Sep 09 09:10:12 PM UTC 24 |
54160502 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2413934117 |
|
|
Sep 09 09:10:17 PM UTC 24 |
Sep 09 09:10:20 PM UTC 24 |
152463998 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1768250728 |
|
|
Sep 09 09:10:03 PM UTC 24 |
Sep 09 09:10:12 PM UTC 24 |
41470650 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3248739258 |
|
|
Sep 09 09:10:10 PM UTC 24 |
Sep 09 09:10:13 PM UTC 24 |
24857616 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.822148791 |
|
|
Sep 09 09:10:06 PM UTC 24 |
Sep 09 09:10:13 PM UTC 24 |
1408703109 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3816360473 |
|
|
Sep 09 09:09:55 PM UTC 24 |
Sep 09 09:10:13 PM UTC 24 |
836178283 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3729787399 |
|
|
Sep 09 09:10:06 PM UTC 24 |
Sep 09 09:10:13 PM UTC 24 |
149250147 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3659649216 |
|
|
Sep 09 09:10:03 PM UTC 24 |
Sep 09 09:10:13 PM UTC 24 |
323999424 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.460238257 |
|
|
Sep 09 09:10:06 PM UTC 24 |
Sep 09 09:10:13 PM UTC 24 |
108381892 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.454130865 |
|
|
Sep 09 09:10:10 PM UTC 24 |
Sep 09 09:10:14 PM UTC 24 |
27262407 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.802923715 |
|
|
Sep 09 09:09:57 PM UTC 24 |
Sep 09 09:10:14 PM UTC 24 |
2028738103 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4229422430 |
|
|
Sep 09 09:09:55 PM UTC 24 |
Sep 09 09:10:14 PM UTC 24 |
281975770 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2937970805 |
|
|
Sep 09 09:10:10 PM UTC 24 |
Sep 09 09:10:14 PM UTC 24 |
119169902 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1294089836 |
|
|
Sep 09 09:10:11 PM UTC 24 |
Sep 09 09:10:15 PM UTC 24 |
15660252 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.785070993 |
|
|
Sep 09 09:10:11 PM UTC 24 |
Sep 09 09:10:15 PM UTC 24 |
78054997 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.196116961 |
|
|
Sep 09 09:10:11 PM UTC 24 |
Sep 09 09:10:15 PM UTC 24 |
85220941 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2668591459 |
|
|
Sep 09 09:10:11 PM UTC 24 |
Sep 09 09:10:15 PM UTC 24 |
13794821 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2360120328 |
|
|
Sep 09 09:10:04 PM UTC 24 |
Sep 09 09:10:15 PM UTC 24 |
195528904 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2081921743 |
|
|
Sep 09 09:09:52 PM UTC 24 |
Sep 09 09:10:15 PM UTC 24 |
5639253170 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1600039256 |
|
|
Sep 09 09:10:12 PM UTC 24 |
Sep 09 09:10:15 PM UTC 24 |
85701746 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3470438131 |
|
|
Sep 09 09:09:55 PM UTC 24 |
Sep 09 09:10:15 PM UTC 24 |
141248664 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4045958554 |
|
|
Sep 09 09:09:59 PM UTC 24 |
Sep 09 09:10:16 PM UTC 24 |
1247363494 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3558061354 |
|
|
Sep 09 09:10:11 PM UTC 24 |
Sep 09 09:10:16 PM UTC 24 |
110378696 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1116143637 |
|
|
Sep 09 09:10:12 PM UTC 24 |
Sep 09 09:10:16 PM UTC 24 |
81981228 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1196105469 |
|
|
Sep 09 09:10:11 PM UTC 24 |
Sep 09 09:10:17 PM UTC 24 |
185254751 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2232010858 |
|
|
Sep 09 09:10:00 PM UTC 24 |
Sep 09 09:10:18 PM UTC 24 |
374474464 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1033272713 |
|
|
Sep 09 09:09:57 PM UTC 24 |
Sep 09 09:10:19 PM UTC 24 |
3826510580 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3559342911 |
|
|
Sep 09 09:10:14 PM UTC 24 |
Sep 09 09:10:19 PM UTC 24 |
35228095 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.269351954 |
|
|
Sep 09 09:10:14 PM UTC 24 |
Sep 09 09:10:20 PM UTC 24 |
19335803 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1090451826 |
|
|
Sep 09 09:10:14 PM UTC 24 |
Sep 09 09:10:20 PM UTC 24 |
51008181 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3142305807 |
|
|
Sep 09 09:10:14 PM UTC 24 |
Sep 09 09:10:20 PM UTC 24 |
25391524 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2333630559 |
|
|
Sep 09 09:10:14 PM UTC 24 |
Sep 09 09:10:20 PM UTC 24 |
110446049 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2640589885 |
|
|
Sep 09 09:10:17 PM UTC 24 |
Sep 09 09:10:20 PM UTC 24 |
148469572 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1971965323 |
|
|
Sep 09 09:10:14 PM UTC 24 |
Sep 09 09:10:21 PM UTC 24 |
56891731 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.745325457 |
|
|
Sep 09 09:10:14 PM UTC 24 |
Sep 09 09:10:21 PM UTC 24 |
170918210 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2474326422 |
|
|
Sep 09 09:10:14 PM UTC 24 |
Sep 09 09:10:22 PM UTC 24 |
469781357 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3301015600 |
|
|
Sep 09 09:10:14 PM UTC 24 |
Sep 09 09:10:22 PM UTC 24 |
111125370 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2016795244 |
|
|
Sep 09 09:10:17 PM UTC 24 |
Sep 09 09:10:23 PM UTC 24 |
100124250 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1386678245 |
|
|
Sep 09 09:10:19 PM UTC 24 |
Sep 09 09:10:25 PM UTC 24 |
45682564 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2340003265 |
|
|
Sep 09 09:10:16 PM UTC 24 |
Sep 09 09:10:25 PM UTC 24 |
43472113 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3854346760 |
|
|
Sep 09 09:10:11 PM UTC 24 |
Sep 09 09:10:25 PM UTC 24 |
106354826 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3597605963 |
|
|
Sep 09 09:10:16 PM UTC 24 |
Sep 09 09:10:26 PM UTC 24 |
22598963 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3414983390 |
|
|
Sep 09 09:10:16 PM UTC 24 |
Sep 09 09:10:26 PM UTC 24 |
92322880 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3485798729 |
|
|
Sep 09 09:10:12 PM UTC 24 |
Sep 09 09:10:26 PM UTC 24 |
199218508 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.840726105 |
|
|
Sep 09 09:10:16 PM UTC 24 |
Sep 09 09:10:26 PM UTC 24 |
123938775 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.981594375 |
|
|
Sep 09 09:10:18 PM UTC 24 |
Sep 09 09:10:30 PM UTC 24 |
24133234 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.577664208 |
|
|
Sep 09 09:10:18 PM UTC 24 |
Sep 09 09:10:30 PM UTC 24 |
189591813 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3368612752 |
|
|
Sep 09 09:10:17 PM UTC 24 |
Sep 09 09:10:31 PM UTC 24 |
44332991 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2316115012 |
|
|
Sep 09 09:10:04 PM UTC 24 |
Sep 09 09:10:34 PM UTC 24 |
4274331750 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2072703577 |
|
|
Sep 09 09:10:16 PM UTC 24 |
Sep 09 09:10:35 PM UTC 24 |
14239259 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3286351813 |
|
|
Sep 09 09:10:12 PM UTC 24 |
Sep 09 09:10:35 PM UTC 24 |
42823825 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2488745582 |
|
|
Sep 09 09:10:12 PM UTC 24 |
Sep 09 09:10:35 PM UTC 24 |
290367032 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1243614745 |
|
|
Sep 09 09:10:13 PM UTC 24 |
Sep 09 09:10:35 PM UTC 24 |
28271051 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2067423023 |
|
|
Sep 09 09:10:13 PM UTC 24 |
Sep 09 09:10:35 PM UTC 24 |
15757604 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1942702783 |
|
|
Sep 09 09:10:16 PM UTC 24 |
Sep 09 09:10:36 PM UTC 24 |
58151640 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.128855910 |
|
|
Sep 09 09:10:13 PM UTC 24 |
Sep 09 09:10:36 PM UTC 24 |
18027862 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3945278540 |
|
|
Sep 09 09:10:16 PM UTC 24 |
Sep 09 09:10:36 PM UTC 24 |
107017062 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.395093096 |
|
|
Sep 09 09:10:13 PM UTC 24 |
Sep 09 09:10:36 PM UTC 24 |
35977201 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.480461990 |
|
|
Sep 09 09:10:16 PM UTC 24 |
Sep 09 09:10:36 PM UTC 24 |
20861733 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.379021329 |
|
|
Sep 09 09:10:13 PM UTC 24 |
Sep 09 09:10:36 PM UTC 24 |
45258997 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1135783366 |
|
|
Sep 09 09:10:13 PM UTC 24 |
Sep 09 09:10:37 PM UTC 24 |
84784826 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3512953326 |
|
|
Sep 09 09:10:13 PM UTC 24 |
Sep 09 09:10:37 PM UTC 24 |
147752855 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4070379100 |
|
|
Sep 09 09:10:16 PM UTC 24 |
Sep 09 09:10:38 PM UTC 24 |
78526486 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.402679683 |
|
|
Sep 09 09:10:13 PM UTC 24 |
Sep 09 09:10:43 PM UTC 24 |
14061951 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3385579025 |
|
|
Sep 09 09:10:13 PM UTC 24 |
Sep 09 09:10:43 PM UTC 24 |
64325144 ps |