| T816 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.4259330584 |
|
|
Sep 11 06:53:28 PM UTC 24 |
Sep 11 06:53:37 PM UTC 24 |
1035139246 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.3600786235 |
|
|
Sep 11 06:53:21 PM UTC 24 |
Sep 11 06:53:37 PM UTC 24 |
2609869890 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.1833059262 |
|
|
Sep 11 06:53:21 PM UTC 24 |
Sep 11 06:53:37 PM UTC 24 |
1261094561 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.2777756089 |
|
|
Sep 11 06:53:21 PM UTC 24 |
Sep 11 06:53:37 PM UTC 24 |
988253012 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.2309953777 |
|
|
Sep 11 06:53:28 PM UTC 24 |
Sep 11 06:53:38 PM UTC 24 |
2050749760 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.2032043540 |
|
|
Sep 11 06:53:26 PM UTC 24 |
Sep 11 06:53:39 PM UTC 24 |
558619763 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.841700060 |
|
|
Sep 11 06:53:26 PM UTC 24 |
Sep 11 06:53:40 PM UTC 24 |
1416092469 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2075662791 |
|
|
Sep 11 06:53:39 PM UTC 24 |
Sep 11 06:53:42 PM UTC 24 |
30071786 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.4131594839 |
|
|
Sep 11 06:53:39 PM UTC 24 |
Sep 11 06:53:42 PM UTC 24 |
19008302 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.763253535 |
|
|
Sep 11 06:53:26 PM UTC 24 |
Sep 11 06:53:44 PM UTC 24 |
1462816396 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.755979037 |
|
|
Sep 11 06:50:35 PM UTC 24 |
Sep 11 06:53:44 PM UTC 24 |
4494905701 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.2425811047 |
|
|
Sep 11 06:53:35 PM UTC 24 |
Sep 11 06:53:44 PM UTC 24 |
1585977045 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.2286384922 |
|
|
Sep 11 06:53:03 PM UTC 24 |
Sep 11 06:53:45 PM UTC 24 |
500855425 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.452550062 |
|
|
Sep 11 06:53:32 PM UTC 24 |
Sep 11 06:53:45 PM UTC 24 |
363353726 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.2980809000 |
|
|
Sep 11 06:53:39 PM UTC 24 |
Sep 11 06:53:46 PM UTC 24 |
700891078 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.3971006092 |
|
|
Sep 11 06:53:35 PM UTC 24 |
Sep 11 06:53:46 PM UTC 24 |
288050805 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.745334884 |
|
|
Sep 11 06:53:43 PM UTC 24 |
Sep 11 06:53:47 PM UTC 24 |
94902906 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.1177491245 |
|
|
Sep 11 06:51:11 PM UTC 24 |
Sep 11 06:53:47 PM UTC 24 |
16349462954 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.976553826 |
|
|
Sep 11 06:53:37 PM UTC 24 |
Sep 11 06:53:48 PM UTC 24 |
221244900 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.2059015705 |
|
|
Sep 11 06:52:55 PM UTC 24 |
Sep 11 06:53:49 PM UTC 24 |
1117292471 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.2405541177 |
|
|
Sep 11 06:53:37 PM UTC 24 |
Sep 11 06:53:51 PM UTC 24 |
1204680563 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.1379695628 |
|
|
Sep 11 06:53:33 PM UTC 24 |
Sep 11 06:53:51 PM UTC 24 |
1150649146 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.491186070 |
|
|
Sep 11 06:52:08 PM UTC 24 |
Sep 11 06:53:51 PM UTC 24 |
5452238726 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.2284474772 |
|
|
Sep 11 06:53:49 PM UTC 24 |
Sep 11 06:53:52 PM UTC 24 |
91874142 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.2250040123 |
|
|
Sep 11 06:53:42 PM UTC 24 |
Sep 11 06:53:52 PM UTC 24 |
71549289 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.3993991076 |
|
|
Sep 11 06:53:37 PM UTC 24 |
Sep 11 06:53:52 PM UTC 24 |
2160431405 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.2438578632 |
|
|
Sep 11 06:53:43 PM UTC 24 |
Sep 11 06:53:53 PM UTC 24 |
602490233 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2149108313 |
|
|
Sep 11 06:51:17 PM UTC 24 |
Sep 11 06:53:53 PM UTC 24 |
21548011988 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2618387247 |
|
|
Sep 11 06:52:02 PM UTC 24 |
Sep 11 06:53:54 PM UTC 24 |
12334926124 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.31391782 |
|
|
Sep 11 06:53:47 PM UTC 24 |
Sep 11 06:53:56 PM UTC 24 |
1361078648 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.255188874 |
|
|
Sep 11 06:53:47 PM UTC 24 |
Sep 11 06:53:58 PM UTC 24 |
1086092686 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.662520141 |
|
|
Sep 11 06:51:43 PM UTC 24 |
Sep 11 06:53:58 PM UTC 24 |
18977586815 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.2437355895 |
|
|
Sep 11 06:53:19 PM UTC 24 |
Sep 11 06:53:58 PM UTC 24 |
981415968 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.2467892815 |
|
|
Sep 11 06:51:35 PM UTC 24 |
Sep 11 06:53:58 PM UTC 24 |
5690635428 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.4062076845 |
|
|
Sep 11 06:53:45 PM UTC 24 |
Sep 11 06:53:59 PM UTC 24 |
1079972066 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.3106333067 |
|
|
Sep 11 06:53:26 PM UTC 24 |
Sep 11 06:53:59 PM UTC 24 |
9658274971 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.1961392394 |
|
|
Sep 11 06:53:09 PM UTC 24 |
Sep 11 06:53:59 PM UTC 24 |
270637838 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.3165557823 |
|
|
Sep 11 06:53:24 PM UTC 24 |
Sep 11 06:53:59 PM UTC 24 |
1225900823 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.1364984271 |
|
|
Sep 11 06:53:47 PM UTC 24 |
Sep 11 06:54:05 PM UTC 24 |
2481102573 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.270281930 |
|
|
Sep 11 06:53:47 PM UTC 24 |
Sep 11 06:54:06 PM UTC 24 |
422928502 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.3124459899 |
|
|
Sep 11 06:53:32 PM UTC 24 |
Sep 11 06:54:09 PM UTC 24 |
478913497 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.4185746728 |
|
|
Sep 11 06:53:41 PM UTC 24 |
Sep 11 06:54:19 PM UTC 24 |
297280806 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.3087550062 |
|
|
Sep 11 06:51:43 PM UTC 24 |
Sep 11 06:54:23 PM UTC 24 |
18985800406 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1506405043 |
|
|
Sep 11 06:52:21 PM UTC 24 |
Sep 11 06:54:28 PM UTC 24 |
24119116671 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.1123426391 |
|
|
Sep 11 06:52:21 PM UTC 24 |
Sep 11 06:54:31 PM UTC 24 |
15030929167 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1930705504 |
|
|
Sep 11 06:53:00 PM UTC 24 |
Sep 11 06:54:36 PM UTC 24 |
8832797847 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.1517752728 |
|
|
Sep 11 06:51:06 PM UTC 24 |
Sep 11 06:54:38 PM UTC 24 |
5987737780 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.1566111348 |
|
|
Sep 11 06:53:23 PM UTC 24 |
Sep 11 06:54:42 PM UTC 24 |
2415369331 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.2563337738 |
|
|
Sep 11 06:52:25 PM UTC 24 |
Sep 11 06:54:45 PM UTC 24 |
21718315121 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.3033252981 |
|
|
Sep 11 06:53:39 PM UTC 24 |
Sep 11 06:55:06 PM UTC 24 |
3550095398 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.1036563960 |
|
|
Sep 11 06:50:02 PM UTC 24 |
Sep 11 06:55:11 PM UTC 24 |
34134959735 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.2728895085 |
|
|
Sep 11 06:53:15 PM UTC 24 |
Sep 11 06:55:20 PM UTC 24 |
117463210640 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.3298828935 |
|
|
Sep 11 06:52:45 PM UTC 24 |
Sep 11 06:55:41 PM UTC 24 |
36046265711 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.3838401364 |
|
|
Sep 11 06:53:23 PM UTC 24 |
Sep 11 06:55:42 PM UTC 24 |
10888102497 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.1837271813 |
|
|
Sep 11 06:50:55 PM UTC 24 |
Sep 11 06:55:44 PM UTC 24 |
7920911091 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.1337214817 |
|
|
Sep 11 06:52:15 PM UTC 24 |
Sep 11 06:55:49 PM UTC 24 |
7787166940 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.3449974193 |
|
|
Sep 11 06:51:29 PM UTC 24 |
Sep 11 06:55:57 PM UTC 24 |
8831336829 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.2480652782 |
|
|
Sep 11 06:53:30 PM UTC 24 |
Sep 11 06:56:51 PM UTC 24 |
19817209442 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.2977552420 |
|
|
Sep 11 06:52:52 PM UTC 24 |
Sep 11 06:57:05 PM UTC 24 |
6681659540 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.2051690582 |
|
|
Sep 11 06:52:02 PM UTC 24 |
Sep 11 06:57:53 PM UTC 24 |
11674819344 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.3460339647 |
|
|
Sep 11 06:53:08 PM UTC 24 |
Sep 11 06:58:17 PM UTC 24 |
19578617829 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.4103164101 |
|
|
Sep 11 06:51:21 PM UTC 24 |
Sep 11 06:58:54 PM UTC 24 |
33090583715 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3222831339 |
|
|
Sep 11 06:49:11 PM UTC 24 |
Sep 11 06:59:59 PM UTC 24 |
77155631318 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.502601912 |
|
|
Sep 11 06:52:40 PM UTC 24 |
Sep 11 07:01:25 PM UTC 24 |
16244761180 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.1109118149 |
|
|
Sep 11 06:49:01 PM UTC 24 |
Sep 11 07:01:29 PM UTC 24 |
87627623234 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.3173324064 |
|
|
Sep 11 06:53:47 PM UTC 24 |
Sep 11 07:02:57 PM UTC 24 |
31585931995 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2842574975 |
|
|
Sep 11 06:45:51 PM UTC 24 |
Sep 11 06:45:55 PM UTC 24 |
109316820 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4165623490 |
|
|
Sep 11 06:45:55 PM UTC 24 |
Sep 11 06:45:58 PM UTC 24 |
760896387 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1557788494 |
|
|
Sep 11 06:45:58 PM UTC 24 |
Sep 11 06:46:01 PM UTC 24 |
338764764 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1033034651 |
|
|
Sep 11 06:46:00 PM UTC 24 |
Sep 11 06:46:02 PM UTC 24 |
121519474 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2262466064 |
|
|
Sep 11 06:45:59 PM UTC 24 |
Sep 11 06:46:05 PM UTC 24 |
363591369 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2810412664 |
|
|
Sep 11 06:46:03 PM UTC 24 |
Sep 11 06:46:05 PM UTC 24 |
13208415 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3936680081 |
|
|
Sep 11 06:46:02 PM UTC 24 |
Sep 11 06:46:06 PM UTC 24 |
289679870 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.841408678 |
|
|
Sep 11 06:46:03 PM UTC 24 |
Sep 11 06:46:08 PM UTC 24 |
450751435 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2738916252 |
|
|
Sep 11 06:46:06 PM UTC 24 |
Sep 11 06:46:08 PM UTC 24 |
13779283 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1884619159 |
|
|
Sep 11 06:46:06 PM UTC 24 |
Sep 11 06:46:09 PM UTC 24 |
378538194 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3627656603 |
|
|
Sep 11 06:46:07 PM UTC 24 |
Sep 11 06:46:09 PM UTC 24 |
436102597 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3976500045 |
|
|
Sep 11 06:46:07 PM UTC 24 |
Sep 11 06:46:10 PM UTC 24 |
66811287 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2088816424 |
|
|
Sep 11 06:46:08 PM UTC 24 |
Sep 11 06:46:11 PM UTC 24 |
116022926 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4165197738 |
|
|
Sep 11 06:46:09 PM UTC 24 |
Sep 11 06:46:13 PM UTC 24 |
140621149 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2588377339 |
|
|
Sep 11 06:46:11 PM UTC 24 |
Sep 11 06:46:13 PM UTC 24 |
16504769 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.242764121 |
|
|
Sep 11 06:46:11 PM UTC 24 |
Sep 11 06:46:14 PM UTC 24 |
247092703 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3950770694 |
|
|
Sep 11 06:45:56 PM UTC 24 |
Sep 11 06:46:14 PM UTC 24 |
967566573 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3576778322 |
|
|
Sep 11 06:46:09 PM UTC 24 |
Sep 11 06:46:14 PM UTC 24 |
472699856 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2777028528 |
|
|
Sep 11 06:46:32 PM UTC 24 |
Sep 11 06:46:34 PM UTC 24 |
31303108 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1015605414 |
|
|
Sep 11 06:46:11 PM UTC 24 |
Sep 11 06:46:15 PM UTC 24 |
49470974 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.333337849 |
|
|
Sep 11 06:46:13 PM UTC 24 |
Sep 11 06:46:15 PM UTC 24 |
12862319 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2035131151 |
|
|
Sep 11 06:46:13 PM UTC 24 |
Sep 11 06:46:15 PM UTC 24 |
33607508 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.121515057 |
|
|
Sep 11 06:46:13 PM UTC 24 |
Sep 11 06:46:16 PM UTC 24 |
39704858 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2622297205 |
|
|
Sep 11 06:46:14 PM UTC 24 |
Sep 11 06:46:17 PM UTC 24 |
22970752 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.36107432 |
|
|
Sep 11 06:46:14 PM UTC 24 |
Sep 11 06:46:17 PM UTC 24 |
92269702 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3734689455 |
|
|
Sep 11 06:46:11 PM UTC 24 |
Sep 11 06:46:17 PM UTC 24 |
191259431 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3546279104 |
|
|
Sep 11 06:46:30 PM UTC 24 |
Sep 11 06:46:34 PM UTC 24 |
185069422 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1629580635 |
|
|
Sep 11 06:46:12 PM UTC 24 |
Sep 11 06:46:17 PM UTC 24 |
422762652 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1413195727 |
|
|
Sep 11 06:46:15 PM UTC 24 |
Sep 11 06:46:18 PM UTC 24 |
21897346 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1610563695 |
|
|
Sep 11 06:46:15 PM UTC 24 |
Sep 11 06:46:19 PM UTC 24 |
65047331 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1512986607 |
|
|
Sep 11 06:46:17 PM UTC 24 |
Sep 11 06:46:20 PM UTC 24 |
139364842 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.953360433 |
|
|
Sep 11 06:46:17 PM UTC 24 |
Sep 11 06:46:20 PM UTC 24 |
439058411 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.90081746 |
|
|
Sep 11 06:46:15 PM UTC 24 |
Sep 11 06:46:20 PM UTC 24 |
137682596 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2896000918 |
|
|
Sep 11 06:46:18 PM UTC 24 |
Sep 11 06:46:20 PM UTC 24 |
16698922 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2092687945 |
|
|
Sep 11 06:46:17 PM UTC 24 |
Sep 11 06:46:20 PM UTC 24 |
256361264 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.638973017 |
|
|
Sep 11 06:46:18 PM UTC 24 |
Sep 11 06:46:21 PM UTC 24 |
39800490 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1082718422 |
|
|
Sep 11 06:46:18 PM UTC 24 |
Sep 11 06:46:21 PM UTC 24 |
458915499 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3869405585 |
|
|
Sep 11 06:46:19 PM UTC 24 |
Sep 11 06:46:22 PM UTC 24 |
26802292 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3450079551 |
|
|
Sep 11 06:46:20 PM UTC 24 |
Sep 11 06:46:23 PM UTC 24 |
279610970 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.418367591 |
|
|
Sep 11 06:46:21 PM UTC 24 |
Sep 11 06:46:24 PM UTC 24 |
40025955 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3182364684 |
|
|
Sep 11 06:46:21 PM UTC 24 |
Sep 11 06:46:24 PM UTC 24 |
73517548 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2750909320 |
|
|
Sep 11 06:46:21 PM UTC 24 |
Sep 11 06:46:25 PM UTC 24 |
162646441 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4291458214 |
|
|
Sep 11 06:46:22 PM UTC 24 |
Sep 11 06:46:25 PM UTC 24 |
168600308 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.489375376 |
|
|
Sep 11 06:46:18 PM UTC 24 |
Sep 11 06:46:26 PM UTC 24 |
170286589 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2097605118 |
|
|
Sep 11 06:46:21 PM UTC 24 |
Sep 11 06:46:26 PM UTC 24 |
306670916 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3676812340 |
|
|
Sep 11 06:46:23 PM UTC 24 |
Sep 11 06:46:26 PM UTC 24 |
319134489 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2094926676 |
|
|
Sep 11 06:46:26 PM UTC 24 |
Sep 11 06:46:28 PM UTC 24 |
43675653 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2947695732 |
|
|
Sep 11 06:46:26 PM UTC 24 |
Sep 11 06:46:28 PM UTC 24 |
44484268 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4117678495 |
|
|
Sep 11 06:46:10 PM UTC 24 |
Sep 11 06:46:29 PM UTC 24 |
1418615057 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.201015548 |
|
|
Sep 11 06:46:15 PM UTC 24 |
Sep 11 06:46:29 PM UTC 24 |
1104810843 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.668758300 |
|
|
Sep 11 06:46:09 PM UTC 24 |
Sep 11 06:46:29 PM UTC 24 |
692503276 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.254539125 |
|
|
Sep 11 06:46:26 PM UTC 24 |
Sep 11 06:46:30 PM UTC 24 |
65938707 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1564534285 |
|
|
Sep 11 06:46:21 PM UTC 24 |
Sep 11 06:46:30 PM UTC 24 |
1539531507 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.140677355 |
|
|
Sep 11 06:46:27 PM UTC 24 |
Sep 11 06:46:30 PM UTC 24 |
104555752 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2854715530 |
|
|
Sep 11 06:46:25 PM UTC 24 |
Sep 11 06:46:30 PM UTC 24 |
2179715244 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.781726580 |
|
|
Sep 11 06:46:27 PM UTC 24 |
Sep 11 06:46:30 PM UTC 24 |
25448895 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1749791951 |
|
|
Sep 11 06:46:25 PM UTC 24 |
Sep 11 06:46:31 PM UTC 24 |
52766652 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1742099261 |
|
|
Sep 11 06:46:27 PM UTC 24 |
Sep 11 06:46:31 PM UTC 24 |
39080311 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3617846784 |
|
|
Sep 11 06:46:23 PM UTC 24 |
Sep 11 06:46:31 PM UTC 24 |
866306288 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2044568063 |
|
|
Sep 11 06:46:29 PM UTC 24 |
Sep 11 06:46:32 PM UTC 24 |
97955728 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2807376518 |
|
|
Sep 11 06:46:29 PM UTC 24 |
Sep 11 06:46:32 PM UTC 24 |
62747396 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2308287012 |
|
|
Sep 11 06:46:15 PM UTC 24 |
Sep 11 06:46:33 PM UTC 24 |
958146048 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.634794180 |
|
|
Sep 11 06:45:58 PM UTC 24 |
Sep 11 06:46:33 PM UTC 24 |
4574939000 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3409503190 |
|
|
Sep 11 06:46:30 PM UTC 24 |
Sep 11 06:46:33 PM UTC 24 |
35311970 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2436257769 |
|
|
Sep 11 06:46:32 PM UTC 24 |
Sep 11 06:46:34 PM UTC 24 |
36427409 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2546080589 |
|
|
Sep 11 06:46:30 PM UTC 24 |
Sep 11 06:46:34 PM UTC 24 |
75658886 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4103423780 |
|
|
Sep 11 06:46:32 PM UTC 24 |
Sep 11 06:46:34 PM UTC 24 |
14950894 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4126682710 |
|
|
Sep 11 06:46:32 PM UTC 24 |
Sep 11 06:46:35 PM UTC 24 |
51016349 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.421555062 |
|
|
Sep 11 06:46:30 PM UTC 24 |
Sep 11 06:46:36 PM UTC 24 |
79697346 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3173043804 |
|
|
Sep 11 06:46:33 PM UTC 24 |
Sep 11 06:46:36 PM UTC 24 |
67736547 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3049898595 |
|
|
Sep 11 06:46:30 PM UTC 24 |
Sep 11 06:46:36 PM UTC 24 |
191276004 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.179595057 |
|
|
Sep 11 06:46:33 PM UTC 24 |
Sep 11 06:46:37 PM UTC 24 |
183333093 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3576928003 |
|
|
Sep 11 06:46:30 PM UTC 24 |
Sep 11 06:46:37 PM UTC 24 |
122011162 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2391338600 |
|
|
Sep 11 06:46:34 PM UTC 24 |
Sep 11 06:46:37 PM UTC 24 |
361378002 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2066018591 |
|
|
Sep 11 06:46:35 PM UTC 24 |
Sep 11 06:46:38 PM UTC 24 |
21419133 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3623174881 |
|
|
Sep 11 06:46:35 PM UTC 24 |
Sep 11 06:46:38 PM UTC 24 |
34981753 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1864508879 |
|
|
Sep 11 06:46:36 PM UTC 24 |
Sep 11 06:46:39 PM UTC 24 |
14470438 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1637970817 |
|
|
Sep 11 06:46:36 PM UTC 24 |
Sep 11 06:46:39 PM UTC 24 |
18514686 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3084493555 |
|
|
Sep 11 06:46:35 PM UTC 24 |
Sep 11 06:46:39 PM UTC 24 |
233844239 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2635661060 |
|
|
Sep 11 06:46:35 PM UTC 24 |
Sep 11 06:46:40 PM UTC 24 |
42904786 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1376803426 |
|
|
Sep 11 06:46:36 PM UTC 24 |
Sep 11 06:46:40 PM UTC 24 |
26408904 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3659400613 |
|
|
Sep 11 06:46:21 PM UTC 24 |
Sep 11 06:46:40 PM UTC 24 |
6734137272 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.74330751 |
|
|
Sep 11 06:46:38 PM UTC 24 |
Sep 11 06:46:41 PM UTC 24 |
55049329 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1683382845 |
|
|
Sep 11 06:46:34 PM UTC 24 |
Sep 11 06:46:41 PM UTC 24 |
139828213 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1216826772 |
|
|
Sep 11 06:46:38 PM UTC 24 |
Sep 11 06:46:41 PM UTC 24 |
601092854 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1414908329 |
|
|
Sep 11 06:46:35 PM UTC 24 |
Sep 11 06:46:41 PM UTC 24 |
111440938 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3205052832 |
|
|
Sep 11 06:46:40 PM UTC 24 |
Sep 11 06:46:42 PM UTC 24 |
69146165 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.95857887 |
|
|
Sep 11 06:46:29 PM UTC 24 |
Sep 11 06:46:43 PM UTC 24 |
908978525 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3771023913 |
|
|
Sep 11 06:46:39 PM UTC 24 |
Sep 11 06:46:43 PM UTC 24 |
91107010 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3163023042 |
|
|
Sep 11 06:46:40 PM UTC 24 |
Sep 11 06:46:44 PM UTC 24 |
65225180 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3911130693 |
|
|
Sep 11 06:46:40 PM UTC 24 |
Sep 11 06:46:44 PM UTC 24 |
241975439 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3833815162 |
|
|
Sep 11 06:46:41 PM UTC 24 |
Sep 11 06:46:44 PM UTC 24 |
94076210 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2034478521 |
|
|
Sep 11 06:46:41 PM UTC 24 |
Sep 11 06:46:44 PM UTC 24 |
82658657 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2412259513 |
|
|
Sep 11 06:46:39 PM UTC 24 |
Sep 11 06:46:45 PM UTC 24 |
87203753 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.149373482 |
|
|
Sep 11 06:46:41 PM UTC 24 |
Sep 11 06:46:45 PM UTC 24 |
588041472 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1331980920 |
|
|
Sep 11 06:46:40 PM UTC 24 |
Sep 11 06:46:45 PM UTC 24 |
172011700 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.945662868 |
|
|
Sep 11 06:46:43 PM UTC 24 |
Sep 11 06:46:46 PM UTC 24 |
27854801 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1194071325 |
|
|
Sep 11 06:46:44 PM UTC 24 |
Sep 11 06:46:47 PM UTC 24 |
322179507 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.165249898 |
|
|
Sep 11 06:46:45 PM UTC 24 |
Sep 11 06:46:47 PM UTC 24 |
56387101 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4250123467 |
|
|
Sep 11 06:46:34 PM UTC 24 |
Sep 11 06:46:48 PM UTC 24 |
970105169 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1727373335 |
|
|
Sep 11 06:46:41 PM UTC 24 |
Sep 11 06:46:48 PM UTC 24 |
198012460 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3716851091 |
|
|
Sep 11 06:46:45 PM UTC 24 |
Sep 11 06:46:48 PM UTC 24 |
36316436 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1079256524 |
|
|
Sep 11 06:46:39 PM UTC 24 |
Sep 11 06:46:48 PM UTC 24 |
8822900767 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3903072398 |
|
|
Sep 11 06:46:44 PM UTC 24 |
Sep 11 06:46:48 PM UTC 24 |
369920740 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.4258411455 |
|
|
Sep 11 06:46:46 PM UTC 24 |
Sep 11 06:46:48 PM UTC 24 |
29396160 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2100574192 |
|
|
Sep 11 06:46:46 PM UTC 24 |
Sep 11 06:46:50 PM UTC 24 |
82294952 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3956764315 |
|
|
Sep 11 06:46:45 PM UTC 24 |
Sep 11 06:46:50 PM UTC 24 |
175122787 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.4187554087 |
|
|
Sep 11 06:46:48 PM UTC 24 |
Sep 11 06:46:51 PM UTC 24 |
90594139 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1163396345 |
|
|
Sep 11 06:46:48 PM UTC 24 |
Sep 11 06:46:51 PM UTC 24 |
19625993 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3593040264 |
|
|
Sep 11 06:46:48 PM UTC 24 |
Sep 11 06:46:52 PM UTC 24 |
67565820 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.990373607 |
|
|
Sep 11 06:46:50 PM UTC 24 |
Sep 11 06:46:52 PM UTC 24 |
56627886 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.248802990 |
|
|
Sep 11 06:46:38 PM UTC 24 |
Sep 11 06:46:52 PM UTC 24 |
698190914 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1910294404 |
|
|
Sep 11 06:46:48 PM UTC 24 |
Sep 11 06:46:52 PM UTC 24 |
390396229 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2757946128 |
|
|
Sep 11 06:46:53 PM UTC 24 |
Sep 11 06:47:03 PM UTC 24 |
199994663 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.179708980 |
|
|
Sep 11 06:46:45 PM UTC 24 |
Sep 11 06:46:52 PM UTC 24 |
592304050 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3037751969 |
|
|
Sep 11 06:46:48 PM UTC 24 |
Sep 11 06:46:53 PM UTC 24 |
77061546 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2129355218 |
|
|
Sep 11 06:46:48 PM UTC 24 |
Sep 11 06:46:53 PM UTC 24 |
61530111 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3905933623 |
|
|
Sep 11 06:46:49 PM UTC 24 |
Sep 11 06:46:53 PM UTC 24 |
48351027 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3679358716 |
|
|
Sep 11 06:46:42 PM UTC 24 |
Sep 11 06:46:53 PM UTC 24 |
1117006152 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2027697631 |
|
|
Sep 11 06:46:42 PM UTC 24 |
Sep 11 06:46:54 PM UTC 24 |
1369124125 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3077413685 |
|
|
Sep 11 06:46:46 PM UTC 24 |
Sep 11 06:46:55 PM UTC 24 |
668306923 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2072411335 |
|
|
Sep 11 06:46:51 PM UTC 24 |
Sep 11 06:46:55 PM UTC 24 |
83875900 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2906293520 |
|
|
Sep 11 06:46:53 PM UTC 24 |
Sep 11 06:46:55 PM UTC 24 |
38590192 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2436675877 |
|
|
Sep 11 06:46:53 PM UTC 24 |
Sep 11 06:46:56 PM UTC 24 |
23835239 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3854624790 |
|
|
Sep 11 06:46:53 PM UTC 24 |
Sep 11 06:46:56 PM UTC 24 |
20423811 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.4294057958 |
|
|
Sep 11 06:46:51 PM UTC 24 |
Sep 11 06:46:56 PM UTC 24 |
80505662 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2142202708 |
|
|
Sep 11 06:46:53 PM UTC 24 |
Sep 11 06:46:56 PM UTC 24 |
39771365 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1438550514 |
|
|
Sep 11 06:46:34 PM UTC 24 |
Sep 11 06:46:57 PM UTC 24 |
4136632510 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.4023294174 |
|
|
Sep 11 06:46:55 PM UTC 24 |
Sep 11 06:46:57 PM UTC 24 |
23860945 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3748440185 |
|
|
Sep 11 06:46:53 PM UTC 24 |
Sep 11 06:46:58 PM UTC 24 |
246694007 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2860689742 |
|
|
Sep 11 06:46:54 PM UTC 24 |
Sep 11 06:46:58 PM UTC 24 |
45418085 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3167771154 |
|
|
Sep 11 06:46:55 PM UTC 24 |
Sep 11 06:46:58 PM UTC 24 |
110426037 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.686826614 |
|
|
Sep 11 06:46:55 PM UTC 24 |
Sep 11 06:46:58 PM UTC 24 |
48939838 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1188214657 |
|
|
Sep 11 06:46:54 PM UTC 24 |
Sep 11 06:46:59 PM UTC 24 |
84506344 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1060168044 |
|
|
Sep 11 06:46:57 PM UTC 24 |
Sep 11 06:46:59 PM UTC 24 |
70864178 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1525995989 |
|
|
Sep 11 06:46:57 PM UTC 24 |
Sep 11 06:46:59 PM UTC 24 |
52666315 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4034331679 |
|
|
Sep 11 06:46:57 PM UTC 24 |
Sep 11 06:46:59 PM UTC 24 |
288612104 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.111222030 |
|
|
Sep 11 06:47:01 PM UTC 24 |
Sep 11 06:47:03 PM UTC 24 |
119312307 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1470635308 |
|
|
Sep 11 06:46:53 PM UTC 24 |
Sep 11 06:47:00 PM UTC 24 |
463450488 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1921296944 |
|
|
Sep 11 06:46:53 PM UTC 24 |
Sep 11 06:47:00 PM UTC 24 |
1736281833 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3494050458 |
|
|
Sep 11 06:46:57 PM UTC 24 |
Sep 11 06:47:00 PM UTC 24 |
66265404 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3662220521 |
|
|
Sep 11 06:46:58 PM UTC 24 |
Sep 11 06:47:00 PM UTC 24 |
17656485 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1667513833 |
|
|
Sep 11 06:46:58 PM UTC 24 |
Sep 11 06:47:00 PM UTC 24 |
22399260 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.147245149 |
|
|
Sep 11 06:46:57 PM UTC 24 |
Sep 11 06:47:01 PM UTC 24 |
1862848712 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.398666904 |
|
|
Sep 11 06:46:59 PM UTC 24 |
Sep 11 06:47:02 PM UTC 24 |
26348632 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2112980167 |
|
|
Sep 11 06:46:59 PM UTC 24 |
Sep 11 06:47:02 PM UTC 24 |
29691594 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3088249183 |
|
|
Sep 11 06:46:59 PM UTC 24 |
Sep 11 06:47:02 PM UTC 24 |
21278943 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.960281790 |
|
|
Sep 11 06:46:59 PM UTC 24 |
Sep 11 06:47:02 PM UTC 24 |
41579270 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.641990515 |
|
|
Sep 11 06:47:02 PM UTC 24 |
Sep 11 06:47:04 PM UTC 24 |
19337081 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1106144794 |
|
|
Sep 11 06:46:52 PM UTC 24 |
Sep 11 06:47:02 PM UTC 24 |
3535977801 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3063510363 |
|
|
Sep 11 06:46:58 PM UTC 24 |
Sep 11 06:47:02 PM UTC 24 |
83112105 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2477203028 |
|
|
Sep 11 06:47:01 PM UTC 24 |
Sep 11 06:47:03 PM UTC 24 |
65088365 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3158493240 |
|
|
Sep 11 06:47:01 PM UTC 24 |
Sep 11 06:47:03 PM UTC 24 |
76561570 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.665058844 |
|
|
Sep 11 06:47:01 PM UTC 24 |
Sep 11 06:47:03 PM UTC 24 |
21375549 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1643832090 |
|
|
Sep 11 06:47:01 PM UTC 24 |
Sep 11 06:47:04 PM UTC 24 |
29617470 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1781006215 |
|
|
Sep 11 06:46:59 PM UTC 24 |
Sep 11 06:47:04 PM UTC 24 |
462789477 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2335649070 |
|
|
Sep 11 06:47:02 PM UTC 24 |
Sep 11 06:47:04 PM UTC 24 |
31565560 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3601600183 |
|
|
Sep 11 06:47:01 PM UTC 24 |
Sep 11 06:47:05 PM UTC 24 |
176643798 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2308434526 |
|
|
Sep 11 06:46:59 PM UTC 24 |
Sep 11 06:47:05 PM UTC 24 |
236297587 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1210030330 |
|
|
Sep 11 06:47:03 PM UTC 24 |
Sep 11 06:47:05 PM UTC 24 |
71092355 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3105304832 |
|
|
Sep 11 06:47:02 PM UTC 24 |
Sep 11 06:47:05 PM UTC 24 |
109365111 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2190581364 |
|
|
Sep 11 06:47:02 PM UTC 24 |
Sep 11 06:47:06 PM UTC 24 |
146534433 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2744343089 |
|
|
Sep 11 06:47:03 PM UTC 24 |
Sep 11 06:47:06 PM UTC 24 |
37421054 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.521335953 |
|
|
Sep 11 06:47:03 PM UTC 24 |
Sep 11 06:47:06 PM UTC 24 |
37469225 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.685943193 |
|
|
Sep 11 06:47:02 PM UTC 24 |
Sep 11 06:47:06 PM UTC 24 |
59562898 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4036178885 |
|
|
Sep 11 06:46:47 PM UTC 24 |
Sep 11 06:47:07 PM UTC 24 |
2766645240 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1011668853 |
|
|
Sep 11 06:47:02 PM UTC 24 |
Sep 11 06:47:07 PM UTC 24 |
77544224 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1412793949 |
|
|
Sep 11 06:47:04 PM UTC 24 |
Sep 11 06:47:07 PM UTC 24 |
43519027 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3721386449 |
|
|
Sep 11 06:47:05 PM UTC 24 |
Sep 11 06:47:07 PM UTC 24 |
19731843 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.688805629 |
|
|
Sep 11 06:47:05 PM UTC 24 |
Sep 11 06:47:07 PM UTC 24 |
25030918 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.4192604698 |
|
|
Sep 11 06:47:05 PM UTC 24 |
Sep 11 06:47:07 PM UTC 24 |
16472103 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.256443203 |
|
|
Sep 11 06:47:05 PM UTC 24 |
Sep 11 06:47:07 PM UTC 24 |
28096326 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3447735457 |
|
|
Sep 11 06:46:46 PM UTC 24 |
Sep 11 06:47:08 PM UTC 24 |
3308027653 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3149575114 |
|
|
Sep 11 06:47:03 PM UTC 24 |
Sep 11 06:47:08 PM UTC 24 |
83489796 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3881520376 |
|
|
Sep 11 06:47:03 PM UTC 24 |
Sep 11 06:47:08 PM UTC 24 |
324644884 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3352057844 |
|
|
Sep 11 06:47:06 PM UTC 24 |
Sep 11 06:47:08 PM UTC 24 |
13903578 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3506534536 |
|
|
Sep 11 06:47:03 PM UTC 24 |
Sep 11 06:47:09 PM UTC 24 |
388635656 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.613912967 |
|
|
Sep 11 06:47:06 PM UTC 24 |
Sep 11 06:47:09 PM UTC 24 |
158400506 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3141248826 |
|
|
Sep 11 06:47:06 PM UTC 24 |
Sep 11 06:47:09 PM UTC 24 |
79431666 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3466459741 |
|
|
Sep 11 06:47:06 PM UTC 24 |
Sep 11 06:47:10 PM UTC 24 |
26699829 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1823185594 |
|
|
Sep 11 06:47:07 PM UTC 24 |
Sep 11 06:47:10 PM UTC 24 |
31658627 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3903988380 |
|
|
Sep 11 06:47:05 PM UTC 24 |
Sep 11 06:47:10 PM UTC 24 |
90896400 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2605021451 |
|
|
Sep 11 06:47:05 PM UTC 24 |
Sep 11 06:47:10 PM UTC 24 |
103438813 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3029501596 |
|
|
Sep 11 06:47:06 PM UTC 24 |
Sep 11 06:47:10 PM UTC 24 |
184833063 ps |