| T583 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.777504039 |
|
|
Sep 24 11:07:15 PM UTC 24 |
Sep 24 11:07:50 PM UTC 24 |
315900075 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1541288420 |
|
|
Sep 24 11:07:12 PM UTC 24 |
Sep 24 11:07:50 PM UTC 24 |
870458196 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.1846517671 |
|
|
Sep 24 11:07:47 PM UTC 24 |
Sep 24 11:07:51 PM UTC 24 |
58251645 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.3529921775 |
|
|
Sep 24 11:07:29 PM UTC 24 |
Sep 24 11:07:52 PM UTC 24 |
2268842086 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.2797486625 |
|
|
Sep 24 11:07:37 PM UTC 24 |
Sep 24 11:07:53 PM UTC 24 |
1034988540 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.527125834 |
|
|
Sep 24 11:07:51 PM UTC 24 |
Sep 24 11:07:54 PM UTC 24 |
15205888 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2711823280 |
|
|
Sep 24 11:07:53 PM UTC 24 |
Sep 24 11:07:55 PM UTC 24 |
26801154 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.1648265549 |
|
|
Sep 24 11:07:51 PM UTC 24 |
Sep 24 11:07:55 PM UTC 24 |
41328682 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.1675823995 |
|
|
Sep 24 11:07:38 PM UTC 24 |
Sep 24 11:07:57 PM UTC 24 |
1371776179 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.190369168 |
|
|
Sep 24 11:07:47 PM UTC 24 |
Sep 24 11:07:57 PM UTC 24 |
144777329 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.2675508405 |
|
|
Sep 24 11:07:48 PM UTC 24 |
Sep 24 11:07:59 PM UTC 24 |
833840784 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.3927446257 |
|
|
Sep 24 11:07:48 PM UTC 24 |
Sep 24 11:08:00 PM UTC 24 |
335056235 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.3468318014 |
|
|
Sep 24 11:07:55 PM UTC 24 |
Sep 24 11:08:01 PM UTC 24 |
562199015 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_errors.401882122 |
|
|
Sep 24 11:07:47 PM UTC 24 |
Sep 24 11:08:04 PM UTC 24 |
1059009568 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.268388231 |
|
|
Sep 24 11:07:27 PM UTC 24 |
Sep 24 11:08:04 PM UTC 24 |
261781614 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.2974611270 |
|
|
Sep 24 11:07:50 PM UTC 24 |
Sep 24 11:08:04 PM UTC 24 |
1502159929 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.2263697260 |
|
|
Sep 24 11:07:33 PM UTC 24 |
Sep 24 11:08:06 PM UTC 24 |
1467856904 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.3843180795 |
|
|
Sep 24 11:07:50 PM UTC 24 |
Sep 24 11:08:06 PM UTC 24 |
297490781 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.3526071609 |
|
|
Sep 24 11:07:31 PM UTC 24 |
Sep 24 11:08:07 PM UTC 24 |
999434713 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.1676860859 |
|
|
Sep 24 11:08:00 PM UTC 24 |
Sep 24 11:08:08 PM UTC 24 |
946668275 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.294821246 |
|
|
Sep 24 11:07:54 PM UTC 24 |
Sep 24 11:08:08 PM UTC 24 |
53533983 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.3805614780 |
|
|
Sep 24 11:08:06 PM UTC 24 |
Sep 24 11:08:08 PM UTC 24 |
16211763 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.1323725794 |
|
|
Sep 24 11:07:59 PM UTC 24 |
Sep 24 11:08:09 PM UTC 24 |
1133106047 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.2557396642 |
|
|
Sep 24 11:07:47 PM UTC 24 |
Sep 24 11:08:09 PM UTC 24 |
466159369 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.3497711423 |
|
|
Sep 24 11:06:14 PM UTC 24 |
Sep 24 11:08:10 PM UTC 24 |
27395803998 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.780431856 |
|
|
Sep 24 11:08:07 PM UTC 24 |
Sep 24 11:08:10 PM UTC 24 |
22487990 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.4010713470 |
|
|
Sep 24 11:07:56 PM UTC 24 |
Sep 24 11:08:10 PM UTC 24 |
444447199 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.3420273361 |
|
|
Sep 24 11:07:48 PM UTC 24 |
Sep 24 11:08:10 PM UTC 24 |
1469220464 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.263870738 |
|
|
Sep 24 11:08:06 PM UTC 24 |
Sep 24 11:08:10 PM UTC 24 |
154469636 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.4091807981 |
|
|
Sep 24 11:07:59 PM UTC 24 |
Sep 24 11:08:11 PM UTC 24 |
534406094 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.3166037076 |
|
|
Sep 24 11:06:26 PM UTC 24 |
Sep 24 11:08:11 PM UTC 24 |
11654340542 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.1284663550 |
|
|
Sep 24 11:08:09 PM UTC 24 |
Sep 24 11:08:13 PM UTC 24 |
369900188 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.3358045310 |
|
|
Sep 24 11:05:27 PM UTC 24 |
Sep 24 11:08:14 PM UTC 24 |
68257255356 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_errors.624146506 |
|
|
Sep 24 11:07:56 PM UTC 24 |
Sep 24 11:08:14 PM UTC 24 |
293231768 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.3591810346 |
|
|
Sep 24 11:08:12 PM UTC 24 |
Sep 24 11:08:14 PM UTC 24 |
24165111 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3515162111 |
|
|
Sep 24 11:08:13 PM UTC 24 |
Sep 24 11:08:16 PM UTC 24 |
11776259 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.2562166534 |
|
|
Sep 24 11:08:12 PM UTC 24 |
Sep 24 11:08:16 PM UTC 24 |
495425233 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.1415521142 |
|
|
Sep 24 11:08:15 PM UTC 24 |
Sep 24 11:08:19 PM UTC 24 |
38060407 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.2554169894 |
|
|
Sep 24 11:08:07 PM UTC 24 |
Sep 24 11:08:19 PM UTC 24 |
222377995 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.3931998044 |
|
|
Sep 24 11:06:18 PM UTC 24 |
Sep 24 11:08:19 PM UTC 24 |
27563836730 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.854303784 |
|
|
Sep 24 11:08:01 PM UTC 24 |
Sep 24 11:08:20 PM UTC 24 |
3793085015 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.3111010930 |
|
|
Sep 24 11:08:10 PM UTC 24 |
Sep 24 11:08:21 PM UTC 24 |
874324990 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.3892505725 |
|
|
Sep 24 11:06:39 PM UTC 24 |
Sep 24 11:08:21 PM UTC 24 |
2920130877 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.503755355 |
|
|
Sep 24 11:08:10 PM UTC 24 |
Sep 24 11:08:22 PM UTC 24 |
502472378 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.1692678761 |
|
|
Sep 24 11:08:10 PM UTC 24 |
Sep 24 11:08:24 PM UTC 24 |
298698679 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.389993675 |
|
|
Sep 24 11:08:10 PM UTC 24 |
Sep 24 11:08:25 PM UTC 24 |
608439328 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.2171435258 |
|
|
Sep 24 11:08:16 PM UTC 24 |
Sep 24 11:08:25 PM UTC 24 |
864853206 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.3178713719 |
|
|
Sep 24 11:08:18 PM UTC 24 |
Sep 24 11:08:25 PM UTC 24 |
297532163 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.2643169127 |
|
|
Sep 24 11:08:23 PM UTC 24 |
Sep 24 11:08:25 PM UTC 24 |
12751533 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.3506176642 |
|
|
Sep 24 11:08:09 PM UTC 24 |
Sep 24 11:08:27 PM UTC 24 |
347644706 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2799630626 |
|
|
Sep 24 11:08:25 PM UTC 24 |
Sep 24 11:08:27 PM UTC 24 |
25329025 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.2301466330 |
|
|
Sep 24 11:08:23 PM UTC 24 |
Sep 24 11:08:27 PM UTC 24 |
34998109 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.1669653013 |
|
|
Sep 24 11:08:15 PM UTC 24 |
Sep 24 11:08:28 PM UTC 24 |
373546107 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_errors.26714268 |
|
|
Sep 24 11:08:09 PM UTC 24 |
Sep 24 11:08:30 PM UTC 24 |
1410923867 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.850140877 |
|
|
Sep 24 11:08:27 PM UTC 24 |
Sep 24 11:08:34 PM UTC 24 |
250275301 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.2483835090 |
|
|
Sep 24 11:07:53 PM UTC 24 |
Sep 24 11:08:32 PM UTC 24 |
930443010 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.4197612159 |
|
|
Sep 24 11:08:20 PM UTC 24 |
Sep 24 11:08:34 PM UTC 24 |
402210690 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.258128225 |
|
|
Sep 24 11:08:20 PM UTC 24 |
Sep 24 11:08:35 PM UTC 24 |
1443358137 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.1147896204 |
|
|
Sep 24 11:08:15 PM UTC 24 |
Sep 24 11:08:35 PM UTC 24 |
679341074 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.2200012813 |
|
|
Sep 24 11:08:28 PM UTC 24 |
Sep 24 11:08:35 PM UTC 24 |
534529712 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.3559120043 |
|
|
Sep 24 11:08:21 PM UTC 24 |
Sep 24 11:08:35 PM UTC 24 |
293562627 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.2025792423 |
|
|
Sep 24 11:08:20 PM UTC 24 |
Sep 24 11:08:36 PM UTC 24 |
308443308 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.2397227771 |
|
|
Sep 24 11:08:33 PM UTC 24 |
Sep 24 11:08:36 PM UTC 24 |
67026803 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.362218292 |
|
|
Sep 24 11:08:27 PM UTC 24 |
Sep 24 11:08:38 PM UTC 24 |
78718989 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3776474791 |
|
|
Sep 24 11:08:36 PM UTC 24 |
Sep 24 11:08:39 PM UTC 24 |
33574602 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.2998067513 |
|
|
Sep 24 11:08:07 PM UTC 24 |
Sep 24 11:08:40 PM UTC 24 |
941553734 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.941149229 |
|
|
Sep 24 11:08:34 PM UTC 24 |
Sep 24 11:08:40 PM UTC 24 |
423797986 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.2204277222 |
|
|
Sep 24 11:08:13 PM UTC 24 |
Sep 24 11:08:41 PM UTC 24 |
932566096 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.3575075052 |
|
|
Sep 24 11:08:37 PM UTC 24 |
Sep 24 11:08:41 PM UTC 24 |
215690882 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.3506104430 |
|
|
Sep 24 11:08:37 PM UTC 24 |
Sep 24 11:08:41 PM UTC 24 |
230415225 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.4003921531 |
|
|
Sep 24 11:08:28 PM UTC 24 |
Sep 24 11:08:43 PM UTC 24 |
300191864 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.2775510157 |
|
|
Sep 24 11:08:28 PM UTC 24 |
Sep 24 11:08:44 PM UTC 24 |
438584331 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.344173811 |
|
|
Sep 24 11:08:42 PM UTC 24 |
Sep 24 11:08:44 PM UTC 24 |
42148861 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3322172850 |
|
|
Sep 24 11:08:42 PM UTC 24 |
Sep 24 11:08:44 PM UTC 24 |
50914380 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.622852513 |
|
|
Sep 24 11:08:42 PM UTC 24 |
Sep 24 11:08:46 PM UTC 24 |
319809882 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.3013679186 |
|
|
Sep 24 11:08:31 PM UTC 24 |
Sep 24 11:08:46 PM UTC 24 |
1003826735 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.1818003849 |
|
|
Sep 24 11:08:29 PM UTC 24 |
Sep 24 11:08:47 PM UTC 24 |
1233019378 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.1915040649 |
|
|
Sep 24 11:07:21 PM UTC 24 |
Sep 24 11:08:47 PM UTC 24 |
2355490266 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.1821163974 |
|
|
Sep 24 11:08:39 PM UTC 24 |
Sep 24 11:08:49 PM UTC 24 |
286321246 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.3669105591 |
|
|
Sep 24 11:08:37 PM UTC 24 |
Sep 24 11:08:49 PM UTC 24 |
67613056 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_errors.1578344199 |
|
|
Sep 24 11:08:27 PM UTC 24 |
Sep 24 11:08:49 PM UTC 24 |
1137061456 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.83460397 |
|
|
Sep 24 11:08:45 PM UTC 24 |
Sep 24 11:08:50 PM UTC 24 |
101947888 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.828086564 |
|
|
Sep 24 11:08:47 PM UTC 24 |
Sep 24 11:08:51 PM UTC 24 |
100431692 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.2524759569 |
|
|
Sep 24 11:08:45 PM UTC 24 |
Sep 24 11:08:51 PM UTC 24 |
81492405 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.3141670308 |
|
|
Sep 24 11:08:38 PM UTC 24 |
Sep 24 11:08:52 PM UTC 24 |
1785484898 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.3293896056 |
|
|
Sep 24 11:08:51 PM UTC 24 |
Sep 24 11:08:55 PM UTC 24 |
98543563 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_errors.2309479080 |
|
|
Sep 24 11:08:37 PM UTC 24 |
Sep 24 11:08:55 PM UTC 24 |
1381302725 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.3978353260 |
|
|
Sep 24 11:08:37 PM UTC 24 |
Sep 24 11:08:55 PM UTC 24 |
9765311201 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3008097785 |
|
|
Sep 24 11:08:53 PM UTC 24 |
Sep 24 11:08:55 PM UTC 24 |
15047596 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.1929232636 |
|
|
Sep 24 11:09:17 PM UTC 24 |
Sep 24 11:09:28 PM UTC 24 |
173448539 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_errors.4008801357 |
|
|
Sep 24 11:08:46 PM UTC 24 |
Sep 24 11:08:56 PM UTC 24 |
651062233 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.266969793 |
|
|
Sep 24 11:09:25 PM UTC 24 |
Sep 24 11:09:32 PM UTC 24 |
105907799 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.2764388622 |
|
|
Sep 24 11:08:40 PM UTC 24 |
Sep 24 11:08:59 PM UTC 24 |
666183200 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.3009793612 |
|
|
Sep 24 11:07:22 PM UTC 24 |
Sep 24 11:08:59 PM UTC 24 |
40212911530 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.1036962588 |
|
|
Sep 24 11:08:57 PM UTC 24 |
Sep 24 11:09:00 PM UTC 24 |
33490065 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.2607295010 |
|
|
Sep 24 11:08:27 PM UTC 24 |
Sep 24 11:09:00 PM UTC 24 |
1680893623 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.4252708477 |
|
|
Sep 24 11:08:50 PM UTC 24 |
Sep 24 11:09:01 PM UTC 24 |
1290315299 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.2947040534 |
|
|
Sep 24 11:08:49 PM UTC 24 |
Sep 24 11:09:01 PM UTC 24 |
896371009 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.322908013 |
|
|
Sep 24 11:08:57 PM UTC 24 |
Sep 24 11:09:02 PM UTC 24 |
1214375893 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.1366888358 |
|
|
Sep 24 11:08:51 PM UTC 24 |
Sep 24 11:09:03 PM UTC 24 |
143665292 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.3477039053 |
|
|
Sep 24 11:09:01 PM UTC 24 |
Sep 24 11:09:03 PM UTC 24 |
20450811 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2415055659 |
|
|
Sep 24 11:09:02 PM UTC 24 |
Sep 24 11:09:04 PM UTC 24 |
27889443 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.2187018084 |
|
|
Sep 24 11:08:49 PM UTC 24 |
Sep 24 11:09:06 PM UTC 24 |
230999865 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.1639781626 |
|
|
Sep 24 11:08:47 PM UTC 24 |
Sep 24 11:09:06 PM UTC 24 |
2674452008 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.287292916 |
|
|
Sep 24 11:09:02 PM UTC 24 |
Sep 24 11:09:07 PM UTC 24 |
259827400 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.1859322518 |
|
|
Sep 24 11:08:56 PM UTC 24 |
Sep 24 11:09:08 PM UTC 24 |
77997820 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.2832763935 |
|
|
Sep 24 11:08:36 PM UTC 24 |
Sep 24 11:09:08 PM UTC 24 |
694957774 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.679464168 |
|
|
Sep 24 11:09:04 PM UTC 24 |
Sep 24 11:09:10 PM UTC 24 |
48956126 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_errors.875791678 |
|
|
Sep 24 11:08:57 PM UTC 24 |
Sep 24 11:09:10 PM UTC 24 |
846223572 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.968074476 |
|
|
Sep 24 11:09:07 PM UTC 24 |
Sep 24 11:09:12 PM UTC 24 |
342816439 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.4213261697 |
|
|
Sep 24 11:08:57 PM UTC 24 |
Sep 24 11:09:13 PM UTC 24 |
463617720 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.3737265525 |
|
|
Sep 24 11:06:59 PM UTC 24 |
Sep 24 11:09:13 PM UTC 24 |
17874681642 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.1632917749 |
|
|
Sep 24 11:09:11 PM UTC 24 |
Sep 24 11:09:14 PM UTC 24 |
80935094 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.2255980534 |
|
|
Sep 24 11:06:02 PM UTC 24 |
Sep 24 11:09:14 PM UTC 24 |
5016040274 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.2025636812 |
|
|
Sep 24 11:09:03 PM UTC 24 |
Sep 24 11:09:15 PM UTC 24 |
388892338 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.3539130377 |
|
|
Sep 24 11:08:59 PM UTC 24 |
Sep 24 11:09:15 PM UTC 24 |
1014123100 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.3697110796 |
|
|
Sep 24 11:08:59 PM UTC 24 |
Sep 24 11:09:15 PM UTC 24 |
1168879814 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.2699396387 |
|
|
Sep 24 11:09:19 PM UTC 24 |
Sep 24 11:09:29 PM UTC 24 |
237458700 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1032691707 |
|
|
Sep 24 11:09:15 PM UTC 24 |
Sep 24 11:09:17 PM UTC 24 |
23498022 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.2520193747 |
|
|
Sep 24 11:08:04 PM UTC 24 |
Sep 24 11:09:18 PM UTC 24 |
1857818233 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.3011729668 |
|
|
Sep 24 11:08:58 PM UTC 24 |
Sep 24 11:09:18 PM UTC 24 |
339961379 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.2805257086 |
|
|
Sep 24 11:09:13 PM UTC 24 |
Sep 24 11:09:19 PM UTC 24 |
66884565 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.3164971643 |
|
|
Sep 24 11:09:17 PM UTC 24 |
Sep 24 11:09:20 PM UTC 24 |
109015790 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.4274172564 |
|
|
Sep 24 11:08:44 PM UTC 24 |
Sep 24 11:09:21 PM UTC 24 |
1278724614 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.3267042060 |
|
|
Sep 24 11:09:08 PM UTC 24 |
Sep 24 11:09:22 PM UTC 24 |
711694964 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.2473808575 |
|
|
Sep 24 11:09:07 PM UTC 24 |
Sep 24 11:09:23 PM UTC 24 |
452514848 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.2361520191 |
|
|
Sep 24 11:09:21 PM UTC 24 |
Sep 24 11:09:23 PM UTC 24 |
57846933 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.3835279060 |
|
|
Sep 24 11:09:07 PM UTC 24 |
Sep 24 11:09:24 PM UTC 24 |
1076429053 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.2960192306 |
|
|
Sep 24 11:09:17 PM UTC 24 |
Sep 24 11:09:24 PM UTC 24 |
321864364 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.2043410492 |
|
|
Sep 24 11:09:15 PM UTC 24 |
Sep 24 11:09:24 PM UTC 24 |
90251362 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_errors.3136328041 |
|
|
Sep 24 11:09:06 PM UTC 24 |
Sep 24 11:09:24 PM UTC 24 |
953414446 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.1582170213 |
|
|
Sep 24 11:09:22 PM UTC 24 |
Sep 24 11:09:25 PM UTC 24 |
15984015 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.1093852461 |
|
|
Sep 24 11:09:08 PM UTC 24 |
Sep 24 11:09:25 PM UTC 24 |
1095558235 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2338327910 |
|
|
Sep 24 11:09:24 PM UTC 24 |
Sep 24 11:09:26 PM UTC 24 |
18845828 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.2836759378 |
|
|
Sep 24 11:08:31 PM UTC 24 |
Sep 24 11:09:27 PM UTC 24 |
2206803340 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.457600388 |
|
|
Sep 24 11:09:30 PM UTC 24 |
Sep 24 11:09:32 PM UTC 24 |
39830194 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.3852441481 |
|
|
Sep 24 11:10:21 PM UTC 24 |
Sep 24 11:10:29 PM UTC 24 |
86576955 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.2934690552 |
|
|
Sep 24 11:09:25 PM UTC 24 |
Sep 24 11:09:33 PM UTC 24 |
1576193320 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.344892580 |
|
|
Sep 24 11:09:19 PM UTC 24 |
Sep 24 11:09:34 PM UTC 24 |
246911012 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.2385202650 |
|
|
Sep 24 11:08:54 PM UTC 24 |
Sep 24 11:09:34 PM UTC 24 |
1489418695 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.4131704960 |
|
|
Sep 24 11:09:33 PM UTC 24 |
Sep 24 11:09:35 PM UTC 24 |
10682196 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.785665601 |
|
|
Sep 24 11:09:30 PM UTC 24 |
Sep 24 11:09:35 PM UTC 24 |
51310094 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.3712974920 |
|
|
Sep 24 11:09:19 PM UTC 24 |
Sep 24 11:09:36 PM UTC 24 |
482774456 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.2878775507 |
|
|
Sep 24 11:09:25 PM UTC 24 |
Sep 24 11:09:37 PM UTC 24 |
599968471 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.468650749 |
|
|
Sep 24 11:09:25 PM UTC 24 |
Sep 24 11:09:39 PM UTC 24 |
241349321 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.1541158198 |
|
|
Sep 24 11:09:27 PM UTC 24 |
Sep 24 11:09:40 PM UTC 24 |
472432003 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.2520198338 |
|
|
Sep 24 11:09:27 PM UTC 24 |
Sep 24 11:09:42 PM UTC 24 |
304593719 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.2189450651 |
|
|
Sep 24 11:09:03 PM UTC 24 |
Sep 24 11:09:42 PM UTC 24 |
262735201 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.42132643 |
|
|
Sep 24 11:09:17 PM UTC 24 |
Sep 24 11:09:42 PM UTC 24 |
1054827883 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.1082118234 |
|
|
Sep 24 11:09:25 PM UTC 24 |
Sep 24 11:09:43 PM UTC 24 |
392648516 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.380728496 |
|
|
Sep 24 11:09:35 PM UTC 24 |
Sep 24 11:09:43 PM UTC 24 |
126948047 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.2799770715 |
|
|
Sep 24 11:09:44 PM UTC 24 |
Sep 24 11:09:46 PM UTC 24 |
13198521 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1271023924 |
|
|
Sep 24 11:09:44 PM UTC 24 |
Sep 24 11:09:46 PM UTC 24 |
44654673 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.2442346493 |
|
|
Sep 24 11:09:44 PM UTC 24 |
Sep 24 11:09:47 PM UTC 24 |
52999279 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.1177024363 |
|
|
Sep 24 11:09:35 PM UTC 24 |
Sep 24 11:09:47 PM UTC 24 |
228463692 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1186398163 |
|
|
Sep 24 11:09:36 PM UTC 24 |
Sep 24 11:09:49 PM UTC 24 |
302913296 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.3220974486 |
|
|
Sep 24 11:09:38 PM UTC 24 |
Sep 24 11:09:50 PM UTC 24 |
222354818 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.3369323582 |
|
|
Sep 24 11:09:35 PM UTC 24 |
Sep 24 11:09:50 PM UTC 24 |
567073993 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.2952734577 |
|
|
Sep 24 11:09:27 PM UTC 24 |
Sep 24 11:09:52 PM UTC 24 |
3221018259 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.841243638 |
|
|
Sep 24 11:09:48 PM UTC 24 |
Sep 24 11:09:52 PM UTC 24 |
35530235 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.293251060 |
|
|
Sep 24 11:09:38 PM UTC 24 |
Sep 24 11:09:52 PM UTC 24 |
457261952 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.3563555191 |
|
|
Sep 24 11:09:15 PM UTC 24 |
Sep 24 11:09:52 PM UTC 24 |
321289028 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_errors.25479370 |
|
|
Sep 24 11:09:35 PM UTC 24 |
Sep 24 11:09:52 PM UTC 24 |
359569464 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.3352447151 |
|
|
Sep 24 11:09:24 PM UTC 24 |
Sep 24 11:09:52 PM UTC 24 |
1023014973 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.270528721 |
|
|
Sep 24 11:09:47 PM UTC 24 |
Sep 24 11:09:53 PM UTC 24 |
78235540 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.3128725225 |
|
|
Sep 24 11:09:36 PM UTC 24 |
Sep 24 11:09:53 PM UTC 24 |
3258852836 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.588435815 |
|
|
Sep 24 11:09:52 PM UTC 24 |
Sep 24 11:09:54 PM UTC 24 |
25640189 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.707584428 |
|
|
Sep 24 11:09:52 PM UTC 24 |
Sep 24 11:09:55 PM UTC 24 |
77132899 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.3766022115 |
|
|
Sep 24 11:09:33 PM UTC 24 |
Sep 24 11:09:55 PM UTC 24 |
205345994 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.906980911 |
|
|
Sep 24 11:09:44 PM UTC 24 |
Sep 24 11:09:56 PM UTC 24 |
1396788300 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.198763931 |
|
|
Sep 24 11:09:54 PM UTC 24 |
Sep 24 11:09:56 PM UTC 24 |
22343460 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.2344059312 |
|
|
Sep 24 11:09:48 PM UTC 24 |
Sep 24 11:09:57 PM UTC 24 |
261679653 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.3472269966 |
|
|
Sep 24 11:09:10 PM UTC 24 |
Sep 24 11:09:58 PM UTC 24 |
4076967262 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.848220298 |
|
|
Sep 24 11:09:57 PM UTC 24 |
Sep 24 11:09:59 PM UTC 24 |
90224635 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_errors.2670211858 |
|
|
Sep 24 11:09:47 PM UTC 24 |
Sep 24 11:10:00 PM UTC 24 |
205563186 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.878115478 |
|
|
Sep 24 11:09:58 PM UTC 24 |
Sep 24 11:10:00 PM UTC 24 |
36882046 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.3368377524 |
|
|
Sep 24 11:09:54 PM UTC 24 |
Sep 24 11:10:01 PM UTC 24 |
200148986 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.552329240 |
|
|
Sep 24 11:09:54 PM UTC 24 |
Sep 24 11:10:01 PM UTC 24 |
357116967 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.2837573443 |
|
|
Sep 24 11:09:58 PM UTC 24 |
Sep 24 11:10:03 PM UTC 24 |
63267579 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.306177978 |
|
|
Sep 24 11:09:50 PM UTC 24 |
Sep 24 11:10:03 PM UTC 24 |
388367492 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.2227601465 |
|
|
Sep 24 11:09:52 PM UTC 24 |
Sep 24 11:10:03 PM UTC 24 |
258590967 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.1028893952 |
|
|
Sep 24 11:09:54 PM UTC 24 |
Sep 24 11:10:05 PM UTC 24 |
975731791 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.1263184798 |
|
|
Sep 24 11:10:01 PM UTC 24 |
Sep 24 11:10:06 PM UTC 24 |
56741320 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.4042254953 |
|
|
Sep 24 11:10:01 PM UTC 24 |
Sep 24 11:10:06 PM UTC 24 |
127472535 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.705702080 |
|
|
Sep 24 11:07:12 PM UTC 24 |
Sep 24 11:10:06 PM UTC 24 |
3961823102 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.1764217188 |
|
|
Sep 24 11:09:54 PM UTC 24 |
Sep 24 11:10:08 PM UTC 24 |
890431441 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.814960785 |
|
|
Sep 24 11:09:50 PM UTC 24 |
Sep 24 11:10:08 PM UTC 24 |
1890528622 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.56476535 |
|
|
Sep 24 11:10:02 PM UTC 24 |
Sep 24 11:10:08 PM UTC 24 |
515058116 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.4116079574 |
|
|
Sep 24 11:09:55 PM UTC 24 |
Sep 24 11:10:09 PM UTC 24 |
222572048 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.2249604433 |
|
|
Sep 24 11:10:07 PM UTC 24 |
Sep 24 11:10:09 PM UTC 24 |
61725217 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.2744624393 |
|
|
Sep 24 11:09:54 PM UTC 24 |
Sep 24 11:10:10 PM UTC 24 |
393165937 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.3115517104 |
|
|
Sep 24 11:10:07 PM UTC 24 |
Sep 24 11:10:11 PM UTC 24 |
105081128 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2240380145 |
|
|
Sep 24 11:10:09 PM UTC 24 |
Sep 24 11:10:11 PM UTC 24 |
12853245 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.2887294410 |
|
|
Sep 24 11:10:27 PM UTC 24 |
Sep 24 11:10:30 PM UTC 24 |
52299517 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.1182674095 |
|
|
Sep 24 11:09:44 PM UTC 24 |
Sep 24 11:10:12 PM UTC 24 |
312191591 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_errors.2448096940 |
|
|
Sep 24 11:09:54 PM UTC 24 |
Sep 24 11:10:13 PM UTC 24 |
575622662 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.755613652 |
|
|
Sep 24 11:10:10 PM UTC 24 |
Sep 24 11:10:14 PM UTC 24 |
118480531 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.3691164764 |
|
|
Sep 24 11:10:04 PM UTC 24 |
Sep 24 11:10:15 PM UTC 24 |
752342676 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.3072717840 |
|
|
Sep 24 11:10:04 PM UTC 24 |
Sep 24 11:10:16 PM UTC 24 |
6210175723 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.938305721 |
|
|
Sep 24 11:10:09 PM UTC 24 |
Sep 24 11:10:17 PM UTC 24 |
65357114 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.3982416834 |
|
|
Sep 24 11:10:02 PM UTC 24 |
Sep 24 11:10:18 PM UTC 24 |
1827410308 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.4022888563 |
|
|
Sep 24 11:07:39 PM UTC 24 |
Sep 24 11:10:19 PM UTC 24 |
32717888547 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.1605967381 |
|
|
Sep 24 11:10:01 PM UTC 24 |
Sep 24 11:10:19 PM UTC 24 |
1718989938 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.3996919372 |
|
|
Sep 24 11:10:04 PM UTC 24 |
Sep 24 11:10:20 PM UTC 24 |
434621603 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.2758815555 |
|
|
Sep 24 11:09:55 PM UTC 24 |
Sep 24 11:10:20 PM UTC 24 |
3189601951 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.2888201640 |
|
|
Sep 24 11:10:18 PM UTC 24 |
Sep 24 11:10:20 PM UTC 24 |
70318432 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.601616954 |
|
|
Sep 24 11:09:54 PM UTC 24 |
Sep 24 11:10:21 PM UTC 24 |
1212979709 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.3713789580 |
|
|
Sep 24 11:10:18 PM UTC 24 |
Sep 24 11:10:22 PM UTC 24 |
195883175 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1779856503 |
|
|
Sep 24 11:10:21 PM UTC 24 |
Sep 24 11:10:23 PM UTC 24 |
41475492 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_errors.2692845126 |
|
|
Sep 24 11:10:10 PM UTC 24 |
Sep 24 11:10:23 PM UTC 24 |
1141680677 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.131109066 |
|
|
Sep 24 11:10:22 PM UTC 24 |
Sep 24 11:10:26 PM UTC 24 |
305543989 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.1379559470 |
|
|
Sep 24 11:10:21 PM UTC 24 |
Sep 24 11:10:26 PM UTC 24 |
571338479 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.367395723 |
|
|
Sep 24 11:10:13 PM UTC 24 |
Sep 24 11:10:27 PM UTC 24 |
282295268 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.2232297462 |
|
|
Sep 24 11:10:11 PM UTC 24 |
Sep 24 11:10:28 PM UTC 24 |
1109795727 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.559482811 |
|
|
Sep 24 11:10:13 PM UTC 24 |
Sep 24 11:10:28 PM UTC 24 |
455394337 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.1600111088 |
|
|
Sep 24 11:08:51 PM UTC 24 |
Sep 24 11:10:29 PM UTC 24 |
9820477070 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.4189028624 |
|
|
Sep 24 11:10:14 PM UTC 24 |
Sep 24 11:10:31 PM UTC 24 |
387268079 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1355015102 |
|
|
Sep 24 11:10:29 PM UTC 24 |
Sep 24 11:10:31 PM UTC 24 |
22660214 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.587800288 |
|
|
Sep 24 11:10:11 PM UTC 24 |
Sep 24 11:10:31 PM UTC 24 |
449396115 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.3197441214 |
|
|
Sep 24 11:10:09 PM UTC 24 |
Sep 24 11:10:32 PM UTC 24 |
404475068 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_errors.4285439380 |
|
|
Sep 24 11:10:21 PM UTC 24 |
Sep 24 11:10:35 PM UTC 24 |
1291194306 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.2850898893 |
|
|
Sep 24 11:10:29 PM UTC 24 |
Sep 24 11:10:35 PM UTC 24 |
52606501 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.1624388015 |
|
|
Sep 24 11:10:30 PM UTC 24 |
Sep 24 11:10:36 PM UTC 24 |
65483334 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.738609822 |
|
|
Sep 24 11:10:00 PM UTC 24 |
Sep 24 11:10:37 PM UTC 24 |
279008487 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.3662271433 |
|
|
Sep 24 11:10:22 PM UTC 24 |
Sep 24 11:10:38 PM UTC 24 |
372542908 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.3890740111 |
|
|
Sep 24 11:10:24 PM UTC 24 |
Sep 24 11:10:39 PM UTC 24 |
545512731 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2617987715 |
|
|
Sep 24 11:10:25 PM UTC 24 |
Sep 24 11:10:39 PM UTC 24 |
380765580 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.567726 |
|
|
Sep 24 11:11:13 PM UTC 24 |
Sep 24 11:11:37 PM UTC 24 |
3861542801 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.2809796577 |
|
|
Sep 24 11:10:37 PM UTC 24 |
Sep 24 11:10:39 PM UTC 24 |
48409090 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.3711163103 |
|
|
Sep 24 11:10:22 PM UTC 24 |
Sep 24 11:10:40 PM UTC 24 |
985891633 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.320586767 |
|
|
Sep 24 11:10:38 PM UTC 24 |
Sep 24 11:10:41 PM UTC 24 |
12410784 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.3804566282 |
|
|
Sep 24 11:10:38 PM UTC 24 |
Sep 24 11:10:41 PM UTC 24 |
35244609 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.3232480433 |
|
|
Sep 24 11:10:32 PM UTC 24 |
Sep 24 11:10:42 PM UTC 24 |
303084229 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.658286555 |
|
|
Sep 24 11:10:33 PM UTC 24 |
Sep 24 11:10:42 PM UTC 24 |
1012553727 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.3385608461 |
|
|
Sep 24 11:10:30 PM UTC 24 |
Sep 24 11:10:43 PM UTC 24 |
1040250821 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.1900733412 |
|
|
Sep 24 11:09:28 PM UTC 24 |
Sep 24 11:10:43 PM UTC 24 |
12429138222 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.3150409619 |
|
|
Sep 24 11:10:40 PM UTC 24 |
Sep 24 11:10:44 PM UTC 24 |
55366596 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.3206008715 |
|
|
Sep 24 11:10:32 PM UTC 24 |
Sep 24 11:10:44 PM UTC 24 |
217142429 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3300372189 |
|
|
Sep 24 11:09:52 PM UTC 24 |
Sep 24 11:10:47 PM UTC 24 |
6779335810 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.413302745 |
|
|
Sep 24 11:10:45 PM UTC 24 |
Sep 24 11:10:48 PM UTC 24 |
18120121 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_errors.337950103 |
|
|
Sep 24 11:10:30 PM UTC 24 |
Sep 24 11:10:49 PM UTC 24 |
724964745 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.924379553 |
|
|
Sep 24 11:10:47 PM UTC 24 |
Sep 24 11:10:49 PM UTC 24 |
46123293 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.478088118 |
|
|
Sep 24 11:10:34 PM UTC 24 |
Sep 24 11:10:49 PM UTC 24 |
1134249012 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.3619624711 |
|
|
Sep 24 11:10:45 PM UTC 24 |
Sep 24 11:10:50 PM UTC 24 |
50985604 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.4192125901 |
|
|
Sep 24 11:10:33 PM UTC 24 |
Sep 24 11:10:51 PM UTC 24 |
278541498 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.4108968719 |
|
|
Sep 24 11:10:40 PM UTC 24 |
Sep 24 11:10:52 PM UTC 24 |
91641287 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.889466059 |
|
|
Sep 24 11:10:21 PM UTC 24 |
Sep 24 11:10:52 PM UTC 24 |
1069925939 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.3482643375 |
|
|
Sep 24 11:10:42 PM UTC 24 |
Sep 24 11:10:53 PM UTC 24 |
328266112 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.3204834721 |
|
|
Sep 24 11:10:40 PM UTC 24 |
Sep 24 11:10:54 PM UTC 24 |
1332023193 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.2903278893 |
|
|
Sep 24 11:10:41 PM UTC 24 |
Sep 24 11:10:55 PM UTC 24 |
368571424 ps |