| T810 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.1277510608 |
|
|
Sep 24 11:10:50 PM UTC 24 |
Sep 24 11:10:55 PM UTC 24 |
62167998 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.1061127120 |
|
|
Sep 24 11:10:29 PM UTC 24 |
Sep 24 11:10:56 PM UTC 24 |
272289005 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.169711268 |
|
|
Sep 24 11:10:56 PM UTC 24 |
Sep 24 11:10:58 PM UTC 24 |
80036061 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.2745512280 |
|
|
Sep 24 11:10:42 PM UTC 24 |
Sep 24 11:10:58 PM UTC 24 |
1622046030 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.19323268 |
|
|
Sep 24 11:10:44 PM UTC 24 |
Sep 24 11:10:59 PM UTC 24 |
400733768 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2666531155 |
|
|
Sep 24 11:10:57 PM UTC 24 |
Sep 24 11:10:59 PM UTC 24 |
11005478 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.2819955493 |
|
|
Sep 24 11:10:49 PM UTC 24 |
Sep 24 11:11:01 PM UTC 24 |
75554509 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.1430008652 |
|
|
Sep 24 11:10:42 PM UTC 24 |
Sep 24 11:11:01 PM UTC 24 |
4507131475 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.39573856 |
|
|
Sep 24 11:10:56 PM UTC 24 |
Sep 24 11:11:02 PM UTC 24 |
487711184 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.3100932210 |
|
|
Sep 24 11:10:50 PM UTC 24 |
Sep 24 11:11:03 PM UTC 24 |
425416459 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.2554820211 |
|
|
Sep 24 11:11:00 PM UTC 24 |
Sep 24 11:11:04 PM UTC 24 |
46641486 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.2339600343 |
|
|
Sep 24 11:10:53 PM UTC 24 |
Sep 24 11:11:06 PM UTC 24 |
973270272 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.1510098708 |
|
|
Sep 24 11:10:59 PM UTC 24 |
Sep 24 11:11:06 PM UTC 24 |
259196546 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.1435912696 |
|
|
Sep 24 11:10:50 PM UTC 24 |
Sep 24 11:11:06 PM UTC 24 |
711124643 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.507520765 |
|
|
Sep 24 11:11:02 PM UTC 24 |
Sep 24 11:11:07 PM UTC 24 |
590950632 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.1029181952 |
|
|
Sep 24 11:10:53 PM UTC 24 |
Sep 24 11:11:08 PM UTC 24 |
1147981464 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.4267379310 |
|
|
Sep 24 11:11:08 PM UTC 24 |
Sep 24 11:11:11 PM UTC 24 |
36163023 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.433166858 |
|
|
Sep 24 11:11:08 PM UTC 24 |
Sep 24 11:11:11 PM UTC 24 |
27562053 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.1232725447 |
|
|
Sep 24 11:10:52 PM UTC 24 |
Sep 24 11:11:11 PM UTC 24 |
2822434657 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2441983843 |
|
|
Sep 24 11:08:42 PM UTC 24 |
Sep 24 11:11:12 PM UTC 24 |
6784984112 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3582805700 |
|
|
Sep 24 11:09:20 PM UTC 24 |
Sep 24 11:11:12 PM UTC 24 |
15459281921 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.3857029229 |
|
|
Sep 24 11:11:08 PM UTC 24 |
Sep 24 11:11:14 PM UTC 24 |
49782836 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.1577771554 |
|
|
Sep 24 11:10:49 PM UTC 24 |
Sep 24 11:11:14 PM UTC 24 |
1272061658 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.1102251024 |
|
|
Sep 24 11:10:40 PM UTC 24 |
Sep 24 11:11:15 PM UTC 24 |
538535870 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.2812793690 |
|
|
Sep 24 11:11:03 PM UTC 24 |
Sep 24 11:11:16 PM UTC 24 |
452127313 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.565289558 |
|
|
Sep 24 11:11:13 PM UTC 24 |
Sep 24 11:11:17 PM UTC 24 |
66238163 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.1393355191 |
|
|
Sep 24 11:11:01 PM UTC 24 |
Sep 24 11:11:17 PM UTC 24 |
329839727 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.3067080010 |
|
|
Sep 24 11:11:02 PM UTC 24 |
Sep 24 11:11:18 PM UTC 24 |
1302074489 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.251437254 |
|
|
Sep 24 11:11:03 PM UTC 24 |
Sep 24 11:11:20 PM UTC 24 |
451009036 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.1236517302 |
|
|
Sep 24 11:10:50 PM UTC 24 |
Sep 24 11:11:20 PM UTC 24 |
2654809816 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.1337158717 |
|
|
Sep 24 11:11:19 PM UTC 24 |
Sep 24 11:11:21 PM UTC 24 |
51322795 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.3343680002 |
|
|
Sep 24 11:09:57 PM UTC 24 |
Sep 24 11:11:39 PM UTC 24 |
38005634169 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.1107918938 |
|
|
Sep 24 11:10:59 PM UTC 24 |
Sep 24 11:11:23 PM UTC 24 |
752737749 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.2147261789 |
|
|
Sep 24 11:11:12 PM UTC 24 |
Sep 24 11:11:23 PM UTC 24 |
331070479 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.1376785410 |
|
|
Sep 24 11:11:04 PM UTC 24 |
Sep 24 11:11:24 PM UTC 24 |
1542886164 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.1501338142 |
|
|
Sep 24 11:11:14 PM UTC 24 |
Sep 24 11:11:28 PM UTC 24 |
1212971771 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.624287862 |
|
|
Sep 24 11:11:17 PM UTC 24 |
Sep 24 11:11:28 PM UTC 24 |
851936866 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.3092814127 |
|
|
Sep 24 11:11:16 PM UTC 24 |
Sep 24 11:11:29 PM UTC 24 |
317526085 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.3139021964 |
|
|
Sep 24 11:09:57 PM UTC 24 |
Sep 24 11:11:29 PM UTC 24 |
19544745039 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.1331985983 |
|
|
Sep 24 11:06:47 PM UTC 24 |
Sep 24 11:11:29 PM UTC 24 |
7531943757 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.340622654 |
|
|
Sep 24 11:11:13 PM UTC 24 |
Sep 24 11:11:29 PM UTC 24 |
912833852 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.465362968 |
|
|
Sep 24 11:09:40 PM UTC 24 |
Sep 24 11:11:32 PM UTC 24 |
25645748951 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.982677609 |
|
|
Sep 24 11:11:17 PM UTC 24 |
Sep 24 11:11:33 PM UTC 24 |
1227676283 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.877399009 |
|
|
Sep 24 11:11:11 PM UTC 24 |
Sep 24 11:11:35 PM UTC 24 |
748841885 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.3781746725 |
|
|
Sep 24 11:07:50 PM UTC 24 |
Sep 24 11:11:46 PM UTC 24 |
5869956465 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.3179341265 |
|
|
Sep 24 11:10:36 PM UTC 24 |
Sep 24 11:11:58 PM UTC 24 |
3009651663 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.1580252832 |
|
|
Sep 24 11:10:07 PM UTC 24 |
Sep 24 11:11:59 PM UTC 24 |
2711883694 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.1188782172 |
|
|
Sep 24 11:10:27 PM UTC 24 |
Sep 24 11:12:04 PM UTC 24 |
2701513083 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.811683108 |
|
|
Sep 24 11:08:42 PM UTC 24 |
Sep 24 11:12:22 PM UTC 24 |
42417992815 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.1613588013 |
|
|
Sep 24 11:10:54 PM UTC 24 |
Sep 24 11:12:50 PM UTC 24 |
6905985387 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.4017944236 |
|
|
Sep 24 11:04:11 PM UTC 24 |
Sep 24 11:12:50 PM UTC 24 |
35886529034 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.3327568008 |
|
|
Sep 24 11:10:15 PM UTC 24 |
Sep 24 11:13:06 PM UTC 24 |
4429412809 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.644022259 |
|
|
Sep 24 11:09:28 PM UTC 24 |
Sep 24 11:13:20 PM UTC 24 |
8209591591 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.2009032681 |
|
|
Sep 24 11:08:12 PM UTC 24 |
Sep 24 11:13:21 PM UTC 24 |
31729385152 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.2109593664 |
|
|
Sep 24 11:09:52 PM UTC 24 |
Sep 24 11:13:27 PM UTC 24 |
12109368153 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.1737404805 |
|
|
Sep 24 11:09:19 PM UTC 24 |
Sep 24 11:13:34 PM UTC 24 |
28912182040 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.4025575454 |
|
|
Sep 24 11:10:25 PM UTC 24 |
Sep 24 11:13:50 PM UTC 24 |
7540886356 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.3988760061 |
|
|
Sep 24 11:11:17 PM UTC 24 |
Sep 24 11:13:52 PM UTC 24 |
6995783652 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.1151634149 |
|
|
Sep 24 11:08:50 PM UTC 24 |
Sep 24 11:14:36 PM UTC 24 |
6872987046 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.985652683 |
|
|
Sep 24 11:06:02 PM UTC 24 |
Sep 24 11:15:30 PM UTC 24 |
17072708570 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.1886399531 |
|
|
Sep 24 11:01:01 PM UTC 24 |
Sep 24 11:15:31 PM UTC 24 |
114122837655 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.2233487116 |
|
|
Sep 24 11:11:07 PM UTC 24 |
Sep 24 11:15:40 PM UTC 24 |
49847869416 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2337729385 |
|
|
Sep 24 11:09:01 PM UTC 24 |
Sep 24 11:16:35 PM UTC 24 |
58231866236 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.3475681072 |
|
|
Sep 24 11:08:02 PM UTC 24 |
Sep 24 11:20:11 PM UTC 24 |
17347391398 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.1457165300 |
|
|
Sep 24 11:10:44 PM UTC 24 |
Sep 24 11:20:13 PM UTC 24 |
71634848575 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.422294932 |
|
|
Sep 24 11:10:06 PM UTC 24 |
Sep 24 11:20:33 PM UTC 24 |
64945933703 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.716200288 |
|
|
Sep 24 10:57:38 PM UTC 24 |
Sep 24 10:57:42 PM UTC 24 |
389866759 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3865870993 |
|
|
Sep 24 10:57:40 PM UTC 24 |
Sep 24 10:57:43 PM UTC 24 |
18377949 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3764618770 |
|
|
Sep 24 10:57:38 PM UTC 24 |
Sep 24 10:57:43 PM UTC 24 |
438372008 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2954278266 |
|
|
Sep 24 10:57:41 PM UTC 24 |
Sep 24 10:57:44 PM UTC 24 |
32001344 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1842858616 |
|
|
Sep 24 10:57:40 PM UTC 24 |
Sep 24 10:57:44 PM UTC 24 |
137695417 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2671745188 |
|
|
Sep 24 10:57:42 PM UTC 24 |
Sep 24 10:57:46 PM UTC 24 |
204215301 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2158834105 |
|
|
Sep 24 10:57:44 PM UTC 24 |
Sep 24 10:57:46 PM UTC 24 |
15499830 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.4171589794 |
|
|
Sep 24 10:57:44 PM UTC 24 |
Sep 24 10:57:46 PM UTC 24 |
45848009 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1877490107 |
|
|
Sep 24 10:57:44 PM UTC 24 |
Sep 24 10:57:47 PM UTC 24 |
26571955 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.674893182 |
|
|
Sep 24 10:57:45 PM UTC 24 |
Sep 24 10:57:48 PM UTC 24 |
54491022 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.4212410920 |
|
|
Sep 24 10:57:45 PM UTC 24 |
Sep 24 10:57:48 PM UTC 24 |
244142191 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3315508851 |
|
|
Sep 24 10:57:44 PM UTC 24 |
Sep 24 10:57:49 PM UTC 24 |
242372423 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.942040607 |
|
|
Sep 24 10:57:47 PM UTC 24 |
Sep 24 10:57:50 PM UTC 24 |
162221826 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.318256837 |
|
|
Sep 24 10:57:47 PM UTC 24 |
Sep 24 10:57:51 PM UTC 24 |
270232341 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3733787785 |
|
|
Sep 24 10:57:47 PM UTC 24 |
Sep 24 10:57:51 PM UTC 24 |
94667377 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.389002762 |
|
|
Sep 24 10:57:49 PM UTC 24 |
Sep 24 10:57:52 PM UTC 24 |
257881360 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2707318500 |
|
|
Sep 24 10:57:40 PM UTC 24 |
Sep 24 10:57:53 PM UTC 24 |
484049507 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.567497099 |
|
|
Sep 24 10:57:51 PM UTC 24 |
Sep 24 10:57:54 PM UTC 24 |
37607250 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3242643563 |
|
|
Sep 24 10:57:49 PM UTC 24 |
Sep 24 10:57:55 PM UTC 24 |
396037328 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.713996516 |
|
|
Sep 24 10:57:53 PM UTC 24 |
Sep 24 10:57:55 PM UTC 24 |
40660988 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3088914498 |
|
|
Sep 24 10:57:38 PM UTC 24 |
Sep 24 10:57:56 PM UTC 24 |
3984892986 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1057407457 |
|
|
Sep 24 10:57:54 PM UTC 24 |
Sep 24 10:57:56 PM UTC 24 |
12452375 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.544860374 |
|
|
Sep 24 10:57:55 PM UTC 24 |
Sep 24 10:57:58 PM UTC 24 |
198955625 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.737016335 |
|
|
Sep 24 10:57:53 PM UTC 24 |
Sep 24 10:57:59 PM UTC 24 |
365946217 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.537070227 |
|
|
Sep 24 10:58:18 PM UTC 24 |
Sep 24 10:58:23 PM UTC 24 |
494747122 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1898111306 |
|
|
Sep 24 10:57:56 PM UTC 24 |
Sep 24 10:57:59 PM UTC 24 |
17902034 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.755992743 |
|
|
Sep 24 10:57:56 PM UTC 24 |
Sep 24 10:57:59 PM UTC 24 |
44570151 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4150842853 |
|
|
Sep 24 10:57:51 PM UTC 24 |
Sep 24 10:57:59 PM UTC 24 |
117951504 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.746934793 |
|
|
Sep 24 10:57:57 PM UTC 24 |
Sep 24 10:58:00 PM UTC 24 |
29213883 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.710431544 |
|
|
Sep 24 10:57:57 PM UTC 24 |
Sep 24 10:58:01 PM UTC 24 |
77721845 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2589725070 |
|
|
Sep 24 10:57:48 PM UTC 24 |
Sep 24 10:58:02 PM UTC 24 |
9088771905 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4262280231 |
|
|
Sep 24 10:57:59 PM UTC 24 |
Sep 24 10:58:02 PM UTC 24 |
67886623 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.780331828 |
|
|
Sep 24 10:58:00 PM UTC 24 |
Sep 24 10:58:04 PM UTC 24 |
71135774 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3774192093 |
|
|
Sep 24 10:58:01 PM UTC 24 |
Sep 24 10:58:04 PM UTC 24 |
47739356 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1675843574 |
|
|
Sep 24 10:58:01 PM UTC 24 |
Sep 24 10:58:04 PM UTC 24 |
30312920 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2374959379 |
|
|
Sep 24 10:58:03 PM UTC 24 |
Sep 24 10:58:05 PM UTC 24 |
14688971 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.523618490 |
|
|
Sep 24 10:58:03 PM UTC 24 |
Sep 24 10:58:06 PM UTC 24 |
68776657 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3731971967 |
|
|
Sep 24 10:58:02 PM UTC 24 |
Sep 24 10:58:06 PM UTC 24 |
121649015 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4102444375 |
|
|
Sep 24 10:57:48 PM UTC 24 |
Sep 24 10:58:06 PM UTC 24 |
4693699980 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2561194492 |
|
|
Sep 24 10:58:01 PM UTC 24 |
Sep 24 10:58:07 PM UTC 24 |
127380261 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2114843523 |
|
|
Sep 24 10:58:04 PM UTC 24 |
Sep 24 10:58:07 PM UTC 24 |
156084909 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1886026814 |
|
|
Sep 24 10:58:04 PM UTC 24 |
Sep 24 10:58:07 PM UTC 24 |
111593360 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1827931114 |
|
|
Sep 24 10:58:05 PM UTC 24 |
Sep 24 10:58:08 PM UTC 24 |
24906765 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1276289352 |
|
|
Sep 24 10:58:06 PM UTC 24 |
Sep 24 10:58:09 PM UTC 24 |
19524644 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2522830923 |
|
|
Sep 24 10:58:06 PM UTC 24 |
Sep 24 10:58:10 PM UTC 24 |
175510175 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1348447607 |
|
|
Sep 24 10:58:06 PM UTC 24 |
Sep 24 10:58:10 PM UTC 24 |
319997524 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1299911106 |
|
|
Sep 24 10:58:08 PM UTC 24 |
Sep 24 10:58:11 PM UTC 24 |
82365674 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3401181092 |
|
|
Sep 24 10:58:08 PM UTC 24 |
Sep 24 10:58:13 PM UTC 24 |
406207684 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3532932892 |
|
|
Sep 24 10:58:09 PM UTC 24 |
Sep 24 10:58:13 PM UTC 24 |
124680219 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.664154579 |
|
|
Sep 24 10:58:11 PM UTC 24 |
Sep 24 10:58:13 PM UTC 24 |
50416736 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2302872203 |
|
|
Sep 24 10:58:11 PM UTC 24 |
Sep 24 10:58:14 PM UTC 24 |
14682378 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3257521874 |
|
|
Sep 24 10:58:11 PM UTC 24 |
Sep 24 10:58:14 PM UTC 24 |
54541109 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3593146134 |
|
|
Sep 24 10:58:10 PM UTC 24 |
Sep 24 10:58:15 PM UTC 24 |
81272422 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.169089170 |
|
|
Sep 24 10:57:59 PM UTC 24 |
Sep 24 10:58:15 PM UTC 24 |
4411839196 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3023198974 |
|
|
Sep 24 10:58:09 PM UTC 24 |
Sep 24 10:58:16 PM UTC 24 |
157605209 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1184131969 |
|
|
Sep 24 10:58:13 PM UTC 24 |
Sep 24 10:58:16 PM UTC 24 |
46460683 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.365586479 |
|
|
Sep 24 10:58:13 PM UTC 24 |
Sep 24 10:58:16 PM UTC 24 |
25345938 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2777736128 |
|
|
Sep 24 10:58:14 PM UTC 24 |
Sep 24 10:58:17 PM UTC 24 |
71130877 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2499965274 |
|
|
Sep 24 10:58:14 PM UTC 24 |
Sep 24 10:58:19 PM UTC 24 |
668294527 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.470779639 |
|
|
Sep 24 10:58:17 PM UTC 24 |
Sep 24 10:58:19 PM UTC 24 |
28621090 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1881077850 |
|
|
Sep 24 10:58:18 PM UTC 24 |
Sep 24 10:58:20 PM UTC 24 |
35734483 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3555852145 |
|
|
Sep 24 10:58:16 PM UTC 24 |
Sep 24 10:58:21 PM UTC 24 |
224261550 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.210949964 |
|
|
Sep 24 10:58:17 PM UTC 24 |
Sep 24 10:58:21 PM UTC 24 |
765772143 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1338236891 |
|
|
Sep 24 10:58:20 PM UTC 24 |
Sep 24 10:58:22 PM UTC 24 |
99350128 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2758297566 |
|
|
Sep 24 10:58:17 PM UTC 24 |
Sep 24 10:58:23 PM UTC 24 |
1085371318 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2128180481 |
|
|
Sep 24 10:58:21 PM UTC 24 |
Sep 24 10:58:24 PM UTC 24 |
22314962 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2617496705 |
|
|
Sep 24 10:58:07 PM UTC 24 |
Sep 24 10:58:24 PM UTC 24 |
1933557971 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1940984144 |
|
|
Sep 24 10:58:21 PM UTC 24 |
Sep 24 10:58:24 PM UTC 24 |
25125545 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.778589397 |
|
|
Sep 24 10:58:20 PM UTC 24 |
Sep 24 10:58:25 PM UTC 24 |
116647143 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1378338959 |
|
|
Sep 24 10:58:21 PM UTC 24 |
Sep 24 10:58:25 PM UTC 24 |
175470140 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1337140541 |
|
|
Sep 24 10:58:23 PM UTC 24 |
Sep 24 10:58:25 PM UTC 24 |
170213275 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2668977212 |
|
|
Sep 24 10:57:59 PM UTC 24 |
Sep 24 10:58:26 PM UTC 24 |
2914114059 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.813509325 |
|
|
Sep 24 10:58:17 PM UTC 24 |
Sep 24 10:58:26 PM UTC 24 |
554831529 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3229169174 |
|
|
Sep 24 10:58:24 PM UTC 24 |
Sep 24 10:58:27 PM UTC 24 |
35609896 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2406139944 |
|
|
Sep 24 10:58:25 PM UTC 24 |
Sep 24 10:58:28 PM UTC 24 |
19922994 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.722573264 |
|
|
Sep 24 10:58:25 PM UTC 24 |
Sep 24 10:58:28 PM UTC 24 |
72717663 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3827614366 |
|
|
Sep 24 10:58:25 PM UTC 24 |
Sep 24 10:58:29 PM UTC 24 |
228372009 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2472497486 |
|
|
Sep 24 10:58:25 PM UTC 24 |
Sep 24 10:58:29 PM UTC 24 |
1071166265 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3980587041 |
|
|
Sep 24 10:58:25 PM UTC 24 |
Sep 24 10:58:29 PM UTC 24 |
273893820 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3990299003 |
|
|
Sep 24 10:58:27 PM UTC 24 |
Sep 24 10:58:30 PM UTC 24 |
14920039 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.845706789 |
|
|
Sep 24 10:58:27 PM UTC 24 |
Sep 24 10:58:30 PM UTC 24 |
374087690 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1429890459 |
|
|
Sep 24 10:58:26 PM UTC 24 |
Sep 24 10:58:30 PM UTC 24 |
292754850 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1790872780 |
|
|
Sep 24 10:58:28 PM UTC 24 |
Sep 24 10:58:31 PM UTC 24 |
66719876 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3741551877 |
|
|
Sep 24 10:58:24 PM UTC 24 |
Sep 24 10:58:31 PM UTC 24 |
231430902 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1444957539 |
|
|
Sep 24 10:58:29 PM UTC 24 |
Sep 24 10:58:32 PM UTC 24 |
217451132 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2456472518 |
|
|
Sep 24 10:58:29 PM UTC 24 |
Sep 24 10:58:32 PM UTC 24 |
236467515 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.575304503 |
|
|
Sep 24 10:58:08 PM UTC 24 |
Sep 24 10:58:33 PM UTC 24 |
868707329 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2823750023 |
|
|
Sep 24 10:58:30 PM UTC 24 |
Sep 24 10:58:33 PM UTC 24 |
71516344 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1385751961 |
|
|
Sep 24 10:58:31 PM UTC 24 |
Sep 24 10:58:35 PM UTC 24 |
238521651 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4131718161 |
|
|
Sep 24 10:58:32 PM UTC 24 |
Sep 24 10:58:35 PM UTC 24 |
59072100 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2548384836 |
|
|
Sep 24 10:58:32 PM UTC 24 |
Sep 24 10:58:35 PM UTC 24 |
18023012 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.10049997 |
|
|
Sep 24 10:58:32 PM UTC 24 |
Sep 24 10:58:36 PM UTC 24 |
120279520 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2544514426 |
|
|
Sep 24 10:58:31 PM UTC 24 |
Sep 24 10:58:36 PM UTC 24 |
207371907 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3890233735 |
|
|
Sep 24 10:58:30 PM UTC 24 |
Sep 24 10:58:36 PM UTC 24 |
962967173 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1665374329 |
|
|
Sep 24 10:58:34 PM UTC 24 |
Sep 24 10:58:36 PM UTC 24 |
144320100 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.873622273 |
|
|
Sep 24 10:58:31 PM UTC 24 |
Sep 24 10:58:37 PM UTC 24 |
102554662 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1998056395 |
|
|
Sep 24 10:58:32 PM UTC 24 |
Sep 24 10:58:38 PM UTC 24 |
373308306 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.4119890378 |
|
|
Sep 24 10:58:34 PM UTC 24 |
Sep 24 10:58:38 PM UTC 24 |
1068154488 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3891385323 |
|
|
Sep 24 10:58:30 PM UTC 24 |
Sep 24 10:58:38 PM UTC 24 |
354009563 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2784135881 |
|
|
Sep 24 10:58:36 PM UTC 24 |
Sep 24 10:58:39 PM UTC 24 |
36098522 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1226093987 |
|
|
Sep 24 10:58:25 PM UTC 24 |
Sep 24 10:58:39 PM UTC 24 |
3498578389 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1518877727 |
|
|
Sep 24 10:58:37 PM UTC 24 |
Sep 24 10:58:40 PM UTC 24 |
16870412 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3989830885 |
|
|
Sep 24 10:58:36 PM UTC 24 |
Sep 24 10:58:40 PM UTC 24 |
246244178 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2755342621 |
|
|
Sep 24 10:58:38 PM UTC 24 |
Sep 24 10:58:41 PM UTC 24 |
89844155 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2802631007 |
|
|
Sep 24 10:58:37 PM UTC 24 |
Sep 24 10:58:42 PM UTC 24 |
638903011 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1178218769 |
|
|
Sep 24 10:58:37 PM UTC 24 |
Sep 24 10:58:42 PM UTC 24 |
33529414 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3585237603 |
|
|
Sep 24 10:58:38 PM UTC 24 |
Sep 24 10:58:42 PM UTC 24 |
176542038 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4044957992 |
|
|
Sep 24 10:58:37 PM UTC 24 |
Sep 24 10:58:42 PM UTC 24 |
320242253 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1062228831 |
|
|
Sep 24 10:58:39 PM UTC 24 |
Sep 24 10:58:43 PM UTC 24 |
75516973 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3617651966 |
|
|
Sep 24 10:58:41 PM UTC 24 |
Sep 24 10:58:43 PM UTC 24 |
89669525 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.889863031 |
|
|
Sep 24 10:58:39 PM UTC 24 |
Sep 24 10:58:44 PM UTC 24 |
158880596 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1320442787 |
|
|
Sep 24 10:58:42 PM UTC 24 |
Sep 24 10:58:45 PM UTC 24 |
48496987 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.15169386 |
|
|
Sep 24 10:58:43 PM UTC 24 |
Sep 24 10:58:45 PM UTC 24 |
49405663 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3846257558 |
|
|
Sep 24 10:58:43 PM UTC 24 |
Sep 24 10:58:46 PM UTC 24 |
47799289 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.567449809 |
|
|
Sep 24 10:58:41 PM UTC 24 |
Sep 24 10:58:46 PM UTC 24 |
460088528 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2366825932 |
|
|
Sep 24 10:58:34 PM UTC 24 |
Sep 24 10:58:46 PM UTC 24 |
714052943 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3556611331 |
|
|
Sep 24 10:58:44 PM UTC 24 |
Sep 24 10:58:47 PM UTC 24 |
94110905 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.234746783 |
|
|
Sep 24 10:58:44 PM UTC 24 |
Sep 24 10:58:47 PM UTC 24 |
70875268 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.326405744 |
|
|
Sep 24 10:58:45 PM UTC 24 |
Sep 24 10:58:49 PM UTC 24 |
73970171 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.5120087 |
|
|
Sep 24 10:58:43 PM UTC 24 |
Sep 24 10:58:49 PM UTC 24 |
102104182 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2028439858 |
|
|
Sep 24 10:58:47 PM UTC 24 |
Sep 24 10:58:49 PM UTC 24 |
25625272 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4209642621 |
|
|
Sep 24 10:58:43 PM UTC 24 |
Sep 24 10:58:49 PM UTC 24 |
489863700 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2925303400 |
|
|
Sep 24 10:58:36 PM UTC 24 |
Sep 24 10:58:50 PM UTC 24 |
881702694 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.943301578 |
|
|
Sep 24 10:58:47 PM UTC 24 |
Sep 24 10:58:50 PM UTC 24 |
710702469 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.859362347 |
|
|
Sep 24 10:58:41 PM UTC 24 |
Sep 24 10:58:50 PM UTC 24 |
668829954 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2619557843 |
|
|
Sep 24 10:58:48 PM UTC 24 |
Sep 24 10:58:50 PM UTC 24 |
15529262 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.511626003 |
|
|
Sep 24 10:58:47 PM UTC 24 |
Sep 24 10:58:51 PM UTC 24 |
1212431484 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1092810983 |
|
|
Sep 24 10:58:49 PM UTC 24 |
Sep 24 10:58:52 PM UTC 24 |
15095764 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1633245370 |
|
|
Sep 24 10:58:50 PM UTC 24 |
Sep 24 10:58:53 PM UTC 24 |
22013620 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2111027489 |
|
|
Sep 24 10:58:48 PM UTC 24 |
Sep 24 10:58:53 PM UTC 24 |
78826101 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2544640965 |
|
|
Sep 24 10:58:50 PM UTC 24 |
Sep 24 10:58:53 PM UTC 24 |
22120859 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.815823100 |
|
|
Sep 24 10:58:48 PM UTC 24 |
Sep 24 10:58:54 PM UTC 24 |
139375936 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2221365243 |
|
|
Sep 24 10:58:47 PM UTC 24 |
Sep 24 10:58:54 PM UTC 24 |
1153038841 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1908704027 |
|
|
Sep 24 10:58:50 PM UTC 24 |
Sep 24 10:58:54 PM UTC 24 |
238681335 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.325572974 |
|
|
Sep 24 10:58:51 PM UTC 24 |
Sep 24 10:58:54 PM UTC 24 |
28104772 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4153600945 |
|
|
Sep 24 10:58:51 PM UTC 24 |
Sep 24 10:58:54 PM UTC 24 |
21898984 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1367283725 |
|
|
Sep 24 10:58:50 PM UTC 24 |
Sep 24 10:58:54 PM UTC 24 |
101195168 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3766949802 |
|
|
Sep 24 10:58:53 PM UTC 24 |
Sep 24 10:58:55 PM UTC 24 |
27254134 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2004782296 |
|
|
Sep 24 10:58:53 PM UTC 24 |
Sep 24 10:58:56 PM UTC 24 |
50927547 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2041587484 |
|
|
Sep 24 10:58:52 PM UTC 24 |
Sep 24 10:58:56 PM UTC 24 |
769537979 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1776383558 |
|
|
Sep 24 10:58:41 PM UTC 24 |
Sep 24 10:58:56 PM UTC 24 |
698634110 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3401967434 |
|
|
Sep 24 10:58:25 PM UTC 24 |
Sep 24 10:58:56 PM UTC 24 |
12886140325 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1729049871 |
|
|
Sep 24 10:58:45 PM UTC 24 |
Sep 24 10:58:56 PM UTC 24 |
696406096 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2510372586 |
|
|
Sep 24 10:58:54 PM UTC 24 |
Sep 24 10:58:57 PM UTC 24 |
101188303 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3498746292 |
|
|
Sep 24 10:58:55 PM UTC 24 |
Sep 24 10:58:58 PM UTC 24 |
19666408 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1368555576 |
|
|
Sep 24 10:58:54 PM UTC 24 |
Sep 24 10:58:58 PM UTC 24 |
488243192 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.51926420 |
|
|
Sep 24 10:58:55 PM UTC 24 |
Sep 24 10:58:58 PM UTC 24 |
39053740 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1059503197 |
|
|
Sep 24 10:58:53 PM UTC 24 |
Sep 24 10:58:58 PM UTC 24 |
106449924 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.189120711 |
|
|
Sep 24 10:58:54 PM UTC 24 |
Sep 24 10:58:59 PM UTC 24 |
229838618 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2537648115 |
|
|
Sep 24 10:58:55 PM UTC 24 |
Sep 24 10:58:58 PM UTC 24 |
38164086 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2384322260 |
|
|
Sep 24 10:58:55 PM UTC 24 |
Sep 24 10:58:59 PM UTC 24 |
56746403 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.763321297 |
|
|
Sep 24 10:58:57 PM UTC 24 |
Sep 24 10:58:59 PM UTC 24 |
51046032 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3405260972 |
|
|
Sep 24 10:58:57 PM UTC 24 |
Sep 24 10:58:59 PM UTC 24 |
91249550 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.837438613 |
|
|
Sep 24 10:58:55 PM UTC 24 |
Sep 24 10:58:59 PM UTC 24 |
89414056 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2815896432 |
|
|
Sep 24 10:58:57 PM UTC 24 |
Sep 24 10:58:59 PM UTC 24 |
35645484 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2065935097 |
|
|
Sep 24 10:58:55 PM UTC 24 |
Sep 24 10:59:00 PM UTC 24 |
338654196 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.42451517 |
|
|
Sep 24 10:58:57 PM UTC 24 |
Sep 24 10:59:00 PM UTC 24 |
145850476 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.4284641199 |
|
|
Sep 24 10:58:57 PM UTC 24 |
Sep 24 10:59:00 PM UTC 24 |
260378342 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.107698323 |
|
|
Sep 24 10:58:57 PM UTC 24 |
Sep 24 10:59:01 PM UTC 24 |
581169736 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.459506265 |
|
|
Sep 24 10:58:58 PM UTC 24 |
Sep 24 10:59:01 PM UTC 24 |
23252682 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1305114732 |
|
|
Sep 24 10:58:59 PM UTC 24 |
Sep 24 10:59:01 PM UTC 24 |
15748703 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2150748497 |
|
|
Sep 24 10:58:59 PM UTC 24 |
Sep 24 10:59:02 PM UTC 24 |
81263117 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1678739155 |
|
|
Sep 24 10:58:59 PM UTC 24 |
Sep 24 10:59:02 PM UTC 24 |
49743309 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2839968168 |
|
|
Sep 24 10:59:00 PM UTC 24 |
Sep 24 10:59:03 PM UTC 24 |
48306049 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.397857456 |
|
|
Sep 24 10:59:00 PM UTC 24 |
Sep 24 10:59:03 PM UTC 24 |
189467233 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2253106909 |
|
|
Sep 24 10:59:00 PM UTC 24 |
Sep 24 10:59:03 PM UTC 24 |
35824715 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2942974532 |
|
|
Sep 24 10:58:59 PM UTC 24 |
Sep 24 10:59:03 PM UTC 24 |
33989312 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.75024150 |
|
|
Sep 24 10:58:59 PM UTC 24 |
Sep 24 10:59:03 PM UTC 24 |
123247529 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1573520838 |
|
|
Sep 24 10:58:59 PM UTC 24 |
Sep 24 10:59:03 PM UTC 24 |
72002062 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3704409966 |
|
|
Sep 24 10:59:02 PM UTC 24 |
Sep 24 10:59:04 PM UTC 24 |
13110816 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3310357169 |
|
|
Sep 24 10:59:02 PM UTC 24 |
Sep 24 10:59:04 PM UTC 24 |
20678614 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1060364796 |
|
|
Sep 24 10:59:02 PM UTC 24 |
Sep 24 10:59:05 PM UTC 24 |
33632824 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1094040896 |
|
|
Sep 24 10:59:03 PM UTC 24 |
Sep 24 10:59:05 PM UTC 24 |
12399711 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.573343214 |
|
|
Sep 24 10:59:00 PM UTC 24 |
Sep 24 10:59:05 PM UTC 24 |
93422605 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1021741260 |
|
|
Sep 24 10:59:01 PM UTC 24 |
Sep 24 10:59:05 PM UTC 24 |
407462512 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3585898651 |
|
|
Sep 24 10:59:01 PM UTC 24 |
Sep 24 10:59:06 PM UTC 24 |
86954968 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1145721480 |
|
|
Sep 24 10:59:03 PM UTC 24 |
Sep 24 10:59:07 PM UTC 24 |
49857024 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3749959210 |
|
|
Sep 24 10:59:04 PM UTC 24 |
Sep 24 10:59:07 PM UTC 24 |
27016693 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.977974258 |
|
|
Sep 24 10:59:02 PM UTC 24 |
Sep 24 10:59:07 PM UTC 24 |
44314732 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1970893975 |
|
|
Sep 24 10:59:04 PM UTC 24 |
Sep 24 10:59:07 PM UTC 24 |
68043667 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.516496398 |
|
|
Sep 24 10:59:04 PM UTC 24 |
Sep 24 10:59:07 PM UTC 24 |
19704025 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2728620735 |
|
|
Sep 24 10:59:04 PM UTC 24 |
Sep 24 10:59:08 PM UTC 24 |
25290464 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3003519216 |
|
|
Sep 24 10:59:04 PM UTC 24 |
Sep 24 10:59:08 PM UTC 24 |
226086620 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.979885854 |
|
|
Sep 24 10:59:04 PM UTC 24 |
Sep 24 10:59:08 PM UTC 24 |
34057192 ps |