Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	63024925	13167	0	0
claim_transition_if_regwen_rd_A	63024925	1569	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63024925	13167	0	0
T8	104016	0	0	0
T9	31744	0	0	0
T33	20918	0	0	0
T34	30208	0	0	0
T35	2227	0	0	0
T36	1429	0	0	0
T37	21552	0	0	0
T48	33770	0	0	0
T52	179885	7	0	0
T102	0	3	0	0
T103	0	8	0	0
T110	0	9	0	0
T123	6529	0	0	0
T158	0	2	0	0
T159	0	2	0	0
T160	0	10	0	0
T161	0	10	0	0
T162	0	5	0	0
T163	0	7	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63024925	1569	0	0
T164	149920	8	0	0
T165	0	7	0	0
T166	0	5	0	0
T167	0	217	0	0
T168	0	9	0	0
T169	0	18	0	0
T170	0	258	0	0
T171	0	9	0	0
T172	0	2	0	0
T173	0	145	0	0
T174	73640	0	0	0
T175	14612	0	0	0
T176	35479	0	0	0
T177	111186	0	0	0
T178	29707	0	0	0
T179	29746	0	0	0
T180	12010	0	0	0
T181	84696	0	0	0
T182	1104	0	0	0