Unified Coverage Report :: Module :: lc_ctrl

Module : lc_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.52	100.00	81.94	98.16		100.00	87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.10	100.00	83.10	99.89		100.00	87.50

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.10	100.00	83.10	99.89		100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.48	97.97	95.95	93.40	100.00	98.53	99.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_alert_tx[2].u_prim_alert_sender	100.00			100.00
lc_ctrl_csr_assert	100.00						100.00
tlul_assert_device	100.00						100.00
u_dmi_jtag	80.46			80.46
u_lc_ctrl_fsm	97.54	99.39	90.62		100.00	97.67	100.00
u_lc_ctrl_kmac_if	99.37	99.10	100.00		100.00	97.73	100.00
u_prim_clock_mux2	85.19	100.00	55.56				100.00
u_prim_esc_receiver0	16.07			16.07
u_prim_esc_receiver1	16.07			16.07
u_prim_flop_2sync_init	100.00	100.00				100.00
u_prim_lc_sync	100.00	100.00					100.00
u_prim_mubi4_dec	0.00	0.00
u_prim_rst_n_mux2	85.19	100.00	55.56				100.00
u_reg	99.29	97.79	98.66	100.00		100.00	100.00
u_reg_tap	93.90	97.36	98.54	73.61		100.00	100.00
u_tap_tlul_host	81.19	98.00	92.86	15.09		100.00	100.00

Line Coverage for Module : lc_ctrl

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
ALWAYS	317	41	41	100.00
ALWAYS	368	41	41	100.00
ALWAYS	466	33	33	100.00
ALWAYS	525	3	3	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	567	1	1	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	582	1	1	100.00
ALWAYS	668	5	5	100.00
CONT_ASSIGN	677	1	1	100.00
CONT_ASSIGN	678	1	1	100.00

212                       logic req_ready;
213        1/1            assign req_ready = dmi_req_ready & dmi_resp_ready;
           Tests:       T1 T2 T3 
214                       dmi_jtag #(
215                         .IdcodeValue(IdcodeValue),
216                         .NumDmiWordAbits(7)
217                       ) u_dmi_jtag (
218                         .clk_i,
219                         .rst_ni,
220                         .testmode_i       ( scanmode          ),
221                         .test_rst_ni      ( scan_rst_ni       ),
222                         .dmi_rst_no       (                   ), // unused
223                         .dmi_req_o        ( dmi_req           ),
224                         .dmi_req_valid_o  ( dmi_req_valid     ),
225                         // unless there is room for response, stall
226                         .dmi_req_ready_i  ( req_ready         ),
227                         .dmi_resp_i       ( dmi_resp          ),
228                         .dmi_resp_ready_o ( dmi_resp_ready    ),
229                         .dmi_resp_valid_i ( dmi_resp_valid    ),
230                         .tck_i            ( tck_muxed         ),
231                         .tms_i            ( jtag_i.tms        ),
232                         .trst_ni          ( trst_n_muxed      ),
233                         .td_i             ( jtag_i.tdi        ),
234                         .td_o             ( jtag_o.tdo        ),
235                         .tdo_oe_o         ( jtag_o.tdo_oe     )
236                       );
237                     
238                       // DMI to TL-UL transducing
239                       tlul_adapter_host #(
240                         .EnableDataIntgGen(1)
241                       ) u_tap_tlul_host (
242                         .clk_i,
243                         .rst_ni,
244                         // do not make a request unless there is room for the response
245                         .req_i        ( dmi_req_valid & dmi_resp_ready         ),
246                         .gnt_o        ( dmi_req_ready                          ),
247                         .addr_i       ( top_pkg::TL_AW'({dmi_req.addr, 2'b00}) ),
248                         .we_i         ( dmi_req.op == dm::DTM_WRITE            ),
249                         .wdata_i      ( dmi_req.data                           ),
250                         .wdata_intg_i ('0                                      ),
251                         .be_i         ( {top_pkg::TL_DBW{1'b1}}                ),
252                         .instr_type_i ( prim_mubi_pkg::MuBi4False              ),
253                         .valid_o      ( dmi_resp_valid                         ),
254                         .rdata_o      ( dmi_resp.data                          ),
255                         .rdata_intg_o (                                        ),
256                         .err_o        (                                        ),
257                         .intg_err_o   (                                        ),
258                         .tl_o         ( tap_tl_h2d                             ),
259                         .tl_i         ( tap_tl_d2h                             )
260                       );
261                     
262                       // TL-UL to DMI transducing
263                       assign dmi_resp.resp = '0; // unused inside dmi_jtag
264                     
265                       // These signals are unused
266                       logic unused_tap_tl_d2h;
267        1/1            assign unused_tap_tl_d2h = ^{
           Tests:       T1 T2 T3 
268                         dmi_req.addr[31:30],
269                         tap_tl_d2h.d_opcode,
270                         tap_tl_d2h.d_param,
271                         tap_tl_d2h.d_size,
272                         tap_tl_d2h.d_source,
273                         tap_tl_d2h.d_sink,
274                         tap_tl_d2h.d_user,
275                         tap_tl_d2h.d_error
276                       };
277                     
278                       ///////////////////////////////////////
279                       // Transition Interface and HW Mutex //
280                       ///////////////////////////////////////
281                     
282                       // All registers are HWext
283                       logic          trans_success_d, trans_success_q;
284                       logic          trans_cnt_oflw_error_d, trans_cnt_oflw_error_q;
285                       logic          trans_invalid_error_d, trans_invalid_error_q;
286                       logic          token_invalid_error_d, token_invalid_error_q;
287                       logic          flash_rma_error_d, flash_rma_error_q;
288                       logic          otp_prog_error_d, fatal_prog_error_q;
289                       logic          state_invalid_error_d, fatal_state_error_q;
290                       logic          otp_part_error_q;
291                       mubi8_t        sw_claim_transition_if_d, sw_claim_transition_if_q;
292                       mubi8_t        tap_claim_transition_if_d, tap_claim_transition_if_q;
293                       logic          transition_cmd;
294                       lc_token_t     transition_token_d, transition_token_q;
295                       ext_dec_lc_state_t transition_target_d, transition_target_q;
296                       // No need to register these.
297                       ext_dec_lc_state_t dec_lc_state;
298                       dec_lc_cnt_t       dec_lc_cnt;
299                       dec_lc_id_state_e  dec_lc_id_state;
300                     
301                       logic lc_idle_d, lc_done_d;
302                     
303                       // Assign hardware revision output
304                       assign hw_rev_o = '{silicon_creator_id: SiliconCreatorId,
305                                           product_id:         ProductId,
306                                           revision_id:        RevisionId,
307                                           reserved:           '0};
308                     
309                       // OTP Vendor control bits
310                       logic ext_clock_switched;
311                       logic use_ext_clock_d, use_ext_clock_q;
312                       logic volatile_raw_unlock_d, volatile_raw_unlock_q;
313                       logic [CsrOtpTestCtrlWidth-1:0] otp_vendor_test_ctrl_d, otp_vendor_test_ctrl_q;
314                       logic [CsrOtpTestStatusWidth-1:0] otp_vendor_test_status;
315                     
316                       always_comb begin : p_csr_assign_outputs
317        1/1              hw2reg = '0;
           Tests:       T1 T2 T3 
318        1/1              hw2reg.status.initialized            = lc_done_d;
           Tests:       T1 T2 T3 
319        1/1              hw2reg.status.ready                  = lc_idle_d;
           Tests:       T1 T2 T3 
320        1/1              hw2reg.status.ext_clock_switched     = ext_clock_switched;
           Tests:       T1 T2 T3 
321        1/1              hw2reg.status.transition_successful  = trans_success_q;
           Tests:       T1 T2 T3 
322        1/1              hw2reg.status.transition_count_error = trans_cnt_oflw_error_q;
           Tests:       T1 T2 T3 
323        1/1              hw2reg.status.transition_error       = trans_invalid_error_q;
           Tests:       T1 T2 T3 
324        1/1              hw2reg.status.token_error            = token_invalid_error_q;
           Tests:       T1 T2 T3 
325        1/1              hw2reg.status.flash_rma_error        = flash_rma_error_q;
           Tests:       T1 T2 T3 
326        1/1              hw2reg.status.otp_error              = fatal_prog_error_q;
           Tests:       T1 T2 T3 
327        1/1              hw2reg.status.state_error            = fatal_state_error_q;
           Tests:       T1 T2 T3 
328        1/1              hw2reg.status.otp_partition_error    = otp_part_error_q;
           Tests:       T1 T2 T3 
329        1/1              hw2reg.status.bus_integ_error        = fatal_bus_integ_error_q;
           Tests:       T1 T2 T3 
330        1/1              hw2reg.lc_state                      = dec_lc_state;
           Tests:       T1 T2 T3 
331        1/1              hw2reg.lc_transition_cnt             = dec_lc_cnt;
           Tests:       T1 T2 T3 
332        1/1              hw2reg.lc_id_state                   = {DecLcIdStateNumRep{dec_lc_id_state}};
           Tests:       T1 T2 T3 
333        1/1              hw2reg.device_id                     = otp_device_id_i;
           Tests:       T1 T2 T3 
334        1/1              hw2reg.manuf_state                   = otp_manuf_state_i;
           Tests:       T1 T2 T3 
335        1/1              hw2reg.hw_revision0.silicon_creator_id = hw_rev_o.silicon_creator_id;
           Tests:       T1 T2 T3 
336        1/1              hw2reg.hw_revision0.product_id         = hw_rev_o.product_id;
           Tests:       T1 T2 T3 
337        1/1              hw2reg.hw_revision1.revision_id        = hw_rev_o.revision_id;
           Tests:       T1 T2 T3 
338        1/1              hw2reg.hw_revision1.reserved           = '0;
           Tests:       T1 T2 T3 
339                     
340                         // The assignments above are identical for the TAP.
341        1/1              tap_hw2reg = hw2reg;
           Tests:       T1 T2 T3 
342                     
343                         // Assignments gated by mutex. Again, the TAP has priority.
344        1/1              tap_hw2reg.claim_transition_if = tap_claim_transition_if_q;
           Tests:       T1 T2 T3 
345        1/1              hw2reg.claim_transition_if = sw_claim_transition_if_q;
           Tests:       T1 T2 T3 
346        1/1              if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
347        1/1                tap_hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
           Tests:       T5 T7 T11 
348        1/1                tap_hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
           Tests:       T5 T7 T11 
349        1/1                tap_hw2reg.transition_token  = transition_token_q;
           Tests:       T5 T7 T11 
350        1/1                tap_hw2reg.transition_target = transition_target_q;
           Tests:       T5 T7 T11 
351                           // SEC_CM: TRANSITION.CONFIG.REGWEN
352        1/1                tap_hw2reg.transition_regwen = lc_idle_d;
           Tests:       T5 T7 T11 
353        1/1                tap_hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
           Tests:       T5 T7 T11 
354        1/1                tap_hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
           Tests:       T5 T7 T11 
355        1/1              end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
356        1/1                hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
           Tests:       T1 T2 T4 
357        1/1                hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
           Tests:       T1 T2 T4 
358        1/1                hw2reg.transition_token  = transition_token_q;
           Tests:       T1 T2 T4 
359        1/1                hw2reg.transition_target = transition_target_q;
           Tests:       T1 T2 T4 
360                           // SEC_CM: TRANSITION.CONFIG.REGWEN
361        1/1                hw2reg.transition_regwen = lc_idle_d;
           Tests:       T1 T2 T4 
362        1/1                hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
           Tests:       T1 T2 T4 
363        1/1                hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
           Tests:       T1 T2 T4 
364                         end
                        MISSING_ELSE
365                       end
366                     
367                       always_comb begin : p_csr_assign_inputs
368        1/1              sw_claim_transition_if_d  = sw_claim_transition_if_q;
           Tests:       T1 T2 T3 
369        1/1              tap_claim_transition_if_d = tap_claim_transition_if_q;
           Tests:       T1 T2 T3 
370        1/1              transition_token_d        = transition_token_q;
           Tests:       T1 T2 T3 
371        1/1              transition_target_d       = transition_target_q;
           Tests:       T1 T2 T3 
372        1/1              transition_cmd            = 1'b0;
           Tests:       T1 T2 T3 
373        1/1              otp_vendor_test_ctrl_d    = otp_vendor_test_ctrl_q;
           Tests:       T1 T2 T3 
374        1/1              use_ext_clock_d           = use_ext_clock_q;
           Tests:       T1 T2 T3 
375        1/1              volatile_raw_unlock_d     = volatile_raw_unlock_q;
           Tests:       T1 T2 T3 
376                     
377                         // Note that the mutex claims from the TAP and SW side could arrive within the same cycle.
378                         // In that case we give priority to the TAP mutex claim in order to avoid a race condition.
379                         // TAP mutex claim.
380        1/1              if (mubi8_test_false_loose(sw_claim_transition_if_q) &&
           Tests:       T1 T2 T3 
381                             tap_reg2hw.claim_transition_if.qe) begin
382        1/1                tap_claim_transition_if_d = mubi8_t'(tap_reg2hw.claim_transition_if.q);
           Tests:       T1 T2 T3 
383                         // SW mutex claim.
384        1/1              end else if (mubi8_test_false_loose(tap_claim_transition_if_q) &&
           Tests:       T1 T2 T3 
385                             reg2hw.claim_transition_if.qe) begin
386        1/1                sw_claim_transition_if_d = mubi8_t'(reg2hw.claim_transition_if.q);
           Tests:       T1 T2 T3 
387                         end
                        MISSING_ELSE
388                     
389                     
390                         // The idle signal serves as the REGWEN in this case.
391        1/1              if (lc_idle_d) begin
           Tests:       T1 T2 T3 
392                           // The TAP has priority.
393        1/1                if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
394        1/1                  transition_cmd = tap_reg2hw.transition_cmd.q &
           Tests:       T5 T7 T11 
395                                              tap_reg2hw.transition_cmd.qe;
396                     
397        1/1                  if (tap_reg2hw.transition_ctrl.ext_clock_en.qe) begin
           Tests:       T5 T7 T11 
398        1/1                    use_ext_clock_d |= tap_reg2hw.transition_ctrl.ext_clock_en.q;
           Tests:       T7 T11 T18 
399                             end
                        MISSING_ELSE
400                     
401                             // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
402                             // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
403                             // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
404                             // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
405                             // ---------------------------------------------------------------
406        1/1                  if (tap_reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
           Tests:       T5 T7 T11 
407        1/1                    volatile_raw_unlock_d = tap_reg2hw.transition_ctrl.volatile_raw_unlock.q;
           Tests:       T7 T11 T18 
408                             end
                        MISSING_ELSE
409                             // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
410                     
411        1/1                  for (int k = 0; k < LcTokenWidth/32; k++) begin
           Tests:       T5 T7 T11 
412        1/1                    if (tap_reg2hw.transition_token[k].qe) begin
           Tests:       T5 T7 T11 
413        1/1                      transition_token_d[k*32 +: 32] = tap_reg2hw.transition_token[k].q;
           Tests:       T5 T7 T11 
414                               end
                        MISSING_ELSE
415                             end
416                     
417        1/1                  if (tap_reg2hw.transition_target.qe) begin
           Tests:       T5 T7 T11 
418        1/1                    for (int k = 0; k < DecLcStateNumRep; k++) begin
           Tests:       T5 T7 T11 
419        1/1                      transition_target_d[k] = dec_lc_state_e'(
           Tests:       T5 T7 T11 
420                                     tap_reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
421                               end
422                             end
                        MISSING_ELSE
423                     
424        1/1                  if (tap_reg2hw.otp_vendor_test_ctrl.qe) begin
           Tests:       T5 T7 T11 
425        1/1                    otp_vendor_test_ctrl_d = tap_reg2hw.otp_vendor_test_ctrl.q;
           Tests:       T5 T7 T11 
426                             end
                        MISSING_ELSE
427        1/1                end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
428        1/1                  transition_cmd = reg2hw.transition_cmd.q &
           Tests:       T1 T2 T4 
429                                              reg2hw.transition_cmd.qe;
430                     
431        1/1                  if (reg2hw.transition_ctrl.ext_clock_en.qe) begin
           Tests:       T1 T2 T4 
432        1/1                    use_ext_clock_d |= reg2hw.transition_ctrl.ext_clock_en.q;
           Tests:       T1 T2 T6 
433                             end
                        MISSING_ELSE
434                     
435                             // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
436                             // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
437                             // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
438                             // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
439                             // ---------------------------------------------------------------
440        1/1                  if (reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
           Tests:       T1 T2 T4 
441        1/1                    volatile_raw_unlock_d = reg2hw.transition_ctrl.volatile_raw_unlock.q;
           Tests:       T1 T2 T6 
442                             end
                        MISSING_ELSE
443                             // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
444                     
445        1/1                  for (int k = 0; k < LcTokenWidth/32; k++) begin
           Tests:       T1 T2 T4 
446        1/1                    if (reg2hw.transition_token[k].qe) begin
           Tests:       T1 T2 T4 
447        1/1                      transition_token_d[k*32 +: 32] = reg2hw.transition_token[k].q;
           Tests:       T1 T2 T4 
448                               end
                        MISSING_ELSE
449                             end
450                     
451        1/1                  if (reg2hw.transition_target.qe) begin
           Tests:       T1 T2 T4 
452        1/1                    for (int k = 0; k < DecLcStateNumRep; k++) begin
           Tests:       T1 T2 T4 
453        1/1                      transition_target_d[k] = dec_lc_state_e'(
           Tests:       T1 T2 T4 
454                                     reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
455                               end
456                             end
                        MISSING_ELSE
457                     
458        1/1                  if (reg2hw.otp_vendor_test_ctrl.qe) begin
           Tests:       T1 T2 T4 
459        1/1                    otp_vendor_test_ctrl_d = reg2hw.otp_vendor_test_ctrl.q;
           Tests:       T2 T4 T6 
460                             end
                        MISSING_ELSE
461                           end
                        MISSING_ELSE
462                         end
                        MISSING_ELSE
463                       end
464                     
465                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_csrs
466        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
467        1/1                trans_success_q           <= 1'b0;
           Tests:       T1 T2 T3 
468        1/1                trans_cnt_oflw_error_q    <= 1'b0;
           Tests:       T1 T2 T3 
469        1/1                trans_invalid_error_q     <= 1'b0;
           Tests:       T1 T2 T3 
470        1/1                token_invalid_error_q     <= 1'b0;
           Tests:       T1 T2 T3 
471        1/1                flash_rma_error_q         <= 1'b0;
           Tests:       T1 T2 T3 
472        1/1                fatal_prog_error_q        <= 1'b0;
           Tests:       T1 T2 T3 
473        1/1                fatal_state_error_q       <= 1'b0;
           Tests:       T1 T2 T3 
474        1/1                sw_claim_transition_if_q  <= MuBi8False;
           Tests:       T1 T2 T3 
475        1/1                tap_claim_transition_if_q <= MuBi8False;
           Tests:       T1 T2 T3 
476        1/1                transition_token_q        <= '0;
           Tests:       T1 T2 T3 
477        1/1                transition_target_q       <= {DecLcStateNumRep{DecLcStRaw}};
           Tests:       T1 T2 T3 
478        1/1                otp_part_error_q          <= 1'b0;
           Tests:       T1 T2 T3 
479        1/1                fatal_bus_integ_error_q   <= 1'b0;
           Tests:       T1 T2 T3 
480        1/1                otp_vendor_test_ctrl_q    <= '0;
           Tests:       T1 T2 T3 
481        1/1                use_ext_clock_q           <= 1'b0;
           Tests:       T1 T2 T3 
482                         end else begin
483                           // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
484                           // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
485                           // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
486                           // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
487                           // ---------------------------------------------------------------
488                           // In case of a volatile RAW unlock, this bit has to be cleared when the volatile
489                           // unlock is followed by a real transition.
490                           // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
491        1/1                if (SecVolatileRawUnlockEn && transition_cmd && !volatile_raw_unlock_q) begin
           Tests:       T1 T2 T3 
492        1/1                  trans_success_q <= 1'b0;
           Tests:       T2 T4 T5 
493                           end else begin
494        1/1                  trans_success_q <= trans_success_d | trans_success_q;
           Tests:       T1 T2 T3 
495                           end
496                           // All other status and error bits are terminal and require a reset cycle.
497        1/1                trans_cnt_oflw_error_q    <= trans_cnt_oflw_error_d  | trans_cnt_oflw_error_q;
           Tests:       T1 T2 T3 
498        1/1                trans_invalid_error_q     <= trans_invalid_error_d   | trans_invalid_error_q;
           Tests:       T1 T2 T3 
499        1/1                token_invalid_error_q     <= token_invalid_error_d   | token_invalid_error_q;
           Tests:       T1 T2 T3 
500        1/1                flash_rma_error_q         <= flash_rma_error_d       | flash_rma_error_q;
           Tests:       T1 T2 T3 
501        1/1                fatal_prog_error_q        <= otp_prog_error_d        | fatal_prog_error_q;
           Tests:       T1 T2 T3 
502        1/1                fatal_state_error_q       <= state_invalid_error_d   | fatal_state_error_q;
           Tests:       T1 T2 T3 
503        1/1                otp_part_error_q          <= otp_lc_data_i.error     | otp_part_error_q;
           Tests:       T1 T2 T3 
504        1/1                fatal_bus_integ_error_q   <= fatal_bus_integ_error_csr_d |
           Tests:       T1 T2 T3 
505                                                        fatal_bus_integ_error_tap_d |
506                                                        fatal_bus_integ_error_q;
507                           // Other regs, gated by mutex further below.
508        1/1                sw_claim_transition_if_q  <= sw_claim_transition_if_d;
           Tests:       T1 T2 T3 
509        1/1                tap_claim_transition_if_q <= tap_claim_transition_if_d;
           Tests:       T1 T2 T3 
510        1/1                transition_token_q        <= transition_token_d;
           Tests:       T1 T2 T3 
511        1/1                transition_target_q       <= transition_target_d;
           Tests:       T1 T2 T3 
512        1/1                otp_vendor_test_ctrl_q    <= otp_vendor_test_ctrl_d;
           Tests:       T1 T2 T3 
513        1/1                use_ext_clock_q           <= use_ext_clock_d;
           Tests:       T1 T2 T3 
514                         end
515                       end
516                     
517                       // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
518                       // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
519                       // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
520                       // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
521                       // ---------------------------------------------------------------
522                       // If not enabled, this register will become a constant.
523                       if (SecVolatileRawUnlockEn) begin : gen_volatile_raw_unlock_reg
524                         always_ff @(posedge clk_i or negedge rst_ni) begin : p_volatile_raw_unlock_reg
525        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
526        1/1                  volatile_raw_unlock_q     <= 1'b0;
           Tests:       T1 T2 T3 
527                           end else begin
528        1/1                  volatile_raw_unlock_q     <= volatile_raw_unlock_d;
           Tests:       T1 T2 T3 
529                           end
530                         end
531                       end else begin : gen_volatile_raw_unlock_const
532                         logic unused_volatile_raw_unlock;
533                         assign unused_volatile_raw_unlock = ^volatile_raw_unlock_d;
534                         assign volatile_raw_unlock_q = 1'b0;
535                       end
536                       // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
537                     
538        1/1            assign lc_flash_rma_seed_o = transition_token_q[RmaSeedWidth-1:0];
           Tests:       T1 T2 T3 
539                     
540                       // Gate the vendor specific test ctrl/status bits to zero in production states.
541                       // Buffer the enable signal to prevent optimization of the multibit signal.
542                       lc_tx_t lc_raw_test_rma;
543                       lc_tx_t [1:0] lc_raw_test_rma_buf;
544                       prim_lc_sync #(
545                         .NumCopies(2),
546                         .AsyncOn(0)
547                       ) u_prim_lc_sync (
548                         .clk_i,
549                         .rst_ni,
550                         .lc_en_i(lc_raw_test_rma),
551                         .lc_en_o(lc_raw_test_rma_buf)
552                       );
553                     
554        1/1            assign lc_otp_vendor_test_o.ctrl = (lc_tx_test_true_strict(lc_raw_test_rma_buf[0])) ?
           Tests:       T1 T2 T3 
555                                                          otp_vendor_test_ctrl_q                           : '0;
556        1/1            assign otp_vendor_test_status    = (lc_tx_test_true_strict(lc_raw_test_rma_buf[1])) ?
           Tests:       T1 T2 T3 
557                                                          lc_otp_vendor_test_i.status                      : '0;
558                     
559                       //////////////////
560                       // Alert Sender //
561                       //////////////////
562                     
563                       logic [NumAlerts-1:0] alerts;
564                       logic [NumAlerts-1:0] alert_test;
565                       logic [NumAlerts-1:0] tap_alert_test;
566                     
567        1/1            assign alerts = {
           Tests:       T1 T2 T3 
568                         fatal_bus_integ_error_q,
569                         fatal_state_error_q,
570                         fatal_prog_error_q
571                       };
572                     
573        1/1            assign alert_test = {
           Tests:       T1 T2 T3 
574                         reg2hw.alert_test.fatal_bus_integ_error.q &
575                         reg2hw.alert_test.fatal_bus_integ_error.qe,
576                         reg2hw.alert_test.fatal_state_error.q &
577                         reg2hw.alert_test.fatal_state_error.qe,
578                         reg2hw.alert_test.fatal_prog_error.q &
579                         reg2hw.alert_test.fatal_prog_error.qe
580                       };
581                     
582        1/1             assign tap_alert_test = {
           Tests:       T1 T2 T3 
583                         tap_reg2hw.alert_test.fatal_bus_integ_error.q &
584                         tap_reg2hw.alert_test.fatal_bus_integ_error.qe,
585                         tap_reg2hw.alert_test.fatal_state_error.q &
586                         tap_reg2hw.alert_test.fatal_state_error.qe,
587                         tap_reg2hw.alert_test.fatal_prog_error.q &
588                         tap_reg2hw.alert_test.fatal_prog_error.qe
589                       };
590                     
591                       for (genvar k = 0; k < NumAlerts; k++) begin : gen_alert_tx
592                         prim_alert_sender #(
593                           .AsyncOn(AlertAsyncOn[k]),
594                           .IsFatal(1)
595                         ) u_prim_alert_sender (
596                           .clk_i,
597                           .rst_ni,
598                           .alert_test_i  ( alert_test[k] |
599                                            tap_alert_test[k] ),
600                           .alert_req_i   ( alerts[k]         ),
601                           .alert_ack_o   (                   ),
602                           .alert_state_o (                   ),
603                           .alert_rx_i    ( alert_rx_i[k]     ),
604                           .alert_tx_o    ( alert_tx_o[k]     )
605                         );
606                       end
607                     
608                       //////////////////////////
609                       // Escalation Receivers //
610                       //////////////////////////
611                     
612                       // SEC_CM: MAIN.FSM.GLOBAL_ESC
613                       // We still have two escalation receivers here for historical reasons.
614                       // The two actions "wipe secrets" and "scrap lifecycle state" have been
615                       // combined in order to simplify both DV and the design, as otherwise
616                       // this separation of very intertwined actions would have caused too many
617                       // unnecessary corner cases. The escalation receivers are now redundant and
618                       // trigger both actions at once.
619                     
620                       // This escalation action moves the life cycle
621                       // state into a temporary "SCRAP" state named "ESCALATE",
622                       // and asserts the lc_escalate_en life cycle control signal.
623                       logic esc_scrap_state0;
624                       prim_esc_receiver #(
625                         .N_ESC_SEV   (alert_handler_reg_pkg::N_ESC_SEV),
626                         .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW)
627                       ) u_prim_esc_receiver0 (
628                         .clk_i,
629                         .rst_ni,
630                         .esc_req_o (esc_scrap_state0),
631                         .esc_rx_o  (esc_scrap_state0_rx_o),
632                         .esc_tx_i  (esc_scrap_state0_tx_i)
633                       );
634                     
635                       // This escalation action moves the life cycle
636                       // state into a temporary "SCRAP" state named "ESCALATE".
637                       logic esc_scrap_state1;
638                       prim_esc_receiver #(
639                         .N_ESC_SEV   (alert_handler_reg_pkg::N_ESC_SEV),
640                         .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW)
641                       ) u_prim_esc_receiver1 (
642                         .clk_i,
643                         .rst_ni,
644                         .esc_req_o (esc_scrap_state1),
645                         .esc_rx_o  (esc_scrap_state1_rx_o),
646                         .esc_tx_i  (esc_scrap_state1_tx_i)
647                       );
648                     
649                       ////////////////////////////
650                       // Synchronization of IOs //
651                       ////////////////////////////
652                     
653                       // Signals going to and coming from power manager.
654                       logic lc_init;
655                       prim_flop_2sync #(
656                         .Width(1)
657                       ) u_prim_flop_2sync_init (
658                         .clk_i,
659                         .rst_ni,
660                         .d_i(pwr_lc_i.lc_init),
661                         .q_o(lc_init)
662                       );
663                     
664                       logic lc_done_q;
665                       logic lc_idle_q;
666                     
667                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_sync_regs
668        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
669        1/1                lc_done_q <= 1'b0;
           Tests:       T1 T2 T3 
670        1/1                lc_idle_q <= 1'b0;
           Tests:       T1 T2 T3 
671                         end else begin
672        1/1                lc_done_q <= lc_done_d;
           Tests:       T1 T2 T3 
673        1/1                lc_idle_q <= lc_idle_d;
           Tests:       T1 T2 T3 
674                         end
675                       end
676                     
677        1/1            assign pwr_lc_o.lc_done = lc_done_q;
           Tests:       T1 T2 T3 
678        1/1            assign pwr_lc_o.lc_idle = lc_idle_q;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : lc_ctrl

	Total	Covered	Percent
Conditions	72	59	81.94
Logical	72	59	81.94
Non-Logical	0	0
Event	0	0

 LINE       213
 EXPRESSION (dmi_req_ready & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T5,T7

 LINE       241
 EXPRESSION (dmi_req_valid & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T7
1	0	Not Covered
1	1	Covered	T6,T5,T7

 LINE       241
 EXPRESSION (dmi_req.op == DTM_WRITE)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T5,T7

 LINE       394
 EXPRESSION (tap_reg2hw.transition_cmd.q & tap_reg2hw.transition_cmd.qe)
             -------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T11
1	1	Covered	T5,T7,T18

 LINE       428
 EXPRESSION (reg2hw.transition_cmd.q & reg2hw.transition_cmd.qe)
             -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       491
 EXPRESSION (SecVolatileRawUnlockEn && transition_cmd && ((!volatile_raw_unlock_q)))
             -----------1----------    -------2------    -------------3------------

-1-	-2-	-3-	Status	Tests
-	0	1	Covered	T1,T2,T3
-	1	0	Covered	T1,T24,T41
-	1	1	Covered	T2,T4,T5

 LINE       494
 EXPRESSION (trans_success_d | trans_success_q)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       497
 EXPRESSION (trans_cnt_oflw_error_d | trans_cnt_oflw_error_q)
             -----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T45,T52
1	0	Covered	T13,T45,T52

 LINE       498
 EXPRESSION (trans_invalid_error_d | trans_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T13,T42
1	0	Covered	T1,T6,T11

 LINE       499
 EXPRESSION (token_invalid_error_d | token_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T16,T42
1	0	Covered	T13,T16,T42

 LINE       500
 EXPRESSION (flash_rma_error_d | flash_rma_error_q)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T16,T45
1	0	Covered	T13,T16,T45

 LINE       501
 EXPRESSION (otp_prog_error_d | fatal_prog_error_q)
             --------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T13
1	0	Covered	T4,T5,T13

 LINE       502
 EXPRESSION (state_invalid_error_d | fatal_state_error_q)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T16,T20
1	0	Covered	T12,T16,T20

 LINE       503
 EXPRESSION (otp_lc_data_i.error | otp_part_error_q)
             ---------1---------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T44,T100
1	0	Covered	T13,T45,T52

 LINE       504
 EXPRESSION (fatal_bus_integ_error_csr_d | fatal_bus_integ_error_tap_d | fatal_bus_integ_error_q)
             -------------1-------------   -------------2-------------   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T69,T70,T71
1	0	0	Covered	T69,T70,T71

 LINE       573
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T25,T97,T101
1	0	Covered	T1,T2,T3
1	1	Covered	T25,T97,T101

 LINE       573
 SUB-EXPRESSION (reg2hw.alert_test.fatal_state_error.q & reg2hw.alert_test.fatal_state_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T25,T97,T101
1	0	Covered	T1,T2,T3
1	1	Covered	T25,T97,T101

 LINE       573
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prog_error.q & reg2hw.alert_test.fatal_prog_error.qe)
                 ------------------1-----------------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T25,T97,T101
1	0	Covered	T1,T2,T3
1	1	Covered	T25,T97,T101

 LINE       582
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_bus_integ_error.q & tap_reg2hw.alert_test.fatal_bus_integ_error.qe)
                 ----------------------1----------------------   -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T5,T7
1	1	Not Covered

 LINE       582
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_state_error.q & tap_reg2hw.alert_test.fatal_state_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T5,T7
1	1	Not Covered

 LINE       582
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_prog_error.q & tap_reg2hw.alert_test.fatal_prog_error.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T5,T7
1	1	Not Covered

 LINE       595
 EXPRESSION (alert_test[0] | tap_alert_test[0])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T25,T97,T101

 LINE       595
 EXPRESSION (alert_test[1] | tap_alert_test[1])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T25,T97,T101

 LINE       595
 EXPRESSION (alert_test[2] | tap_alert_test[2])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T25,T97,T101

---

Toggle Coverage for Module : lc_ctrl

	Total	Covered	Percent
Totals	105	99	94.29
Total Bits	7426	7289	98.16
Total Bits 0->1	3713	3645	98.17
Total Bits 1->0	3713	3644	98.14

Ports	105	99	94.29
Port Bits	7426	7289	98.16
Port Bits 0->1	3713	3645	98.17
Port Bits 1->0	3713	3644	98.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
clk_kmac_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_kmac_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T11,T13,T25	Yes	T11,T13,T25	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T4,T6	Yes	T2,T4,T6	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T52,T102,T103	Yes	T52,T102,T103	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
jtag_i.tdi	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	INPUT
jtag_i.trst_n	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
jtag_i.tms	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	INPUT
jtag_i.tck	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	INPUT
jtag_o.tdo_oe	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	OUTPUT
jtag_o.tdo	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	OUTPUT
scan_rst_ni	Yes	Yes	T6,T8,T9	Yes	T8,T9,T10	INPUT
scanmode_i[3:0]	No	No		No		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T12,T25,T16	Yes	T12,T25,T16	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T25,T97,T101	Yes	T25,T97,T101	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T12,T25,T16	Yes	T12,T25,T16	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T25,T97,T101	Yes	T25,T97,T101	OUTPUT
esc_scrap_state0_tx_i.resp_n	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	INPUT
esc_scrap_state0_tx_i.resp_p	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	INPUT
esc_scrap_state0_rx_o.esc_n	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	OUTPUT
esc_scrap_state0_rx_o.esc_p	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	OUTPUT
esc_scrap_state1_tx_i.resp_n	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	INPUT
esc_scrap_state1_tx_i.resp_p	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	INPUT
esc_scrap_state1_rx_o.esc_n	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	OUTPUT
esc_scrap_state1_rx_o.esc_p	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	OUTPUT
pwr_lc_i.lc_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_lc_o.lc_idle	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
pwr_lc_o.lc_done	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
strap_en_override_o	No	No		Yes	T1,T24,T41	OUTPUT
lc_otp_vendor_test_o.ctrl[31:0]	Yes	Yes	T4,T17,T42	Yes	T4,T11,T17	OUTPUT
lc_otp_vendor_test_i.status[31:0]	Yes	Yes	T2,T12,T42	Yes	T2,T12,T24	INPUT
lc_otp_program_o.count[383:0]	Yes	Yes	T53,T104,T105	Yes	T53,T104,T105	OUTPUT
lc_otp_program_o.state[319:0]	Yes	Yes	T54,T106,T107	Yes	T54,T106,T107	OUTPUT
lc_otp_program_o.req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
lc_otp_program_i.ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
lc_otp_program_i.err	Yes	Yes	T52,T102,T108	Yes	T52,T102,T109	INPUT
kmac_data_i.error	Yes	Yes	T13,T45,T52	Yes	T13,T45,T52	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T7,T12,T13	Yes	T2,T7,T12	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T2,T7,T12	Yes	T2,T7,T12	INPUT
kmac_data_i.done	Yes	Yes	T2,T7,T12	Yes	T2,T7,T12	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T2,T7,T12	Yes	T2,T7,T12	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T2,T7,T12	Yes	T2,T7,T12	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T2,T7,T12	Yes	T2,T7,T12	OUTPUT
kmac_data_o.valid	Yes	Yes	T2,T7,T12	Yes	T2,T7,T12	OUTPUT
otp_lc_data_i.rma_token[127:0]	Yes	Yes	T2,T7,T12	Yes	T2,T4,T5	INPUT
otp_lc_data_i.rma_token_valid[3:0]	Yes	Yes	T16,T46,T37	Yes	T16,T46,T37	INPUT
otp_lc_data_i.test_exit_token[127:0]	Yes	Yes	T2,T4,T5	Yes	T4,T5,T7	INPUT
otp_lc_data_i.test_unlock_token[127:0]	Yes	Yes	T2,T4,T5	Yes	T4,T7,T12	INPUT
otp_lc_data_i.test_tokens_valid[3:0]	Yes	Yes	T16,T46,T37	Yes	T16,T46,T37	INPUT
otp_lc_data_i.secrets_valid[3:0]	Yes	Yes	T16,T46,T37	Yes	T16,T46,T37	INPUT
otp_lc_data_i.count[383:0]	Yes	Yes	T53,T104,T105	Yes	T53,T104,T105	INPUT
otp_lc_data_i.state[319:0]	Yes	Yes	T54,T106,T107	Yes	T54,T106,T107	INPUT
otp_lc_data_i.error	Yes	Yes	T13,T45,T52	Yes	T13,T45,T52	INPUT
otp_lc_data_i.valid	Yes	Yes	T12,T53,T54	Yes	T12,T53,T54	INPUT
lc_dft_en_o[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
lc_nvm_debug_en_o[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
lc_hw_debug_en_o[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
lc_cpu_en_o[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
lc_creator_seed_sw_rw_en_o[3:0]	Yes	Yes	T2,T4,T7	Yes	T2,T4,T7	OUTPUT
lc_owner_seed_sw_rw_en_o[3:0]	Yes	Yes	T2,T4,T7	Yes	T2,T4,T7	OUTPUT
lc_iso_part_sw_rd_en_o[3:0]	Yes	Yes	T4,T7,T12	Yes	T4,T7,T12	OUTPUT
lc_iso_part_sw_wr_en_o[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
lc_seed_hw_rd_en_o[3:0]	Yes	Yes	T12,T13,T15	Yes	T12,T13,T15	OUTPUT
lc_keymgr_en_o[3:0]	Yes	Yes	T2,T4,T7	Yes	T2,T4,T7	OUTPUT
lc_escalate_en_o[3:0]	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	OUTPUT
lc_check_byp_en_o[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
lc_clk_byp_req_o[3:0]	Yes	Yes	T7,T14,T17	Yes	T7,T11,T14	OUTPUT
lc_clk_byp_ack_i[3:0]	Yes	Yes	T7,T13,T14	Yes	T7,T13,T14	INPUT
lc_flash_rma_seed_o[31:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T4	OUTPUT
lc_flash_rma_req_o[3:0]	Yes	Yes	T2,T7,T14	Yes	T2,T7,T14	OUTPUT
lc_keymgr_div_o[127:0]	Yes	Yes	T2,T4,T7	Yes	T2,T4,T7	OUTPUT
otp_device_id_i[255:0]	Yes	Yes	T4,T7,T13	Yes	T4,T7,T13	INPUT
otp_manuf_state_i[255:0]	Yes	Yes	T5,T12,T13	Yes	T1,T3,T5	INPUT
hw_rev_o.reserved[23:0]	No	No		No		OUTPUT
hw_rev_o.revision_id[7:0]	No	No		No		OUTPUT
hw_rev_o.product_id[15:0]	No	No		No		OUTPUT
hw_rev_o.silicon_creator_id[15:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : lc_ctrl

	Line No.	Total	Covered	Percent
Branches		31	31	100.00
IF	346	3	3	100.00
IF	380	3	3	100.00
IF	391	18	18	100.00
IF	466	3	3	100.00
IF	668	2	2	100.00
IF	525	2	2	100.00

346            if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
               -1-                                                
347              tap_hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
                 ==>
348              tap_hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
349              tap_hw2reg.transition_token  = transition_token_q;
350              tap_hw2reg.transition_target = transition_target_q;
351              // SEC_CM: TRANSITION.CONFIG.REGWEN
352              tap_hw2reg.transition_regwen = lc_idle_d;
353              tap_hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
354              tap_hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
355            end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
                        -2-                                               
356              hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
                 ==>
357              hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
358              hw2reg.transition_token  = transition_token_q;
359              hw2reg.transition_target = transition_target_q;
360              // SEC_CM: TRANSITION.CONFIG.REGWEN
361              hw2reg.transition_regwen = lc_idle_d;
362              hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
363              hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
364            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T7,T11
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

380            if (mubi8_test_false_loose(sw_claim_transition_if_q) &&
               -1-                                               
381                tap_reg2hw.claim_transition_if.qe) begin
382              tap_claim_transition_if_d = mubi8_t'(tap_reg2hw.claim_transition_if.q);
                 ==>
383            // SW mutex claim.
384            end else if (mubi8_test_false_loose(tap_claim_transition_if_q) &&
                        -2-                                                
385                reg2hw.claim_transition_if.qe) begin
386              sw_claim_transition_if_d = mubi8_t'(reg2hw.claim_transition_if.q);
                 ==>
387            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

391            if (lc_idle_d) begin
               -1-  
392              // The TAP has priority.
393              if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
                 -2-                                                
394                transition_cmd = tap_reg2hw.transition_cmd.q &
395                                 tap_reg2hw.transition_cmd.qe;
396        
397                if (tap_reg2hw.transition_ctrl.ext_clock_en.qe) begin
                   -3-  
398                  use_ext_clock_d |= tap_reg2hw.transition_ctrl.ext_clock_en.q;
                     ==>
399                end
                   MISSING_ELSE
                   ==>
400        
401                // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
402                // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
403                // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
404                // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
405                // ---------------------------------------------------------------
406                if (tap_reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
                   -4-  
407                  volatile_raw_unlock_d = tap_reg2hw.transition_ctrl.volatile_raw_unlock.q;
                     ==>
408                end
                   MISSING_ELSE
                   ==>
409                // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
410        
411                for (int k = 0; k < LcTokenWidth/32; k++) begin
412                  if (tap_reg2hw.transition_token[k].qe) begin
413                    transition_token_d[k*32 +: 32] = tap_reg2hw.transition_token[k].q;
414                  end
415                end
416        
417                if (tap_reg2hw.transition_target.qe) begin
                   -5-  
418                  for (int k = 0; k < DecLcStateNumRep; k++) begin
                     ==>
419                    transition_target_d[k] = dec_lc_state_e'(
420                        tap_reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
421                  end
422                end
                   MISSING_ELSE
                   ==>
423        
424                if (tap_reg2hw.otp_vendor_test_ctrl.qe) begin
                   -6-  
425                  otp_vendor_test_ctrl_d = tap_reg2hw.otp_vendor_test_ctrl.q;
                     ==>
426                end
                   MISSING_ELSE
                   ==>
427              end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
                          -7-                                               
428                transition_cmd = reg2hw.transition_cmd.q &
429                                 reg2hw.transition_cmd.qe;
430        
431                if (reg2hw.transition_ctrl.ext_clock_en.qe) begin
                   -8-  
432                  use_ext_clock_d |= reg2hw.transition_ctrl.ext_clock_en.q;
                     ==>
433                end
                   MISSING_ELSE
                   ==>
434        
435                // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
436                // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
437                // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
438                // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
439                // ---------------------------------------------------------------
440                if (reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
                   -9-  
441                  volatile_raw_unlock_d = reg2hw.transition_ctrl.volatile_raw_unlock.q;
                     ==>
442                end
                   MISSING_ELSE
                   ==>
443                // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
444        
445                for (int k = 0; k < LcTokenWidth/32; k++) begin
446                  if (reg2hw.transition_token[k].qe) begin
447                    transition_token_d[k*32 +: 32] = reg2hw.transition_token[k].q;
448                  end
449                end
450        
451                if (reg2hw.transition_target.qe) begin
                   -10-  
452                  for (int k = 0; k < DecLcStateNumRep; k++) begin
                     ==>
453                    transition_target_d[k] = dec_lc_state_e'(
454                        reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
455                  end
456                end
                   MISSING_ELSE
                   ==>
457        
458                if (reg2hw.otp_vendor_test_ctrl.qe) begin
                   -11-  
459                  otp_vendor_test_ctrl_d = reg2hw.otp_vendor_test_ctrl.q;
                     ==>
460                end
                   MISSING_ELSE
                   ==>
461              end
                 MISSING_ELSE
                 ==>
462            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
1	1	1	-	-	-	-	-	-	-	-	Covered	T7,T11,T18
1	1	0	-	-	-	-	-	-	-	-	Covered	T5,T7,T11
1	1	-	1	-	-	-	-	-	-	-	Covered	T7,T11,T18
1	1	-	0	-	-	-	-	-	-	-	Covered	T5,T7,T11
1	1	-	-	1	-	-	-	-	-	-	Covered	T5,T7,T11
1	1	-	-	0	-	-	-	-	-	-	Covered	T5,T7,T11
1	1	-	-	-	1	-	-	-	-	-	Covered	T5,T7,T11
1	1	-	-	-	0	-	-	-	-	-	Covered	T5,T7,T11
1	0	-	-	-	-	1	1	-	-	-	Covered	T1,T2,T6
1	0	-	-	-	-	1	0	-	-	-	Covered	T1,T2,T4
1	0	-	-	-	-	1	-	1	-	-	Covered	T1,T2,T6
1	0	-	-	-	-	1	-	0	-	-	Covered	T1,T2,T4
1	0	-	-	-	-	1	-	-	1	-	Covered	T1,T2,T4
1	0	-	-	-	-	1	-	-	0	-	Covered	T1,T2,T4
1	0	-	-	-	-	1	-	-	-	1	Covered	T2,T4,T6
1	0	-	-	-	-	1	-	-	-	0	Covered	T1,T2,T4
1	0	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

466            if (!rst_ni) begin
               -1-  
467              trans_success_q           <= 1'b0;
                 ==>
468              trans_cnt_oflw_error_q    <= 1'b0;
469              trans_invalid_error_q     <= 1'b0;
470              token_invalid_error_q     <= 1'b0;
471              flash_rma_error_q         <= 1'b0;
472              fatal_prog_error_q        <= 1'b0;
473              fatal_state_error_q       <= 1'b0;
474              sw_claim_transition_if_q  <= MuBi8False;
475              tap_claim_transition_if_q <= MuBi8False;
476              transition_token_q        <= '0;
477              transition_target_q       <= {DecLcStateNumRep{DecLcStRaw}};
478              otp_part_error_q          <= 1'b0;
479              fatal_bus_integ_error_q   <= 1'b0;
480              otp_vendor_test_ctrl_q    <= '0;
481              use_ext_clock_q           <= 1'b0;
482            end else begin
483              // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
484              // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
485              // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
486              // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
487              // ---------------------------------------------------------------
488              // In case of a volatile RAW unlock, this bit has to be cleared when the volatile
489              // unlock is followed by a real transition.
490              // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
491              if (SecVolatileRawUnlockEn && transition_cmd && !volatile_raw_unlock_q) begin
                 -2-  
492                trans_success_q <= 1'b0;
                   ==>
493              end else begin
494                trans_success_q <= trans_success_d | trans_success_q;
                   ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

668            if (!rst_ni) begin
               -1-  
669              lc_done_q <= 1'b0;
                 ==>
670              lc_idle_q <= 1'b0;
671            end else begin
672              lc_done_q <= lc_done_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

525              if (!rst_ni) begin
                 -1-  
526                volatile_raw_unlock_q     <= 1'b0;
                   ==>
527              end else begin
528                volatile_raw_unlock_q     <= volatile_raw_unlock_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : lc_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	28	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	28	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	61004413	57841848	0	0
DecLcCountWidthCheck_A	824	824	0	0
DecLcIdStateWidthCheck_A	824	824	0	0
DecLcStateWidthCheck_A	824	824	0	0
FpvSecCmCtrlKmacIfFsmCheck_A	59409337	0	0	0
FpvSecCmCtrlLcCntCheck_A	56257205	1	0	0
FpvSecCmCtrlLcFsmCheck_A	59562327	0	0	0
FpvSecCmCtrlLcStateCheck_A	57520453	0	0	0
FpvSecCmRegWeOnehotCheck_A	61004413	80	0	0
FpvSecCmTapRegWeOnehotCheck_A	61004413	0	0	0
LcCheckBypassEnKnown_A	61004413	57841848	0	0
LcClkBypReqKnown_A	61004413	57841848	0	0
LcCpuEnKnown_A	61004413	57841848	0	0
LcCreatorSwRwEn_A	61004413	57841848	0	0
LcDftEnKnown_A	61004413	57841848	0	0
LcEscalateEnKnown_A	61004413	57841848	0	0
LcFlashRmaReqKnown_A	61004413	57841848	0	0
LcFlashRmaSeedKnown_A	61004413	57841848	0	0
LcHwDebugEnKnown_A	61004413	57841848	0	0
LcIsoSwRwEn_A	61004413	57841848	0	0
LcIsoSwWrEn_A	61004413	57841848	0	0
LcKeymgrDiv_A	61004413	57841848	0	0
LcKeymgrEnKnown_A	61004413	57841848	0	0
LcNvmDebugEnKnown_A	61004413	57841848	0	0
LcOtpProgramKnown_A	61004413	57841848	0	0
LcOtpTokenKnown_A	61004413	57841848	0	0
LcOwnerSwRwEn_A	61004413	57841848	0	0
LcSeedHwRdEn_A	61004413	57841848	0	0
NumTokenWordsCheck_A	824	824	0	0
OtpTestCtrlWidth_A	824	824	0	0
PwrLcKnown_A	61004413	57841848	0	0
TlOKnown	61004413	57841848	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

DecLcCountWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824	824	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

DecLcIdStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824	824	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

DecLcStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824	824	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FpvSecCmCtrlKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59409337	0	0	0

FpvSecCmCtrlLcCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56257205	1	0	0
T110	262989	1	0	0
T111	10447	0	0	0
T112	8178	0	0	0
T113	5680	0	0	0
T114	14650	0	0	0
T115	24513	0	0	0
T116	93635	0	0	0
T117	34691	0	0	0
T118	44148	0	0	0
T119	29574	0	0	0

FpvSecCmCtrlLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59562327	0	0	0

FpvSecCmCtrlLcStateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57520453	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	80	0	0
T8	104016	0	0	0
T23	63838	0	0	0
T33	20918	0	0	0
T34	30208	0	0	0
T48	33770	0	0	0
T52	179885	0	0	0
T69	20434	20	0	0
T70	0	20	0	0
T71	0	20	0	0
T99	10157	0	0	0
T120	0	10	0	0
T121	0	10	0	0
T122	10864	0	0	0
T123	6529	0	0	0

FpvSecCmTapRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	0	0	0

LcCheckBypassEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcClkBypReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcCpuEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcCreatorSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcDftEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcEscalateEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcFlashRmaReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcFlashRmaSeedKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcHwDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcIsoSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcIsoSwWrEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcKeymgrDiv_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcKeymgrEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcNvmDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcOtpProgramKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcOtpTokenKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcOwnerSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcSeedHwRdEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

NumTokenWordsCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824	824	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpTestCtrlWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824	824	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

PwrLcKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

TlOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
ALWAYS	317	41	41	100.00
ALWAYS	368	41	41	100.00
ALWAYS	466	33	33	100.00
ALWAYS	525	3	3	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	567	1	1	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	582	1	1	100.00
ALWAYS	668	5	5	100.00
CONT_ASSIGN	677	1	1	100.00
CONT_ASSIGN	678	1	1	100.00

212                       logic req_ready;
213        1/1            assign req_ready = dmi_req_ready & dmi_resp_ready;
           Tests:       T1 T2 T3 
214                       dmi_jtag #(
215                         .IdcodeValue(IdcodeValue),
216                         .NumDmiWordAbits(7)
217                       ) u_dmi_jtag (
218                         .clk_i,
219                         .rst_ni,
220                         .testmode_i       ( scanmode          ),
221                         .test_rst_ni      ( scan_rst_ni       ),
222                         .dmi_rst_no       (                   ), // unused
223                         .dmi_req_o        ( dmi_req           ),
224                         .dmi_req_valid_o  ( dmi_req_valid     ),
225                         // unless there is room for response, stall
226                         .dmi_req_ready_i  ( req_ready         ),
227                         .dmi_resp_i       ( dmi_resp          ),
228                         .dmi_resp_ready_o ( dmi_resp_ready    ),
229                         .dmi_resp_valid_i ( dmi_resp_valid    ),
230                         .tck_i            ( tck_muxed         ),
231                         .tms_i            ( jtag_i.tms        ),
232                         .trst_ni          ( trst_n_muxed      ),
233                         .td_i             ( jtag_i.tdi        ),
234                         .td_o             ( jtag_o.tdo        ),
235                         .tdo_oe_o         ( jtag_o.tdo_oe     )
236                       );
237                     
238                       // DMI to TL-UL transducing
239                       tlul_adapter_host #(
240                         .EnableDataIntgGen(1)
241                       ) u_tap_tlul_host (
242                         .clk_i,
243                         .rst_ni,
244                         // do not make a request unless there is room for the response
245                         .req_i        ( dmi_req_valid & dmi_resp_ready         ),
246                         .gnt_o        ( dmi_req_ready                          ),
247                         .addr_i       ( top_pkg::TL_AW'({dmi_req.addr, 2'b00}) ),
248                         .we_i         ( dmi_req.op == dm::DTM_WRITE            ),
249                         .wdata_i      ( dmi_req.data                           ),
250                         .wdata_intg_i ('0                                      ),
251                         .be_i         ( {top_pkg::TL_DBW{1'b1}}                ),
252                         .instr_type_i ( prim_mubi_pkg::MuBi4False              ),
253                         .valid_o      ( dmi_resp_valid                         ),
254                         .rdata_o      ( dmi_resp.data                          ),
255                         .rdata_intg_o (                                        ),
256                         .err_o        (                                        ),
257                         .intg_err_o   (                                        ),
258                         .tl_o         ( tap_tl_h2d                             ),
259                         .tl_i         ( tap_tl_d2h                             )
260                       );
261                     
262                       // TL-UL to DMI transducing
263                       assign dmi_resp.resp = '0; // unused inside dmi_jtag
264                     
265                       // These signals are unused
266                       logic unused_tap_tl_d2h;
267        1/1            assign unused_tap_tl_d2h = ^{
           Tests:       T1 T2 T3 
268                         dmi_req.addr[31:30],
269                         tap_tl_d2h.d_opcode,
270                         tap_tl_d2h.d_param,
271                         tap_tl_d2h.d_size,
272                         tap_tl_d2h.d_source,
273                         tap_tl_d2h.d_sink,
274                         tap_tl_d2h.d_user,
275                         tap_tl_d2h.d_error
276                       };
277                     
278                       ///////////////////////////////////////
279                       // Transition Interface and HW Mutex //
280                       ///////////////////////////////////////
281                     
282                       // All registers are HWext
283                       logic          trans_success_d, trans_success_q;
284                       logic          trans_cnt_oflw_error_d, trans_cnt_oflw_error_q;
285                       logic          trans_invalid_error_d, trans_invalid_error_q;
286                       logic          token_invalid_error_d, token_invalid_error_q;
287                       logic          flash_rma_error_d, flash_rma_error_q;
288                       logic          otp_prog_error_d, fatal_prog_error_q;
289                       logic          state_invalid_error_d, fatal_state_error_q;
290                       logic          otp_part_error_q;
291                       mubi8_t        sw_claim_transition_if_d, sw_claim_transition_if_q;
292                       mubi8_t        tap_claim_transition_if_d, tap_claim_transition_if_q;
293                       logic          transition_cmd;
294                       lc_token_t     transition_token_d, transition_token_q;
295                       ext_dec_lc_state_t transition_target_d, transition_target_q;
296                       // No need to register these.
297                       ext_dec_lc_state_t dec_lc_state;
298                       dec_lc_cnt_t       dec_lc_cnt;
299                       dec_lc_id_state_e  dec_lc_id_state;
300                     
301                       logic lc_idle_d, lc_done_d;
302                     
303                       // Assign hardware revision output
304                       assign hw_rev_o = '{silicon_creator_id: SiliconCreatorId,
305                                           product_id:         ProductId,
306                                           revision_id:        RevisionId,
307                                           reserved:           '0};
308                     
309                       // OTP Vendor control bits
310                       logic ext_clock_switched;
311                       logic use_ext_clock_d, use_ext_clock_q;
312                       logic volatile_raw_unlock_d, volatile_raw_unlock_q;
313                       logic [CsrOtpTestCtrlWidth-1:0] otp_vendor_test_ctrl_d, otp_vendor_test_ctrl_q;
314                       logic [CsrOtpTestStatusWidth-1:0] otp_vendor_test_status;
315                     
316                       always_comb begin : p_csr_assign_outputs
317        1/1              hw2reg = '0;
           Tests:       T1 T2 T3 
318        1/1              hw2reg.status.initialized            = lc_done_d;
           Tests:       T1 T2 T3 
319        1/1              hw2reg.status.ready                  = lc_idle_d;
           Tests:       T1 T2 T3 
320        1/1              hw2reg.status.ext_clock_switched     = ext_clock_switched;
           Tests:       T1 T2 T3 
321        1/1              hw2reg.status.transition_successful  = trans_success_q;
           Tests:       T1 T2 T3 
322        1/1              hw2reg.status.transition_count_error = trans_cnt_oflw_error_q;
           Tests:       T1 T2 T3 
323        1/1              hw2reg.status.transition_error       = trans_invalid_error_q;
           Tests:       T1 T2 T3 
324        1/1              hw2reg.status.token_error            = token_invalid_error_q;
           Tests:       T1 T2 T3 
325        1/1              hw2reg.status.flash_rma_error        = flash_rma_error_q;
           Tests:       T1 T2 T3 
326        1/1              hw2reg.status.otp_error              = fatal_prog_error_q;
           Tests:       T1 T2 T3 
327        1/1              hw2reg.status.state_error            = fatal_state_error_q;
           Tests:       T1 T2 T3 
328        1/1              hw2reg.status.otp_partition_error    = otp_part_error_q;
           Tests:       T1 T2 T3 
329        1/1              hw2reg.status.bus_integ_error        = fatal_bus_integ_error_q;
           Tests:       T1 T2 T3 
330        1/1              hw2reg.lc_state                      = dec_lc_state;
           Tests:       T1 T2 T3 
331        1/1              hw2reg.lc_transition_cnt             = dec_lc_cnt;
           Tests:       T1 T2 T3 
332        1/1              hw2reg.lc_id_state                   = {DecLcIdStateNumRep{dec_lc_id_state}};
           Tests:       T1 T2 T3 
333        1/1              hw2reg.device_id                     = otp_device_id_i;
           Tests:       T1 T2 T3 
334        1/1              hw2reg.manuf_state                   = otp_manuf_state_i;
           Tests:       T1 T2 T3 
335        1/1              hw2reg.hw_revision0.silicon_creator_id = hw_rev_o.silicon_creator_id;
           Tests:       T1 T2 T3 
336        1/1              hw2reg.hw_revision0.product_id         = hw_rev_o.product_id;
           Tests:       T1 T2 T3 
337        1/1              hw2reg.hw_revision1.revision_id        = hw_rev_o.revision_id;
           Tests:       T1 T2 T3 
338        1/1              hw2reg.hw_revision1.reserved           = '0;
           Tests:       T1 T2 T3 
339                     
340                         // The assignments above are identical for the TAP.
341        1/1              tap_hw2reg = hw2reg;
           Tests:       T1 T2 T3 
342                     
343                         // Assignments gated by mutex. Again, the TAP has priority.
344        1/1              tap_hw2reg.claim_transition_if = tap_claim_transition_if_q;
           Tests:       T1 T2 T3 
345        1/1              hw2reg.claim_transition_if = sw_claim_transition_if_q;
           Tests:       T1 T2 T3 
346        1/1              if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
347        1/1                tap_hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
           Tests:       T5 T7 T11 
348        1/1                tap_hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
           Tests:       T5 T7 T11 
349        1/1                tap_hw2reg.transition_token  = transition_token_q;
           Tests:       T5 T7 T11 
350        1/1                tap_hw2reg.transition_target = transition_target_q;
           Tests:       T5 T7 T11 
351                           // SEC_CM: TRANSITION.CONFIG.REGWEN
352        1/1                tap_hw2reg.transition_regwen = lc_idle_d;
           Tests:       T5 T7 T11 
353        1/1                tap_hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
           Tests:       T5 T7 T11 
354        1/1                tap_hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
           Tests:       T5 T7 T11 
355        1/1              end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
356        1/1                hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
           Tests:       T1 T2 T4 
357        1/1                hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
           Tests:       T1 T2 T4 
358        1/1                hw2reg.transition_token  = transition_token_q;
           Tests:       T1 T2 T4 
359        1/1                hw2reg.transition_target = transition_target_q;
           Tests:       T1 T2 T4 
360                           // SEC_CM: TRANSITION.CONFIG.REGWEN
361        1/1                hw2reg.transition_regwen = lc_idle_d;
           Tests:       T1 T2 T4 
362        1/1                hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
           Tests:       T1 T2 T4 
363        1/1                hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
           Tests:       T1 T2 T4 
364                         end
                        MISSING_ELSE
365                       end
366                     
367                       always_comb begin : p_csr_assign_inputs
368        1/1              sw_claim_transition_if_d  = sw_claim_transition_if_q;
           Tests:       T1 T2 T3 
369        1/1              tap_claim_transition_if_d = tap_claim_transition_if_q;
           Tests:       T1 T2 T3 
370        1/1              transition_token_d        = transition_token_q;
           Tests:       T1 T2 T3 
371        1/1              transition_target_d       = transition_target_q;
           Tests:       T1 T2 T3 
372        1/1              transition_cmd            = 1'b0;
           Tests:       T1 T2 T3 
373        1/1              otp_vendor_test_ctrl_d    = otp_vendor_test_ctrl_q;
           Tests:       T1 T2 T3 
374        1/1              use_ext_clock_d           = use_ext_clock_q;
           Tests:       T1 T2 T3 
375        1/1              volatile_raw_unlock_d     = volatile_raw_unlock_q;
           Tests:       T1 T2 T3 
376                     
377                         // Note that the mutex claims from the TAP and SW side could arrive within the same cycle.
378                         // In that case we give priority to the TAP mutex claim in order to avoid a race condition.
379                         // TAP mutex claim.
380        1/1              if (mubi8_test_false_loose(sw_claim_transition_if_q) &&
           Tests:       T1 T2 T3 
381                             tap_reg2hw.claim_transition_if.qe) begin
382        1/1                tap_claim_transition_if_d = mubi8_t'(tap_reg2hw.claim_transition_if.q);
           Tests:       T1 T2 T3 
383                         // SW mutex claim.
384        1/1              end else if (mubi8_test_false_loose(tap_claim_transition_if_q) &&
           Tests:       T1 T2 T3 
385                             reg2hw.claim_transition_if.qe) begin
386        1/1                sw_claim_transition_if_d = mubi8_t'(reg2hw.claim_transition_if.q);
           Tests:       T1 T2 T3 
387                         end
                        MISSING_ELSE
388                     
389                     
390                         // The idle signal serves as the REGWEN in this case.
391        1/1              if (lc_idle_d) begin
           Tests:       T1 T2 T3 
392                           // The TAP has priority.
393        1/1                if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
394        1/1                  transition_cmd = tap_reg2hw.transition_cmd.q &
           Tests:       T5 T7 T11 
395                                              tap_reg2hw.transition_cmd.qe;
396                     
397        1/1                  if (tap_reg2hw.transition_ctrl.ext_clock_en.qe) begin
           Tests:       T5 T7 T11 
398        1/1                    use_ext_clock_d |= tap_reg2hw.transition_ctrl.ext_clock_en.q;
           Tests:       T7 T11 T18 
399                             end
                        MISSING_ELSE
400                     
401                             // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
402                             // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
403                             // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
404                             // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
405                             // ---------------------------------------------------------------
406        1/1                  if (tap_reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
           Tests:       T5 T7 T11 
407        1/1                    volatile_raw_unlock_d = tap_reg2hw.transition_ctrl.volatile_raw_unlock.q;
           Tests:       T7 T11 T18 
408                             end
                        MISSING_ELSE
409                             // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
410                     
411        1/1                  for (int k = 0; k < LcTokenWidth/32; k++) begin
           Tests:       T5 T7 T11 
412        1/1                    if (tap_reg2hw.transition_token[k].qe) begin
           Tests:       T5 T7 T11 
413        1/1                      transition_token_d[k*32 +: 32] = tap_reg2hw.transition_token[k].q;
           Tests:       T5 T7 T11 
414                               end
                        MISSING_ELSE
415                             end
416                     
417        1/1                  if (tap_reg2hw.transition_target.qe) begin
           Tests:       T5 T7 T11 
418        1/1                    for (int k = 0; k < DecLcStateNumRep; k++) begin
           Tests:       T5 T7 T11 
419        1/1                      transition_target_d[k] = dec_lc_state_e'(
           Tests:       T5 T7 T11 
420                                     tap_reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
421                               end
422                             end
                        MISSING_ELSE
423                     
424        1/1                  if (tap_reg2hw.otp_vendor_test_ctrl.qe) begin
           Tests:       T5 T7 T11 
425        1/1                    otp_vendor_test_ctrl_d = tap_reg2hw.otp_vendor_test_ctrl.q;
           Tests:       T5 T7 T11 
426                             end
                        MISSING_ELSE
427        1/1                end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
           Tests:       T1 T2 T3 
428        1/1                  transition_cmd = reg2hw.transition_cmd.q &
           Tests:       T1 T2 T4 
429                                              reg2hw.transition_cmd.qe;
430                     
431        1/1                  if (reg2hw.transition_ctrl.ext_clock_en.qe) begin
           Tests:       T1 T2 T4 
432        1/1                    use_ext_clock_d |= reg2hw.transition_ctrl.ext_clock_en.q;
           Tests:       T1 T2 T6 
433                             end
                        MISSING_ELSE
434                     
435                             // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
436                             // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
437                             // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
438                             // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
439                             // ---------------------------------------------------------------
440        1/1                  if (reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
           Tests:       T1 T2 T4 
441        1/1                    volatile_raw_unlock_d = reg2hw.transition_ctrl.volatile_raw_unlock.q;
           Tests:       T1 T2 T6 
442                             end
                        MISSING_ELSE
443                             // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
444                     
445        1/1                  for (int k = 0; k < LcTokenWidth/32; k++) begin
           Tests:       T1 T2 T4 
446        1/1                    if (reg2hw.transition_token[k].qe) begin
           Tests:       T1 T2 T4 
447        1/1                      transition_token_d[k*32 +: 32] = reg2hw.transition_token[k].q;
           Tests:       T1 T2 T4 
448                               end
                        MISSING_ELSE
449                             end
450                     
451        1/1                  if (reg2hw.transition_target.qe) begin
           Tests:       T1 T2 T4 
452        1/1                    for (int k = 0; k < DecLcStateNumRep; k++) begin
           Tests:       T1 T2 T4 
453        1/1                      transition_target_d[k] = dec_lc_state_e'(
           Tests:       T1 T2 T4 
454                                     reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
455                               end
456                             end
                        MISSING_ELSE
457                     
458        1/1                  if (reg2hw.otp_vendor_test_ctrl.qe) begin
           Tests:       T1 T2 T4 
459        1/1                    otp_vendor_test_ctrl_d = reg2hw.otp_vendor_test_ctrl.q;
           Tests:       T2 T4 T6 
460                             end
                        MISSING_ELSE
461                           end
                        MISSING_ELSE
462                         end
                        MISSING_ELSE
463                       end
464                     
465                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_csrs
466        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
467        1/1                trans_success_q           <= 1'b0;
           Tests:       T1 T2 T3 
468        1/1                trans_cnt_oflw_error_q    <= 1'b0;
           Tests:       T1 T2 T3 
469        1/1                trans_invalid_error_q     <= 1'b0;
           Tests:       T1 T2 T3 
470        1/1                token_invalid_error_q     <= 1'b0;
           Tests:       T1 T2 T3 
471        1/1                flash_rma_error_q         <= 1'b0;
           Tests:       T1 T2 T3 
472        1/1                fatal_prog_error_q        <= 1'b0;
           Tests:       T1 T2 T3 
473        1/1                fatal_state_error_q       <= 1'b0;
           Tests:       T1 T2 T3 
474        1/1                sw_claim_transition_if_q  <= MuBi8False;
           Tests:       T1 T2 T3 
475        1/1                tap_claim_transition_if_q <= MuBi8False;
           Tests:       T1 T2 T3 
476        1/1                transition_token_q        <= '0;
           Tests:       T1 T2 T3 
477        1/1                transition_target_q       <= {DecLcStateNumRep{DecLcStRaw}};
           Tests:       T1 T2 T3 
478        1/1                otp_part_error_q          <= 1'b0;
           Tests:       T1 T2 T3 
479        1/1                fatal_bus_integ_error_q   <= 1'b0;
           Tests:       T1 T2 T3 
480        1/1                otp_vendor_test_ctrl_q    <= '0;
           Tests:       T1 T2 T3 
481        1/1                use_ext_clock_q           <= 1'b0;
           Tests:       T1 T2 T3 
482                         end else begin
483                           // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
484                           // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
485                           // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
486                           // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
487                           // ---------------------------------------------------------------
488                           // In case of a volatile RAW unlock, this bit has to be cleared when the volatile
489                           // unlock is followed by a real transition.
490                           // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
491        1/1                if (SecVolatileRawUnlockEn && transition_cmd && !volatile_raw_unlock_q) begin
           Tests:       T1 T2 T3 
492        1/1                  trans_success_q <= 1'b0;
           Tests:       T2 T4 T5 
493                           end else begin
494        1/1                  trans_success_q <= trans_success_d | trans_success_q;
           Tests:       T1 T2 T3 
495                           end
496                           // All other status and error bits are terminal and require a reset cycle.
497        1/1                trans_cnt_oflw_error_q    <= trans_cnt_oflw_error_d  | trans_cnt_oflw_error_q;
           Tests:       T1 T2 T3 
498        1/1                trans_invalid_error_q     <= trans_invalid_error_d   | trans_invalid_error_q;
           Tests:       T1 T2 T3 
499        1/1                token_invalid_error_q     <= token_invalid_error_d   | token_invalid_error_q;
           Tests:       T1 T2 T3 
500        1/1                flash_rma_error_q         <= flash_rma_error_d       | flash_rma_error_q;
           Tests:       T1 T2 T3 
501        1/1                fatal_prog_error_q        <= otp_prog_error_d        | fatal_prog_error_q;
           Tests:       T1 T2 T3 
502        1/1                fatal_state_error_q       <= state_invalid_error_d   | fatal_state_error_q;
           Tests:       T1 T2 T3 
503        1/1                otp_part_error_q          <= otp_lc_data_i.error     | otp_part_error_q;
           Tests:       T1 T2 T3 
504        1/1                fatal_bus_integ_error_q   <= fatal_bus_integ_error_csr_d |
           Tests:       T1 T2 T3 
505                                                        fatal_bus_integ_error_tap_d |
506                                                        fatal_bus_integ_error_q;
507                           // Other regs, gated by mutex further below.
508        1/1                sw_claim_transition_if_q  <= sw_claim_transition_if_d;
           Tests:       T1 T2 T3 
509        1/1                tap_claim_transition_if_q <= tap_claim_transition_if_d;
           Tests:       T1 T2 T3 
510        1/1                transition_token_q        <= transition_token_d;
           Tests:       T1 T2 T3 
511        1/1                transition_target_q       <= transition_target_d;
           Tests:       T1 T2 T3 
512        1/1                otp_vendor_test_ctrl_q    <= otp_vendor_test_ctrl_d;
           Tests:       T1 T2 T3 
513        1/1                use_ext_clock_q           <= use_ext_clock_d;
           Tests:       T1 T2 T3 
514                         end
515                       end
516                     
517                       // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
518                       // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
519                       // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
520                       // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
521                       // ---------------------------------------------------------------
522                       // If not enabled, this register will become a constant.
523                       if (SecVolatileRawUnlockEn) begin : gen_volatile_raw_unlock_reg
524                         always_ff @(posedge clk_i or negedge rst_ni) begin : p_volatile_raw_unlock_reg
525        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
526        1/1                  volatile_raw_unlock_q     <= 1'b0;
           Tests:       T1 T2 T3 
527                           end else begin
528        1/1                  volatile_raw_unlock_q     <= volatile_raw_unlock_d;
           Tests:       T1 T2 T3 
529                           end
530                         end
531                       end else begin : gen_volatile_raw_unlock_const
532                         logic unused_volatile_raw_unlock;
533                         assign unused_volatile_raw_unlock = ^volatile_raw_unlock_d;
534                         assign volatile_raw_unlock_q = 1'b0;
535                       end
536                       // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
537                     
538        1/1            assign lc_flash_rma_seed_o = transition_token_q[RmaSeedWidth-1:0];
           Tests:       T1 T2 T3 
539                     
540                       // Gate the vendor specific test ctrl/status bits to zero in production states.
541                       // Buffer the enable signal to prevent optimization of the multibit signal.
542                       lc_tx_t lc_raw_test_rma;
543                       lc_tx_t [1:0] lc_raw_test_rma_buf;
544                       prim_lc_sync #(
545                         .NumCopies(2),
546                         .AsyncOn(0)
547                       ) u_prim_lc_sync (
548                         .clk_i,
549                         .rst_ni,
550                         .lc_en_i(lc_raw_test_rma),
551                         .lc_en_o(lc_raw_test_rma_buf)
552                       );
553                     
554        1/1            assign lc_otp_vendor_test_o.ctrl = (lc_tx_test_true_strict(lc_raw_test_rma_buf[0])) ?
           Tests:       T1 T2 T3 
555                                                          otp_vendor_test_ctrl_q                           : '0;
556        1/1            assign otp_vendor_test_status    = (lc_tx_test_true_strict(lc_raw_test_rma_buf[1])) ?
           Tests:       T1 T2 T3 
557                                                          lc_otp_vendor_test_i.status                      : '0;
558                     
559                       //////////////////
560                       // Alert Sender //
561                       //////////////////
562                     
563                       logic [NumAlerts-1:0] alerts;
564                       logic [NumAlerts-1:0] alert_test;
565                       logic [NumAlerts-1:0] tap_alert_test;
566                     
567        1/1            assign alerts = {
           Tests:       T1 T2 T3 
568                         fatal_bus_integ_error_q,
569                         fatal_state_error_q,
570                         fatal_prog_error_q
571                       };
572                     
573        1/1            assign alert_test = {
           Tests:       T1 T2 T3 
574                         reg2hw.alert_test.fatal_bus_integ_error.q &
575                         reg2hw.alert_test.fatal_bus_integ_error.qe,
576                         reg2hw.alert_test.fatal_state_error.q &
577                         reg2hw.alert_test.fatal_state_error.qe,
578                         reg2hw.alert_test.fatal_prog_error.q &
579                         reg2hw.alert_test.fatal_prog_error.qe
580                       };
581                     
582        1/1             assign tap_alert_test = {
           Tests:       T1 T2 T3 
583                         tap_reg2hw.alert_test.fatal_bus_integ_error.q &
584                         tap_reg2hw.alert_test.fatal_bus_integ_error.qe,
585                         tap_reg2hw.alert_test.fatal_state_error.q &
586                         tap_reg2hw.alert_test.fatal_state_error.qe,
587                         tap_reg2hw.alert_test.fatal_prog_error.q &
588                         tap_reg2hw.alert_test.fatal_prog_error.qe
589                       };
590                     
591                       for (genvar k = 0; k < NumAlerts; k++) begin : gen_alert_tx
592                         prim_alert_sender #(
593                           .AsyncOn(AlertAsyncOn[k]),
594                           .IsFatal(1)
595                         ) u_prim_alert_sender (
596                           .clk_i,
597                           .rst_ni,
598                           .alert_test_i  ( alert_test[k] |
599                                            tap_alert_test[k] ),
600                           .alert_req_i   ( alerts[k]         ),
601                           .alert_ack_o   (                   ),
602                           .alert_state_o (                   ),
603                           .alert_rx_i    ( alert_rx_i[k]     ),
604                           .alert_tx_o    ( alert_tx_o[k]     )
605                         );
606                       end
607                     
608                       //////////////////////////
609                       // Escalation Receivers //
610                       //////////////////////////
611                     
612                       // SEC_CM: MAIN.FSM.GLOBAL_ESC
613                       // We still have two escalation receivers here for historical reasons.
614                       // The two actions "wipe secrets" and "scrap lifecycle state" have been
615                       // combined in order to simplify both DV and the design, as otherwise
616                       // this separation of very intertwined actions would have caused too many
617                       // unnecessary corner cases. The escalation receivers are now redundant and
618                       // trigger both actions at once.
619                     
620                       // This escalation action moves the life cycle
621                       // state into a temporary "SCRAP" state named "ESCALATE",
622                       // and asserts the lc_escalate_en life cycle control signal.
623                       logic esc_scrap_state0;
624                       prim_esc_receiver #(
625                         .N_ESC_SEV   (alert_handler_reg_pkg::N_ESC_SEV),
626                         .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW)
627                       ) u_prim_esc_receiver0 (
628                         .clk_i,
629                         .rst_ni,
630                         .esc_req_o (esc_scrap_state0),
631                         .esc_rx_o  (esc_scrap_state0_rx_o),
632                         .esc_tx_i  (esc_scrap_state0_tx_i)
633                       );
634                     
635                       // This escalation action moves the life cycle
636                       // state into a temporary "SCRAP" state named "ESCALATE".
637                       logic esc_scrap_state1;
638                       prim_esc_receiver #(
639                         .N_ESC_SEV   (alert_handler_reg_pkg::N_ESC_SEV),
640                         .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW)
641                       ) u_prim_esc_receiver1 (
642                         .clk_i,
643                         .rst_ni,
644                         .esc_req_o (esc_scrap_state1),
645                         .esc_rx_o  (esc_scrap_state1_rx_o),
646                         .esc_tx_i  (esc_scrap_state1_tx_i)
647                       );
648                     
649                       ////////////////////////////
650                       // Synchronization of IOs //
651                       ////////////////////////////
652                     
653                       // Signals going to and coming from power manager.
654                       logic lc_init;
655                       prim_flop_2sync #(
656                         .Width(1)
657                       ) u_prim_flop_2sync_init (
658                         .clk_i,
659                         .rst_ni,
660                         .d_i(pwr_lc_i.lc_init),
661                         .q_o(lc_init)
662                       );
663                     
664                       logic lc_done_q;
665                       logic lc_idle_q;
666                     
667                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_sync_regs
668        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
669        1/1                lc_done_q <= 1'b0;
           Tests:       T1 T2 T3 
670        1/1                lc_idle_q <= 1'b0;
           Tests:       T1 T2 T3 
671                         end else begin
672        1/1                lc_done_q <= lc_done_d;
           Tests:       T1 T2 T3 
673        1/1                lc_idle_q <= lc_idle_d;
           Tests:       T1 T2 T3 
674                         end
675                       end
676                     
677        1/1            assign pwr_lc_o.lc_done = lc_done_q;
           Tests:       T1 T2 T3 
678        1/1            assign pwr_lc_o.lc_idle = lc_idle_q;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	71	59	83.10
Logical	71	59	83.10
Non-Logical	0	0
Event	0	0

 LINE       213
 EXPRESSION (dmi_req_ready & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T5,T7

 LINE       241
 EXPRESSION (dmi_req_valid & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T7
1	0	Not Covered
1	1	Covered	T6,T5,T7

 LINE       241
 EXPRESSION (dmi_req.op == DTM_WRITE)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T5,T7

 LINE       394
 EXPRESSION (tap_reg2hw.transition_cmd.q & tap_reg2hw.transition_cmd.qe)
             -------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T11
1	1	Covered	T5,T7,T18

 LINE       428
 EXPRESSION (reg2hw.transition_cmd.q & reg2hw.transition_cmd.qe)
             -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       491
 EXPRESSION (SecVolatileRawUnlockEn && transition_cmd && ((!volatile_raw_unlock_q)))
             -----------1----------    -------2------    -------------3------------

-1-	-2-	-3-	Status	Tests
-	0	1	Covered	T1,T2,T3
-	1	0	Covered	T1,T24,T41
-	1	1	Covered	T2,T4,T5

 LINE       494
 EXPRESSION (trans_success_d | trans_success_q)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       497
 EXPRESSION (trans_cnt_oflw_error_d | trans_cnt_oflw_error_q)
             -----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T45,T52
1	0	Covered	T13,T45,T52

 LINE       498
 EXPRESSION (trans_invalid_error_d | trans_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T13,T42
1	0	Covered	T1,T6,T11

 LINE       499
 EXPRESSION (token_invalid_error_d | token_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T16,T42
1	0	Covered	T13,T16,T42

 LINE       500
 EXPRESSION (flash_rma_error_d | flash_rma_error_q)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T16,T45
1	0	Covered	T13,T16,T45

 LINE       501
 EXPRESSION (otp_prog_error_d | fatal_prog_error_q)
             --------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T13
1	0	Covered	T4,T5,T13

 LINE       502
 EXPRESSION (state_invalid_error_d | fatal_state_error_q)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T16,T20
1	0	Covered	T12,T16,T20

 LINE       503
 EXPRESSION (otp_lc_data_i.error | otp_part_error_q)
             ---------1---------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T44,T100
1	0	Covered	T13,T45,T52

 LINE       504
 EXPRESSION (fatal_bus_integ_error_csr_d | fatal_bus_integ_error_tap_d | fatal_bus_integ_error_q)
             -------------1-------------   -------------2-------------   -----------3-----------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T1,T2,T3
0	0	1	Excluded		VC_COV_UNR
0	1	0	Covered	T69,T70,T71
1	0	0	Covered	T69,T70,T71

 LINE       573
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T25,T97,T101
1	0	Covered	T1,T2,T3
1	1	Covered	T25,T97,T101

 LINE       573
 SUB-EXPRESSION (reg2hw.alert_test.fatal_state_error.q & reg2hw.alert_test.fatal_state_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T25,T97,T101
1	0	Covered	T1,T2,T3
1	1	Covered	T25,T97,T101

 LINE       573
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prog_error.q & reg2hw.alert_test.fatal_prog_error.qe)
                 ------------------1-----------------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T25,T97,T101
1	0	Covered	T1,T2,T3
1	1	Covered	T25,T97,T101

 LINE       582
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_bus_integ_error.q & tap_reg2hw.alert_test.fatal_bus_integ_error.qe)
                 ----------------------1----------------------   -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T5,T7
1	1	Not Covered

 LINE       582
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_state_error.q & tap_reg2hw.alert_test.fatal_state_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T5,T7
1	1	Not Covered

 LINE       582
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_prog_error.q & tap_reg2hw.alert_test.fatal_prog_error.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T5,T7
1	1	Not Covered

 LINE       595
 EXPRESSION (alert_test[0] | tap_alert_test[0])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T25,T97,T101

 LINE       595
 EXPRESSION (alert_test[1] | tap_alert_test[1])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T25,T97,T101

 LINE       595
 EXPRESSION (alert_test[2] | tap_alert_test[2])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T25,T97,T101

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	101	100	99.01
Total Bits	7297	7289	99.89
Total Bits 0->1	3649	3645	99.89
Total Bits 1->0	3648	3644	99.89

Ports	101	100	99.01
Port Bits	7297	7289	99.89
Port Bits 0->1	3649	3645	99.89
Port Bits 1->0	3648	3644	99.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
clk_kmac_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_kmac_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T11,T13,T25	Yes	T11,T13,T25	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T4,T6	Yes	T2,T4,T6	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T52,T102,T103	Yes	T52,T102,T103	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
jtag_i.tdi	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	INPUT
jtag_i.trst_n	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
jtag_i.tms	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	INPUT
jtag_i.tck	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	INPUT
jtag_o.tdo_oe	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	OUTPUT
jtag_o.tdo	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	OUTPUT
scan_rst_ni	Yes	Yes	T6,T8,T9	Yes	T8,T9,T10	INPUT
scanmode_i[3:0]	No	No		No		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T12,T25,T16	Yes	T12,T25,T16	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T25,T97,T101	Yes	T25,T97,T101	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T12,T25,T16	Yes	T12,T25,T16	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T25,T97,T101	Yes	T25,T97,T101	OUTPUT
esc_scrap_state0_tx_i.resp_n	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	INPUT
esc_scrap_state0_tx_i.resp_p	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	INPUT
esc_scrap_state0_rx_o.esc_n	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	OUTPUT
esc_scrap_state0_rx_o.esc_p	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	OUTPUT
esc_scrap_state1_tx_i.resp_n	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	INPUT
esc_scrap_state1_tx_i.resp_p	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	INPUT
esc_scrap_state1_rx_o.esc_n	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	OUTPUT
esc_scrap_state1_rx_o.esc_p	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	OUTPUT
pwr_lc_i.lc_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_lc_o.lc_idle	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
pwr_lc_o.lc_done	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
strap_en_override_o	Yes	Excluded		Yes	T1,T24,T41	OUTPUT	1->0:VC_COV_UNR
lc_otp_vendor_test_o.ctrl[31:0]	Yes	Yes	T4,T17,T42	Yes	T4,T11,T17	OUTPUT
lc_otp_vendor_test_i.status[31:0]	Yes	Yes	T2,T12,T42	Yes	T2,T12,T24	INPUT
lc_otp_program_o.count[383:0]	Yes	Yes	T53,T104,T105	Yes	T53,T104,T105	OUTPUT
lc_otp_program_o.state[319:0]	Yes	Yes	T54,T106,T107	Yes	T54,T106,T107	OUTPUT
lc_otp_program_o.req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
lc_otp_program_i.ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
lc_otp_program_i.err	Yes	Yes	T52,T102,T108	Yes	T52,T102,T109	INPUT
kmac_data_i.error	Yes	Yes	T13,T45,T52	Yes	T13,T45,T52	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T7,T12,T13	Yes	T2,T7,T12	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T2,T7,T12	Yes	T2,T7,T12	INPUT
kmac_data_i.done	Yes	Yes	T2,T7,T12	Yes	T2,T7,T12	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T2,T7,T12	Yes	T2,T7,T12	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T2,T7,T12	Yes	T2,T7,T12	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T2,T7,T12	Yes	T2,T7,T12	OUTPUT
kmac_data_o.valid	Yes	Yes	T2,T7,T12	Yes	T2,T7,T12	OUTPUT
otp_lc_data_i.rma_token[127:0]	Yes	Yes	T2,T7,T12	Yes	T2,T4,T5	INPUT
otp_lc_data_i.rma_token_valid[3:0]	Yes	Yes	T16,T46,T37	Yes	T16,T46,T37	INPUT
otp_lc_data_i.test_exit_token[127:0]	Yes	Yes	T2,T4,T5	Yes	T4,T5,T7	INPUT
otp_lc_data_i.test_unlock_token[127:0]	Yes	Yes	T2,T4,T5	Yes	T4,T7,T12	INPUT
otp_lc_data_i.test_tokens_valid[3:0]	Yes	Yes	T16,T46,T37	Yes	T16,T46,T37	INPUT
otp_lc_data_i.secrets_valid[3:0]	Yes	Yes	T16,T46,T37	Yes	T16,T46,T37	INPUT
otp_lc_data_i.count[383:0]	Yes	Yes	T53,T104,T105	Yes	T53,T104,T105	INPUT
otp_lc_data_i.state[319:0]	Yes	Yes	T54,T106,T107	Yes	T54,T106,T107	INPUT
otp_lc_data_i.error	Yes	Yes	T13,T45,T52	Yes	T13,T45,T52	INPUT
otp_lc_data_i.valid	Yes	Yes	T12,T53,T54	Yes	T12,T53,T54	INPUT
lc_dft_en_o[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
lc_nvm_debug_en_o[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
lc_hw_debug_en_o[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
lc_cpu_en_o[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
lc_creator_seed_sw_rw_en_o[3:0]	Yes	Yes	T2,T4,T7	Yes	T2,T4,T7	OUTPUT
lc_owner_seed_sw_rw_en_o[3:0]	Yes	Yes	T2,T4,T7	Yes	T2,T4,T7	OUTPUT
lc_iso_part_sw_rd_en_o[3:0]	Yes	Yes	T4,T7,T12	Yes	T4,T7,T12	OUTPUT
lc_iso_part_sw_wr_en_o[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
lc_seed_hw_rd_en_o[3:0]	Yes	Yes	T12,T13,T15	Yes	T12,T13,T15	OUTPUT
lc_keymgr_en_o[3:0]	Yes	Yes	T2,T4,T7	Yes	T2,T4,T7	OUTPUT
lc_escalate_en_o[3:0]	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	OUTPUT
lc_check_byp_en_o[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
lc_clk_byp_req_o[3:0]	Yes	Yes	T7,T14,T17	Yes	T7,T11,T14	OUTPUT
lc_clk_byp_ack_i[3:0]	Yes	Yes	T7,T13,T14	Yes	T7,T13,T14	INPUT
lc_flash_rma_seed_o[31:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T4	OUTPUT
lc_flash_rma_req_o[3:0]	Yes	Yes	T2,T7,T14	Yes	T2,T7,T14	OUTPUT
lc_keymgr_div_o[127:0]	Yes	Yes	T2,T4,T7	Yes	T2,T4,T7	OUTPUT
otp_device_id_i[255:0]	Yes	Yes	T4,T7,T13	Yes	T4,T7,T13	INPUT
otp_manuf_state_i[255:0]	Yes	Yes	T5,T12,T13	Yes	T1,T3,T5	INPUT
hw_rev_o.reserved[23:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
hw_rev_o.revision_id[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
hw_rev_o.product_id[15:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
hw_rev_o.silicon_creator_id[15:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		31	31	100.00
IF	346	3	3	100.00
IF	380	3	3	100.00
IF	391	18	18	100.00
IF	466	3	3	100.00
IF	668	2	2	100.00
IF	525	2	2	100.00

346            if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
               -1-                                                
347              tap_hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
                 ==>
348              tap_hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
349              tap_hw2reg.transition_token  = transition_token_q;
350              tap_hw2reg.transition_target = transition_target_q;
351              // SEC_CM: TRANSITION.CONFIG.REGWEN
352              tap_hw2reg.transition_regwen = lc_idle_d;
353              tap_hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
354              tap_hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
355            end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
                        -2-                                               
356              hw2reg.transition_ctrl.ext_clock_en = use_ext_clock_q;
                 ==>
357              hw2reg.transition_ctrl.volatile_raw_unlock = volatile_raw_unlock_q;
358              hw2reg.transition_token  = transition_token_q;
359              hw2reg.transition_target = transition_target_q;
360              // SEC_CM: TRANSITION.CONFIG.REGWEN
361              hw2reg.transition_regwen = lc_idle_d;
362              hw2reg.otp_vendor_test_ctrl     = otp_vendor_test_ctrl_q;
363              hw2reg.otp_vendor_test_status   = otp_vendor_test_status;
364            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T7,T11
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

380            if (mubi8_test_false_loose(sw_claim_transition_if_q) &&
               -1-                                               
381                tap_reg2hw.claim_transition_if.qe) begin
382              tap_claim_transition_if_d = mubi8_t'(tap_reg2hw.claim_transition_if.q);
                 ==>
383            // SW mutex claim.
384            end else if (mubi8_test_false_loose(tap_claim_transition_if_q) &&
                        -2-                                                
385                reg2hw.claim_transition_if.qe) begin
386              sw_claim_transition_if_d = mubi8_t'(reg2hw.claim_transition_if.q);
                 ==>
387            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

391            if (lc_idle_d) begin
               -1-  
392              // The TAP has priority.
393              if (mubi8_test_true_strict(tap_claim_transition_if_q)) begin
                 -2-                                                
394                transition_cmd = tap_reg2hw.transition_cmd.q &
395                                 tap_reg2hw.transition_cmd.qe;
396        
397                if (tap_reg2hw.transition_ctrl.ext_clock_en.qe) begin
                   -3-  
398                  use_ext_clock_d |= tap_reg2hw.transition_ctrl.ext_clock_en.q;
                     ==>
399                end
                   MISSING_ELSE
                   ==>
400        
401                // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
402                // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
403                // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
404                // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
405                // ---------------------------------------------------------------
406                if (tap_reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
                   -4-  
407                  volatile_raw_unlock_d = tap_reg2hw.transition_ctrl.volatile_raw_unlock.q;
                     ==>
408                end
                   MISSING_ELSE
                   ==>
409                // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
410        
411                for (int k = 0; k < LcTokenWidth/32; k++) begin
412                  if (tap_reg2hw.transition_token[k].qe) begin
413                    transition_token_d[k*32 +: 32] = tap_reg2hw.transition_token[k].q;
414                  end
415                end
416        
417                if (tap_reg2hw.transition_target.qe) begin
                   -5-  
418                  for (int k = 0; k < DecLcStateNumRep; k++) begin
                     ==>
419                    transition_target_d[k] = dec_lc_state_e'(
420                        tap_reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
421                  end
422                end
                   MISSING_ELSE
                   ==>
423        
424                if (tap_reg2hw.otp_vendor_test_ctrl.qe) begin
                   -6-  
425                  otp_vendor_test_ctrl_d = tap_reg2hw.otp_vendor_test_ctrl.q;
                     ==>
426                end
                   MISSING_ELSE
                   ==>
427              end else if (mubi8_test_true_strict(sw_claim_transition_if_q)) begin
                          -7-                                               
428                transition_cmd = reg2hw.transition_cmd.q &
429                                 reg2hw.transition_cmd.qe;
430        
431                if (reg2hw.transition_ctrl.ext_clock_en.qe) begin
                   -8-  
432                  use_ext_clock_d |= reg2hw.transition_ctrl.ext_clock_en.q;
                     ==>
433                end
                   MISSING_ELSE
                   ==>
434        
435                // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
436                // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
437                // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
438                // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
439                // ---------------------------------------------------------------
440                if (reg2hw.transition_ctrl.volatile_raw_unlock.qe) begin
                   -9-  
441                  volatile_raw_unlock_d = reg2hw.transition_ctrl.volatile_raw_unlock.q;
                     ==>
442                end
                   MISSING_ELSE
                   ==>
443                // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
444        
445                for (int k = 0; k < LcTokenWidth/32; k++) begin
446                  if (reg2hw.transition_token[k].qe) begin
447                    transition_token_d[k*32 +: 32] = reg2hw.transition_token[k].q;
448                  end
449                end
450        
451                if (reg2hw.transition_target.qe) begin
                   -10-  
452                  for (int k = 0; k < DecLcStateNumRep; k++) begin
                     ==>
453                    transition_target_d[k] = dec_lc_state_e'(
454                        reg2hw.transition_target.q[k*DecLcStateWidth +: DecLcStateWidth]);
455                  end
456                end
                   MISSING_ELSE
                   ==>
457        
458                if (reg2hw.otp_vendor_test_ctrl.qe) begin
                   -11-  
459                  otp_vendor_test_ctrl_d = reg2hw.otp_vendor_test_ctrl.q;
                     ==>
460                end
                   MISSING_ELSE
                   ==>
461              end
                 MISSING_ELSE
                 ==>
462            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
1	1	1	-	-	-	-	-	-	-	-	Covered	T7,T11,T18
1	1	0	-	-	-	-	-	-	-	-	Covered	T5,T7,T11
1	1	-	1	-	-	-	-	-	-	-	Covered	T7,T11,T18
1	1	-	0	-	-	-	-	-	-	-	Covered	T5,T7,T11
1	1	-	-	1	-	-	-	-	-	-	Covered	T5,T7,T11
1	1	-	-	0	-	-	-	-	-	-	Covered	T5,T7,T11
1	1	-	-	-	1	-	-	-	-	-	Covered	T5,T7,T11
1	1	-	-	-	0	-	-	-	-	-	Covered	T5,T7,T11
1	0	-	-	-	-	1	1	-	-	-	Covered	T1,T2,T6
1	0	-	-	-	-	1	0	-	-	-	Covered	T1,T2,T4
1	0	-	-	-	-	1	-	1	-	-	Covered	T1,T2,T6
1	0	-	-	-	-	1	-	0	-	-	Covered	T1,T2,T4
1	0	-	-	-	-	1	-	-	1	-	Covered	T1,T2,T4
1	0	-	-	-	-	1	-	-	0	-	Covered	T1,T2,T4
1	0	-	-	-	-	1	-	-	-	1	Covered	T2,T4,T6
1	0	-	-	-	-	1	-	-	-	0	Covered	T1,T2,T4
1	0	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

466            if (!rst_ni) begin
               -1-  
467              trans_success_q           <= 1'b0;
                 ==>
468              trans_cnt_oflw_error_q    <= 1'b0;
469              trans_invalid_error_q     <= 1'b0;
470              token_invalid_error_q     <= 1'b0;
471              flash_rma_error_q         <= 1'b0;
472              fatal_prog_error_q        <= 1'b0;
473              fatal_state_error_q       <= 1'b0;
474              sw_claim_transition_if_q  <= MuBi8False;
475              tap_claim_transition_if_q <= MuBi8False;
476              transition_token_q        <= '0;
477              transition_target_q       <= {DecLcStateNumRep{DecLcStRaw}};
478              otp_part_error_q          <= 1'b0;
479              fatal_bus_integ_error_q   <= 1'b0;
480              otp_vendor_test_ctrl_q    <= '0;
481              use_ext_clock_q           <= 1'b0;
482            end else begin
483              // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
484              // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
485              // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
486              // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
487              // ---------------------------------------------------------------
488              // In case of a volatile RAW unlock, this bit has to be cleared when the volatile
489              // unlock is followed by a real transition.
490              // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
491              if (SecVolatileRawUnlockEn && transition_cmd && !volatile_raw_unlock_q) begin
                 -2-  
492                trans_success_q <= 1'b0;
                   ==>
493              end else begin
494                trans_success_q <= trans_success_d | trans_success_q;
                   ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

668            if (!rst_ni) begin
               -1-  
669              lc_done_q <= 1'b0;
                 ==>
670              lc_idle_q <= 1'b0;
671            end else begin
672              lc_done_q <= lc_done_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

525              if (!rst_ni) begin
                 -1-  
526                volatile_raw_unlock_q     <= 1'b0;
                   ==>
527              end else begin
528                volatile_raw_unlock_q     <= volatile_raw_unlock_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	28	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	28	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	61004413	57841848	0	0
DecLcCountWidthCheck_A	824	824	0	0
DecLcIdStateWidthCheck_A	824	824	0	0
DecLcStateWidthCheck_A	824	824	0	0
FpvSecCmCtrlKmacIfFsmCheck_A	59409337	0	0	0
FpvSecCmCtrlLcCntCheck_A	56257205	1	0	0
FpvSecCmCtrlLcFsmCheck_A	59562327	0	0	0
FpvSecCmCtrlLcStateCheck_A	57520453	0	0	0
FpvSecCmRegWeOnehotCheck_A	61004413	80	0	0
FpvSecCmTapRegWeOnehotCheck_A	61004413	0	0	0
LcCheckBypassEnKnown_A	61004413	57841848	0	0
LcClkBypReqKnown_A	61004413	57841848	0	0
LcCpuEnKnown_A	61004413	57841848	0	0
LcCreatorSwRwEn_A	61004413	57841848	0	0
LcDftEnKnown_A	61004413	57841848	0	0
LcEscalateEnKnown_A	61004413	57841848	0	0
LcFlashRmaReqKnown_A	61004413	57841848	0	0
LcFlashRmaSeedKnown_A	61004413	57841848	0	0
LcHwDebugEnKnown_A	61004413	57841848	0	0
LcIsoSwRwEn_A	61004413	57841848	0	0
LcIsoSwWrEn_A	61004413	57841848	0	0
LcKeymgrDiv_A	61004413	57841848	0	0
LcKeymgrEnKnown_A	61004413	57841848	0	0
LcNvmDebugEnKnown_A	61004413	57841848	0	0
LcOtpProgramKnown_A	61004413	57841848	0	0
LcOtpTokenKnown_A	61004413	57841848	0	0
LcOwnerSwRwEn_A	61004413	57841848	0	0
LcSeedHwRdEn_A	61004413	57841848	0	0
NumTokenWordsCheck_A	824	824	0	0
OtpTestCtrlWidth_A	824	824	0	0
PwrLcKnown_A	61004413	57841848	0	0
TlOKnown	61004413	57841848	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

DecLcCountWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824	824	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

DecLcIdStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824	824	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

DecLcStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824	824	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FpvSecCmCtrlKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59409337	0	0	0

FpvSecCmCtrlLcCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56257205	1	0	0
T110	262989	1	0	0
T111	10447	0	0	0
T112	8178	0	0	0
T113	5680	0	0	0
T114	14650	0	0	0
T115	24513	0	0	0
T116	93635	0	0	0
T117	34691	0	0	0
T118	44148	0	0	0
T119	29574	0	0	0

FpvSecCmCtrlLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59562327	0	0	0

FpvSecCmCtrlLcStateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57520453	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	80	0	0
T8	104016	0	0	0
T23	63838	0	0	0
T33	20918	0	0	0
T34	30208	0	0	0
T48	33770	0	0	0
T52	179885	0	0	0
T69	20434	20	0	0
T70	0	20	0	0
T71	0	20	0	0
T99	10157	0	0	0
T120	0	10	0	0
T121	0	10	0	0
T122	10864	0	0	0
T123	6529	0	0	0

FpvSecCmTapRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	0	0	0

LcCheckBypassEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcClkBypReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcCpuEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcCreatorSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcDftEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcEscalateEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcFlashRmaReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcFlashRmaSeedKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcHwDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcIsoSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcIsoSwWrEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcKeymgrDiv_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcKeymgrEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcNvmDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcOtpProgramKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcOtpTokenKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcOwnerSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

LcSeedHwRdEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

NumTokenWordsCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824	824	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpTestCtrlWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824	824	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

PwrLcKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0

TlOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	61004413	57841848	0	0
T1	821	759	0	0
T2	1896	1663	0	0
T3	939	865	0	0
T4	3067	2752	0	0
T5	17537	17195	0	0
T6	7233	7148	0	0
T7	50526	49405	0	0
T11	18445	18381	0	0
T12	13618	12428	0	0
T13	36722	30121	0	0