Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	774471	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

962922

1

T1

13

T2

243

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1447802	1			T1	43		T2	298		T3	2
values[0x0]	144416	1			T1	9		T2	57		T12	10
values[0x1]	145175	1			T1	7		T2	63		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	612661	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1124732

1

T1

30

T2

284

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8084	1			T5	1		T36	1		T41	33
valid_sources[0x01]	7510	1			T2	8		T16	1		T36	1
valid_sources[0x02]	20601	1			T2	11		T5	2		T15	1
valid_sources[0x03]	5574	1			T16	1		T41	33		T42	1
valid_sources[0x04]	5918	1			T5	1		T15	2		T16	1
valid_sources[0x05]	5427	1			T1	4		T8	2		T15	1
valid_sources[0x06]	5577	1			T8	3		T30	1		T36	3
valid_sources[0x07]	5676	1			T2	5		T16	1		T30	1
valid_sources[0x08]	5624	1			T6	2		T5	1		T8	2
valid_sources[0x09]	7003	1			T2	2		T12	2		T6	2
valid_sources[0x0a]	5619	1			T8	4		T15	3		T16	3
valid_sources[0x0b]	5793	1			T6	2		T8	1		T15	1
valid_sources[0x0c]	7747	1			T5	2		T15	1		T17	17
valid_sources[0x0d]	5618	1			T6	1		T16	1		T41	44
valid_sources[0x0e]	5695	1			T8	1		T15	1		T16	1
valid_sources[0x0f]	5509	1			T2	1		T5	2		T15	2
valid_sources[0x10]	5959	1			T15	1		T16	4		T41	29
valid_sources[0x11]	5669	1			T15	2		T16	4		T41	25
valid_sources[0x12]	5834	1			T6	1		T15	1		T16	2
valid_sources[0x13]	5742	1			T6	1		T8	7		T15	2
valid_sources[0x14]	5835	1			T22	3		T16	1		T36	2
valid_sources[0x15]	6612	1			T2	8		T5	1		T16	1
valid_sources[0x16]	5538	1			T1	1		T2	13		T6	1
valid_sources[0x17]	5883	1			T6	1		T15	2		T16	5
valid_sources[0x18]	6393	1			T7	14		T36	1		T41	20
valid_sources[0x19]	9647	1			T1	1		T2	7		T15	2
valid_sources[0x1a]	5491	1			T2	7		T5	2		T15	1
valid_sources[0x1b]	6176	1			T1	1		T16	2		T36	2
valid_sources[0x1c]	5747	1			T1	2		T6	1		T5	1
valid_sources[0x1d]	6360	1			T5	2		T36	2		T41	26
valid_sources[0x1e]	5676	1			T1	6		T15	1		T16	2
valid_sources[0x1f]	5559	1			T16	2		T41	28		T42	4
valid_sources[0x20]	5814	1			T5	1		T15	1		T16	1
valid_sources[0x21]	5471	1			T1	1		T5	1		T16	4
valid_sources[0x22]	6535	1			T7	2		T8	3		T15	1
valid_sources[0x23]	8225	1			T2	3		T15	3		T16	10
valid_sources[0x24]	6533	1			T6	1		T5	1		T15	1
valid_sources[0x25]	5661	1			T16	2		T30	1		T41	39
valid_sources[0x26]	6251	1			T2	6		T5	3		T15	2
valid_sources[0x27]	7384	1			T1	3		T15	2		T16	8
valid_sources[0x28]	5898	1			T15	3		T16	7		T36	2
valid_sources[0x29]	6023	1			T2	2		T8	1		T16	1
valid_sources[0x2a]	7109	1			T2	2		T15	1		T16	1
valid_sources[0x2b]	5472	1			T6	1		T15	2		T16	3
valid_sources[0x2c]	5201	1			T2	4		T5	1		T16	2
valid_sources[0x2d]	5756	1			T2	13		T5	1		T15	2
valid_sources[0x2e]	5699	1			T15	1		T16	5		T36	1
valid_sources[0x2f]	5573	1			T5	2		T15	1		T30	1
valid_sources[0x30]	5529	1			T5	1		T15	6		T16	2
valid_sources[0x31]	5881	1			T5	1		T36	2		T41	29
valid_sources[0x32]	8438	1			T2	32		T15	1		T16	3
valid_sources[0x33]	5638	1			T8	2		T30	1		T36	1
valid_sources[0x34]	6115	1			T15	1		T16	6		T30	1
valid_sources[0x35]	14237	1			T6	1		T30	2		T41	40
valid_sources[0x36]	8277	1			T2	3		T5	1		T8	4
valid_sources[0x37]	28718	1			T2	2		T15	1		T16	6
valid_sources[0x38]	6189	1			T30	1		T41	39		T33	9
valid_sources[0x39]	7930	1			T7	11		T16	3		T36	1
valid_sources[0x3a]	6028	1			T5	2		T16	6		T36	2
valid_sources[0x3b]	6812	1			T1	1		T5	2		T16	2
valid_sources[0x3c]	5693	1			T15	1		T16	4		T30	1
valid_sources[0x3d]	6270	1			T5	1		T8	4		T16	1
valid_sources[0x3e]	5928	1			T15	1		T41	29		T42	10
valid_sources[0x3f]	5670	1			T2	66		T16	2		T36	4
valid_sources[0x40]	5755	1			T2	4		T7	4		T8	2
valid_sources[0x41]	6128	1			T6	2		T15	3		T36	2
valid_sources[0x42]	5858	1			T15	2		T16	2		T41	26
valid_sources[0x43]	6009	1			T15	2		T16	1		T93	2
valid_sources[0x44]	7362	1			T2	2		T15	1		T16	2
valid_sources[0x45]	5819	1			T15	2		T16	2		T41	21
valid_sources[0x46]	5904	1			T2	10		T6	1		T5	2
valid_sources[0x47]	5998	1			T2	2		T5	1		T7	6
valid_sources[0x48]	6881	1			T5	1		T16	2		T41	37
valid_sources[0x49]	5860	1			T6	1		T16	2		T41	22
valid_sources[0x4a]	6595	1			T5	1		T15	1		T16	3
valid_sources[0x4b]	5882	1			T1	2		T8	3		T15	4
valid_sources[0x4c]	5517	1			T6	1		T15	2		T16	1
valid_sources[0x4d]	5789	1			T15	1		T93	1		T36	1
valid_sources[0x4e]	8050	1			T5	1		T15	1		T16	1
valid_sources[0x4f]	5925	1			T5	1		T15	3		T16	2
valid_sources[0x50]	6191	1			T1	2		T2	1		T16	2
valid_sources[0x51]	8481	1			T5	3		T8	5		T36	1
valid_sources[0x52]	6867	1			T2	1		T12	2		T36	1
valid_sources[0x53]	5893	1			T6	1		T16	3		T17	17
valid_sources[0x54]	6109	1			T15	1		T16	2		T41	17
valid_sources[0x55]	5760	1			T6	1		T15	2		T16	1
valid_sources[0x56]	7616	1			T5	2		T36	1		T41	36
valid_sources[0x57]	6025	1			T41	24		T33	2		T39	1
valid_sources[0x58]	5572	1			T12	1		T5	1		T15	2
valid_sources[0x59]	5290	1			T6	1		T5	1		T15	1
valid_sources[0x5a]	5472	1			T16	3		T36	2		T41	45
valid_sources[0x5b]	6313	1			T6	1		T5	1		T15	1
valid_sources[0x5c]	6008	1			T17	17		T41	20		T42	20
valid_sources[0x5d]	5497	1			T1	3		T5	1		T16	4
valid_sources[0x5e]	6417	1			T2	11		T15	3		T16	1
valid_sources[0x5f]	6605	1			T15	1		T16	3		T41	29
valid_sources[0x60]	5903	1			T15	2		T36	1		T41	35
valid_sources[0x61]	5890	1			T1	1		T2	5		T6	1
valid_sources[0x62]	5441	1			T2	8		T12	1		T6	1
valid_sources[0x63]	10651	1			T5	1		T15	1		T36	3
valid_sources[0x64]	31136	1			T15	2		T16	1		T41	23
valid_sources[0x65]	5604	1			T2	14		T12	3		T5	2
valid_sources[0x66]	12171	1			T5	1		T15	1		T16	1
valid_sources[0x67]	5655	1			T5	1		T15	1		T30	1
valid_sources[0x68]	7287	1			T6	1		T15	3		T16	7
valid_sources[0x69]	7080	1			T8	1		T15	3		T16	1
valid_sources[0x6a]	5968	1			T5	4		T15	1		T36	3
valid_sources[0x6b]	5894	1			T1	1		T8	1		T15	3
valid_sources[0x6c]	6400	1			T6	1		T5	1		T15	2
valid_sources[0x6d]	6552	1			T12	1		T36	2		T41	17
valid_sources[0x6e]	5554	1			T1	1		T16	1		T36	1
valid_sources[0x6f]	6341	1			T1	4		T6	1		T5	1
valid_sources[0x70]	6764	1			T15	1		T36	2		T41	19
valid_sources[0x71]	15465	1			T2	8		T7	12		T15	1
valid_sources[0x72]	5808	1			T2	3		T16	2		T30	1
valid_sources[0x73]	6493	1			T8	3		T36	3		T41	44
valid_sources[0x74]	11748	1			T1	1		T2	7		T5	1
valid_sources[0x75]	5678	1			T5	3		T15	2		T93	5
valid_sources[0x76]	6585	1			T2	4		T5	2		T8	1
valid_sources[0x77]	8300	1			T15	1		T16	2		T41	34
valid_sources[0x78]	6111	1			T2	1		T15	1		T16	4
valid_sources[0x79]	5664	1			T1	1		T7	4		T16	5
valid_sources[0x7a]	10633	1			T15	2		T16	2		T36	2
valid_sources[0x7b]	6163	1			T6	1		T15	3		T16	6
valid_sources[0x7c]	5472	1			T7	13		T16	2		T36	1
valid_sources[0x7d]	5479	1			T8	1		T16	1		T30	1
valid_sources[0x7e]	5761	1			T6	1		T5	1		T15	1
valid_sources[0x7f]	6001	1			T7	6		T15	1		T41	34
valid_sources[0x80]	5469	1			T5	6		T16	4		T36	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

713181

1

T1

1

T2

141

T3

2

values[0x0]

all_enables

biggest_size

125272

1

T1

7

T2

52

T12

8

values[0x1]

all_enables

biggest_size

124469

1

T1

5

T2

50

T3

1