Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2278502	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2523251

1

T1

12

T3

142

T4

67

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4414023	1			T1	5		T2	2		T3	142
values[0x0]	193747	1			T1	7		T2	1		T3	52
values[0x1]	193983	1			T1	8		T3	49		T4	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1812223	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2989530

1

T1

15

T3

162

T4

77

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14538	1			T14	1		T7	2		T16	9
valid_sources[0x01]	14239	1			T3	1		T7	4		T16	10
valid_sources[0x02]	16756	1			T12	23		T14	1		T7	8
valid_sources[0x03]	14251	1			T12	3		T14	1		T16	15
valid_sources[0x04]	13699	1			T14	1		T7	2		T16	14
valid_sources[0x05]	14110	1			T16	12		T17	1		T31	27
valid_sources[0x06]	14125	1			T16	14		T17	1		T31	20
valid_sources[0x07]	44364	1			T3	6		T16	12		T31	27
valid_sources[0x08]	18370	1			T12	78		T7	3		T16	18
valid_sources[0x09]	14575	1			T3	2		T12	12		T16	11
valid_sources[0x0a]	13929	1			T3	3		T12	10		T16	14
valid_sources[0x0b]	14225	1			T16	10		T17	3		T31	23
valid_sources[0x0c]	14810	1			T3	1		T7	1		T16	17
valid_sources[0x0d]	13910	1			T3	2		T12	8		T7	5
valid_sources[0x0e]	16231	1			T7	2		T16	17		T8	3
valid_sources[0x0f]	14409	1			T12	8		T16	6		T8	5
valid_sources[0x10]	13730	1			T12	2		T14	1		T16	18
valid_sources[0x11]	15817	1			T3	3		T7	1		T16	14
valid_sources[0x12]	17416	1			T3	2		T12	52		T16	21
valid_sources[0x13]	15344	1			T12	24		T14	2		T7	5
valid_sources[0x14]	16469	1			T7	2		T16	11		T17	3
valid_sources[0x15]	14516	1			T2	1		T16	18		T8	4
valid_sources[0x16]	14592	1			T16	11		T17	4		T31	28
valid_sources[0x17]	15103	1			T3	3		T7	2		T16	12
valid_sources[0x18]	14186	1			T3	1		T16	21		T17	6
valid_sources[0x19]	13938	1			T12	69		T16	14		T31	21
valid_sources[0x1a]	14091	1			T2	1		T12	42		T7	1
valid_sources[0x1b]	87969	1			T14	1		T16	11		T31	23
valid_sources[0x1c]	79208	1			T12	68		T16	18		T17	3
valid_sources[0x1d]	14284	1			T12	9		T14	1		T7	2
valid_sources[0x1e]	14424	1			T16	7		T8	4		T17	1
valid_sources[0x1f]	16163	1			T14	1		T16	18		T31	26
valid_sources[0x20]	37118	1			T1	1		T12	15		T16	13
valid_sources[0x21]	16754	1			T12	3		T13	1		T16	12
valid_sources[0x22]	15612	1			T3	2		T16	6		T8	2
valid_sources[0x23]	17830	1			T3	2		T12	16		T14	1
valid_sources[0x24]	15913	1			T3	2		T16	10		T17	5
valid_sources[0x25]	14214	1			T7	2		T16	14		T8	10
valid_sources[0x26]	15007	1			T3	1		T12	23		T16	13
valid_sources[0x27]	13769	1			T3	1		T7	1		T16	17
valid_sources[0x28]	14655	1			T3	2		T16	17		T17	1
valid_sources[0x29]	14229	1			T3	3		T7	6		T16	24
valid_sources[0x2a]	65215	1			T3	4		T7	2		T16	7
valid_sources[0x2b]	43899	1			T3	1		T7	4		T16	19
valid_sources[0x2c]	14545	1			T12	4		T7	2		T16	22
valid_sources[0x2d]	15523	1			T7	2		T16	9		T17	1
valid_sources[0x2e]	18715	1			T1	1		T16	13		T8	1
valid_sources[0x2f]	14439	1			T12	24		T7	4		T16	16
valid_sources[0x30]	15354	1			T12	24		T16	12		T17	1
valid_sources[0x31]	103171	1			T7	1		T16	20		T17	1
valid_sources[0x32]	14189	1			T3	1		T12	14		T16	14
valid_sources[0x33]	14796	1			T3	4		T14	1		T16	11
valid_sources[0x34]	14234	1			T3	1		T7	3		T16	9
valid_sources[0x35]	16082	1			T7	1		T16	14		T31	35
valid_sources[0x36]	14293	1			T3	5		T12	4		T16	17
valid_sources[0x37]	49064	1			T3	3		T7	1		T16	10
valid_sources[0x38]	15839	1			T3	3		T12	5		T14	1
valid_sources[0x39]	13759	1			T14	1		T16	10		T8	7
valid_sources[0x3a]	37757	1			T1	1		T3	3		T16	11
valid_sources[0x3b]	14798	1			T3	1		T7	1		T16	18
valid_sources[0x3c]	14517	1			T14	1		T16	8		T8	1
valid_sources[0x3d]	14731	1			T3	5		T7	1		T16	5
valid_sources[0x3e]	14434	1			T3	6		T12	4		T16	6
valid_sources[0x3f]	15064	1			T16	8		T17	2		T31	25
valid_sources[0x40]	15386	1			T7	2		T16	11		T17	2
valid_sources[0x41]	13815	1			T3	1		T16	21		T17	1
valid_sources[0x42]	13907	1			T16	12		T8	1		T17	1
valid_sources[0x43]	14325	1			T3	2		T7	4		T16	9
valid_sources[0x44]	14318	1			T3	7		T7	2		T16	14
valid_sources[0x45]	14243	1			T16	10		T17	4		T31	28
valid_sources[0x46]	16001	1			T13	1		T7	3		T16	13
valid_sources[0x47]	14140	1			T12	6		T7	4		T16	17
valid_sources[0x48]	15051	1			T3	3		T7	3		T16	19
valid_sources[0x49]	14241	1			T3	3		T16	15		T8	3
valid_sources[0x4a]	14738	1			T7	2		T16	11		T17	5
valid_sources[0x4b]	15631	1			T14	1		T16	12		T17	3
valid_sources[0x4c]	15596	1			T7	2		T16	21		T8	3
valid_sources[0x4d]	13885	1			T3	5		T7	1		T16	10
valid_sources[0x4e]	42371	1			T5	326		T12	7		T16	15
valid_sources[0x4f]	14312	1			T14	1		T7	3		T16	13
valid_sources[0x50]	27450	1			T7	2		T16	11		T8	11
valid_sources[0x51]	15723	1			T7	6		T16	11		T31	34
valid_sources[0x52]	57841	1			T3	1		T16	13		T8	5
valid_sources[0x53]	15980	1			T3	1		T13	1		T16	9
valid_sources[0x54]	13997	1			T12	10		T16	10		T8	21
valid_sources[0x55]	14701	1			T12	44		T7	1		T16	16
valid_sources[0x56]	18632	1			T13	1		T16	14		T17	3
valid_sources[0x57]	14901	1			T7	1		T16	13		T17	1
valid_sources[0x58]	14758	1			T13	1		T14	1		T7	3
valid_sources[0x59]	41461	1			T7	1		T16	16		T31	15
valid_sources[0x5a]	14677	1			T3	3		T12	8		T16	13
valid_sources[0x5b]	17354	1			T7	3		T16	14		T17	2
valid_sources[0x5c]	45695	1			T13	3		T16	15		T17	1
valid_sources[0x5d]	13899	1			T3	2		T12	74		T7	2
valid_sources[0x5e]	14049	1			T7	1		T16	12		T8	9
valid_sources[0x5f]	15260	1			T3	1		T15	707		T16	10
valid_sources[0x60]	14326	1			T3	2		T16	12		T8	1
valid_sources[0x61]	13453	1			T3	1		T12	22		T7	10
valid_sources[0x62]	15613	1			T3	1		T4	128		T16	13
valid_sources[0x63]	15335	1			T1	1		T13	2		T16	18
valid_sources[0x64]	15052	1			T3	4		T12	14		T13	1
valid_sources[0x65]	14670	1			T3	2		T13	2		T16	18
valid_sources[0x66]	13451	1			T12	5		T16	15		T17	3
valid_sources[0x67]	16418	1			T3	1		T16	11		T8	5
valid_sources[0x68]	14786	1			T12	1		T7	1		T16	15
valid_sources[0x69]	14203	1			T16	10		T17	2		T31	20
valid_sources[0x6a]	14205	1			T12	13		T14	1		T7	4
valid_sources[0x6b]	14579	1			T3	1		T14	1		T7	2
valid_sources[0x6c]	14481	1			T16	13		T17	2		T31	29
valid_sources[0x6d]	15744	1			T3	2		T16	8		T17	1
valid_sources[0x6e]	14026	1			T3	3		T16	15		T8	2
valid_sources[0x6f]	14452	1			T16	15		T31	15		T33	7
valid_sources[0x70]	18593	1			T3	1		T16	19		T17	3
valid_sources[0x71]	14264	1			T7	1		T16	11		T8	5
valid_sources[0x72]	19396	1			T3	3		T7	5		T16	7
valid_sources[0x73]	14501	1			T7	2		T16	10		T8	7
valid_sources[0x74]	14278	1			T3	1		T14	1		T7	3
valid_sources[0x75]	13822	1			T3	1		T12	5		T7	6
valid_sources[0x76]	123238	1			T7	1		T16	11		T17	1
valid_sources[0x77]	14331	1			T3	2		T16	10		T8	1
valid_sources[0x78]	13971	1			T3	1		T7	2		T16	17
valid_sources[0x79]	13977	1			T14	1		T7	2		T16	14
valid_sources[0x7a]	13835	1			T7	1		T16	13		T17	2
valid_sources[0x7b]	14307	1			T3	1		T13	1		T16	16
valid_sources[0x7c]	16220	1			T3	5		T16	16		T8	3
valid_sources[0x7d]	14170	1			T3	2		T12	18		T13	1
valid_sources[0x7e]	14619	1			T14	1		T7	1		T16	11
valid_sources[0x7f]	14666	1			T3	2		T12	33		T16	6
valid_sources[0x80]	14370	1			T12	4		T7	3		T16	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2188611

1

T1

1

T3

57

T4

47

values[0x0]

all_enables

biggest_size

168110

1

T1

7

T3

42

T4

11

values[0x1]

all_enables

biggest_size

166530

1

T1

4

T3

43

T4

9