Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	134635097	14285	0	0
claim_transition_if_regwen_rd_A	134635097	1462	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134635097	14285	0	0
T27	8744	0	0	0
T60	0	2	0	0
T72	29827	0	0	0
T82	0	1	0	0
T98	467822	2	0	0
T107	0	9	0	0
T111	0	5	0	0
T112	0	1	0	0
T148	0	1	0	0
T150	0	7	0	0
T151	0	8	0	0
T152	0	3	0	0
T153	104069	0	0	0
T154	36487	0	0	0
T155	4897	0	0	0
T156	442648	0	0	0
T157	1391	0	0	0
T158	19104	0	0	0
T159	387243	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134635097	1462	0	0
T60	0	9	0	0
T82	177670	2	0	0
T106	0	3	0	0
T108	0	37	0	0
T112	0	3	0	0
T116	0	10	0	0
T119	0	2	0	0
T120	0	134	0	0
T160	0	6	0	0
T161	0	3	0	0
T162	368032	0	0	0
T163	544066	0	0	0
T164	40230	0	0	0
T165	23796	0	0	0
T166	7909	0	0	0
T167	9527	0	0	0
T168	31150	0	0	0
T169	1560	0	0	0
T170	25731	0	0	0