Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.64 100.00 55.56 75.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic 75.00 75.00
tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic 75.00 75.00
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic 85.19 100.00 55.56 100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic 85.19 100.00 55.56 100.00


Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
75.00 75.00 gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
75.00 75.00 u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00


16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 
Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Toggle Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk0_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
clk1_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
sel_i No No No INPUT
clk_o Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
selKnown0 101541684 101540030 0 0
selKnown1 132477908 132476254 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 101541684 101540030 0 0
T3 12 11 0 0
T4 4 3 0 0
T5 12 11 0 0
T6 51397 51395 0 0
T7 53529 53527 0 0
T8 76331 76330 0 0
T9 0 22161 0 0
T10 0 19391 0 0
T12 55 54 0 0
T13 2 0 0 0
T14 2 0 0 0
T15 21 19 0 0
T16 79 77 0 0
T17 1 7 0 0
T18 34857 34866 0 0
T19 0 133917 0 0
T20 0 57346 0 0
T21 0 35315 0 0
T22 0 17646 0 0
T23 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 132477908 132476254 0 0
T1 835 834 0 0
T2 1268 1267 0 0
T3 4489 4488 0 0
T4 3157 3156 0 0
T5 7462 7461 0 0
T6 33160 33159 0 0
T7 6 5 0 0
T8 1 0 0 0
T10 0 1 0 0
T11 0 2 0 0
T12 22279 22278 0 0
T13 1285 1284 0 0
T14 1267 1266 0 0
T15 4576 4575 0 0
T16 1 0 0 0
T17 1 0 0 0
T18 1 0 0 0
T19 1 0 0 0
T23 1 0 0 0
T24 0 2 0 0
T25 0 1 0 0
T26 0 3 0 0
T27 0 1 0 0
T28 0 1 0 0
T29 0 2 0 0
T30 0 3 0 0
T31 1 0 0 0
T32 1 0 0 0
T33 1 0 0 0

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk0_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
clk1_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
sel_i No No No INPUT
clk_o Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk0_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
clk1_i Yes Yes T7,T8,T9 Yes T7,T10,T11 INPUT
sel_i No No No INPUT
clk_o Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00


16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT6,T7,T8
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
selKnown0 101474818 101473991 0 0
selKnown1 132476979 132476152 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 101474818 101473991 0 0
T6 51383 51382 0 0
T7 53528 53527 0 0
T8 76331 76330 0 0
T9 0 22161 0 0
T10 0 19391 0 0
T13 1 0 0 0
T14 1 0 0 0
T15 1 0 0 0
T16 1 0 0 0
T17 1 0 0 0
T18 34857 34856 0 0
T19 0 133910 0 0
T20 0 57346 0 0
T21 0 35315 0 0
T22 0 17646 0 0
T23 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 132476979 132476152 0 0
T1 835 834 0 0
T2 1268 1267 0 0
T3 4489 4488 0 0
T4 3157 3156 0 0
T5 7462 7461 0 0
T6 33160 33159 0 0
T12 22279 22278 0 0
T13 1285 1284 0 0
T14 1267 1266 0 0
T15 4576 4575 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00


16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
selKnown0 66866 66039 0 0
selKnown1 929 102 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 66866 66039 0 0
T3 12 11 0 0
T4 4 3 0 0
T5 12 11 0 0
T6 14 13 0 0
T7 1 0 0 0
T12 55 54 0 0
T13 1 0 0 0
T14 1 0 0 0
T15 20 19 0 0
T16 78 77 0 0
T17 0 7 0 0
T18 0 10 0 0
T19 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 929 102 0 0
T7 6 5 0 0
T8 1 0 0 0
T10 0 1 0 0
T11 0 2 0 0
T16 1 0 0 0
T17 1 0 0 0
T18 1 0 0 0
T19 1 0 0 0
T23 1 0 0 0
T24 0 2 0 0
T25 0 1 0 0
T26 0 3 0 0
T27 0 1 0 0
T28 0 1 0 0
T29 0 2 0 0
T30 0 3 0 0
T31 1 0 0 0
T32 1 0 0 0
T33 1 0 0 0