Unified Coverage Report :: Module :: prim_mubi4_dec

Module : prim_mubi4_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_mubi4_dec	0.00	0.00

---

Module Instance : tb.dut.u_prim_mubi4_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bits[0].u_prim_buf	0.00	0.00
gen_bits[1].u_prim_buf	0.00	0.00
gen_bits[2].u_prim_buf	0.00	0.00
gen_bits[3].u_prim_buf	0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_mubi4_dec

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	25	1	0	0.00
CONT_ASSIGN	37	1	0	0.00

24                      logic [MuBi4Width-1:0] mubi, mubi_out;
25         0/1     ==>  assign mubi = MuBi4Width'(mubi_i);
26                      
27                      // The buffer cells have a don't touch constraint on them
28                      // such that synthesis tools won't collapse them
29                      for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
30                        prim_buf u_prim_buf (
31                          .in_i  ( mubi[k]     ),
32                          .out_o ( mubi_out[k] )
33                        );
34                      end
35                      
36                      if (TestTrue && TestStrict) begin : gen_test_true_strict
37         0/1     ==>    assign mubi_dec_o = mubi4_test_true_strict(mubi4_t'(mubi_out));