OTBN Simulation Results

Wednesday January 10 2024 20:03:22 UTC

GitHub Revision: `cf38c1d296`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 55803132295021657086212552594002090640066687299415498461130788370399872772386

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	8.000s	23.695us	1	1	100.00
V1	single_binary	otbn_single	40.000s	155.001us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	57.586us	5	5	100.00
V1	csr_rw	otbn_csr_rw	10.000s	121.210us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	362.579us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	15.329us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	38.176us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	10.000s	121.210us	20	20	100.00
		otbn_csr_aliasing	5.000s	15.329us	5	5	100.00
V1	mem_walk	otbn_mem_walk	36.000s	3.346ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	16.000s	919.545us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.117m	292.106us	10	10	100.00
V2	multi_error	otbn_multi_err	53.000s	168.816us	1	1	100.00
V2	back_to_back	otbn_multi	22.517m	5.926ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.733m	804.229us	10	10	100.00
V2	lc_escalation	otbn_escalate	22.000s	90.636us	50	60	83.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	25.810us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	36.000s	125.913us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	17.573us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	32.491us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	62.319us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	62.319us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	57.586us	5	5	100.00
		otbn_csr_rw	10.000s	121.210us	20	20	100.00
		otbn_csr_aliasing	5.000s	15.329us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	54.200us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	57.586us	5	5	100.00
		otbn_csr_rw	10.000s	121.210us	20	20	100.00
		otbn_csr_aliasing	5.000s	15.329us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	54.200us	20	20	100.00
V2		TOTAL			235	246	95.53
V2S	mem_integrity	otbn_imem_err	15.000s	73.497us	10	10	100.00
		otbn_dmem_err	19.000s	37.622us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	72.431us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	58.303us	5	5	100.00
		otbn_mac_bignum_acc_err	14.000s	57.097us	5	5	100.00
		otbn_urnd_err	8.000s	71.152us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	29.940us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	33.392us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	8.783m	3.311ms	4	5	80.00
		otbn_tl_intg_err	35.000s	197.237us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.133m	479.653us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.783m	3.311ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	8.783m	3.311ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	8.000s	23.695us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	19.000s	37.622us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	15.000s	73.497us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	35.000s	197.237us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	22.000s	90.636us	50	60	83.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	15.000s	73.497us	10	10	100.00
		otbn_dmem_err	19.000s	37.622us	15	15	100.00
		otbn_zero_state_err_urnd	7.000s	25.810us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	29.940us	5	5	100.00
		otbn_sec_cm	8.783m	3.311ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.783m	3.311ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	40.000s	155.001us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	15.000s	73.497us	10	10	100.00
		otbn_dmem_err	19.000s	37.622us	15	15	100.00
		otbn_zero_state_err_urnd	7.000s	25.810us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	29.940us	5	5	100.00
		otbn_sec_cm	8.783m	3.311ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.783m	3.311ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	22.000s	90.636us	50	60	83.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	15.000s	73.497us	10	10	100.00
		otbn_dmem_err	19.000s	37.622us	15	15	100.00
		otbn_zero_state_err_urnd	7.000s	25.810us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	29.940us	5	5	100.00
		otbn_sec_cm	8.783m	3.311ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.783m	3.311ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	40.000s	155.001us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	32.900us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	12.849us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.067m	580.114us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.067m	580.114us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	16.000s	65.058us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.783m	3.311ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.783m	3.311ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	100.323us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.783m	3.311ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.783m	3.311ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	41.000s	10.021ms	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	41.000s	10.021ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	14.000s	242.961us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	40.000s	155.001us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	40.000s	155.001us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	40.000s	155.001us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	22.517m	5.926ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	40.000s	155.001us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	40.000s	155.001us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	18.166us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	40.000s	155.001us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.783m	3.311ms	4	5	80.00
V2S		TOTAL			150	153	98.04
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	6.300m	6.321ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			559	575	97.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	19	19	16	84.21
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.81	99.55	94.59	99.64	91.12	93.61	97.44	91.52	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 4 failures:

Test otbn_escalate has 4 failures.

11.otbn_escalate.31753189809204803106686145450575217020531386303467291429116500702283567244368
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 12531692 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  12531692 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  12531692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.otbn_escalate.106740405289498110852308993350920688469082715571950131502973488453096213876346
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/24.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4533621 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   4533621 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   4533621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_zero_state_err_urnd has 1 failures.

4.otbn_zero_state_err_urnd.55068524062888089392184690747540845542241863460259634032487159506369572851130
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17079931 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  17079931 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  17079931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

40.otbn_escalate.81429365593307961483843103806320696207396087042973606118970949040753278977084
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/40.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 27851399 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  27851399 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  27851399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

44.otbn_escalate.103240445236918310012301436117511751125677992222275848220755699208151523808663
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/44.otbn_escalate/latest/run.log

  UVM_FATAL @   6120230 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   6120230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

52.otbn_escalate.85864628202713277035263640378276505009411669537391224716095568160597019365263
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/52.otbn_escalate/latest/run.log

  UVM_FATAL @  63669503 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  63669503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 0.otbn_ctrl_redun.36183806407109857722536006110857804961209062400213701510275477828413342146465
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log
```
  UVM_FATAL @  32899899 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  32899899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 2.otbn_stack_addr_integ_chk.87760488266143817417960971603073164674302505313701646269795624159281761219167
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10020999483 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10020999483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1298): Assertion SecWipeNonZeroMod_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

2.otbn_sec_cm.30888299451143254557940317900912679780104237351851178945640911996540080493441
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1298): (time 1559522 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1305): (time 1559522 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1259): (time 1559522 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1259): (time 1559522 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1259): (time 1559522 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.56284780047059814092992558050887787298727580218152674699094778645299719062271
    Line 322, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @   5390827 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @   5390827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 9.otbn_escalate.8370306597454265872743342959564395223234466813964232593416245078753253937566
    Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log
```
  UVM_FATAL @   4036264 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   4036264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.72942379964852893329448495721950668348362241116764261701905888248627074684839
    Line 338, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 243556343 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 243556343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 48.otbn_escalate.9686948696265492373790043688878136315860261426789466350355907134708139414298
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/48.otbn_escalate/latest/run.log
```
  UVM_FATAL @  21671105 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  21671105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 1 failures:

Test otbn_escalate has 1 failures.

55.otbn_escalate.103441961310747465775648678521996033612528772889720697467614988977952527988784
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/55.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 42759811 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 42759811 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  42759811 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  42759811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---