OTBN Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: `5f48fbc0e7`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	9.000s	61.295us	1	1	100.00
V1	single_binary	otbn_single	2.283m	404.126us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	24.262us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	39.428us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	235.532us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	18.320us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	30.908us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	39.428us	20	20	100.00
		otbn_csr_aliasing	5.000s	18.320us	5	5	100.00
V1	mem_walk	otbn_mem_walk	20.000s	2.289ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	18.000s	279.006us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	38.000s	234.721us	10	10	100.00
V2	multi_error	otbn_multi_err	1.017m	383.897us	1	1	100.00
V2	back_to_back	otbn_multi	2.867m	1.039ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.383m	824.304us	10	10	100.00
V2	lc_escalation	otbn_escalate	1.033m	244.031us	50	60	83.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	54.195us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	24.000s	62.898us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	26.211us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	21.584us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	796.376us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	796.376us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	24.262us	5	5	100.00
		otbn_csr_rw	6.000s	39.428us	20	20	100.00
		otbn_csr_aliasing	5.000s	18.320us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	20.934us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	24.262us	5	5	100.00
		otbn_csr_rw	6.000s	39.428us	20	20	100.00
		otbn_csr_aliasing	5.000s	18.320us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	20.934us	20	20	100.00
V2		TOTAL			236	246	95.93
V2S	mem_integrity	otbn_imem_err	10.000s	21.501us	10	10	100.00
		otbn_dmem_err	13.000s	43.255us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	36.000s	576.566us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	56.083us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	37.098us	5	5	100.00
		otbn_urnd_err	8.000s	45.223us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	18.409us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	129.881us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	2.767m	1.318ms	5	5	100.00
		otbn_tl_intg_err	38.000s	904.244us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	30.000s	161.482us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	2.767m	1.318ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	2.767m	1.318ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	9.000s	61.295us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	43.255us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	21.501us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	38.000s	904.244us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.033m	244.031us	50	60	83.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	21.501us	10	10	100.00
		otbn_dmem_err	13.000s	43.255us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	54.195us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	18.409us	5	5	100.00
		otbn_sec_cm	2.767m	1.318ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	2.767m	1.318ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.283m	404.126us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	21.501us	10	10	100.00
		otbn_dmem_err	13.000s	43.255us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	54.195us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	18.409us	5	5	100.00
		otbn_sec_cm	2.767m	1.318ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	2.767m	1.318ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.033m	244.031us	50	60	83.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	21.501us	10	10	100.00
		otbn_dmem_err	13.000s	43.255us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	54.195us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	18.409us	5	5	100.00
		otbn_sec_cm	2.767m	1.318ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	2.767m	1.318ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.283m	404.126us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	13.000s	27.129us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	15.000s	64.229us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	38.000s	337.347us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	38.000s	337.347us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	180.825us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	2.767m	1.318ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	2.767m	1.318ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	16.000s	114.921us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	2.767m	1.318ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	2.767m	1.318ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	2.150m	10.016ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	2.150m	10.016ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	12.000s	48.064us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.283m	404.126us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.283m	404.126us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.283m	404.126us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.867m	1.039ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.283m	404.126us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.283m	404.126us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	42.131us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.283m	404.126us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	2.767m	1.318ms	5	5	100.00
V2S		TOTAL			150	153	98.04
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	36.283m	228.931ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			558	575	97.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	19	19	17	89.47
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	99.52	94.15	99.63	90.99	93.38	97.44	91.05	99.58

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

0.otbn_stack_addr_integ_chk.10136547306688026330971176332980931358140742477358026887219439305511519582646
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 8225383 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   8225383 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   8225383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_ctrl_redun has 1 failures.

9.otbn_ctrl_redun.17654027499863616147410575794184122878541947570258692181856638491843097862774
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 24823443 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 24823443 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  24823443 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  24823443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

11.otbn_escalate.63923063812954711244870456200847160504116696788018269067449944797708834877276
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 35317860 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  35317860 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  35317860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.otbn_escalate.1005144303802298928194794294027844453655423713151807583757372679688454864878
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 51258025 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  51258025 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  51258025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:

Test otbn_escalate has 3 failures.

1.otbn_escalate.19587955004710077847569455841095051129027091011595804042003513535540810000472
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log

  UVM_FATAL @  25601996 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  25601996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_escalate.27099401672911112988780642923583102757486433960454592356449237749632566925446
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log

  UVM_FATAL @  18721771 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  18721771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 1.otbn_stress_all_with_rand_reset.4497098873442895581828765020049418496297958655685149270697621155743461644112
    Line 376, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1388007819 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1388007819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.otbn_stress_all_with_rand_reset.6109904357240876266609300384248357078750955552391527503869563465671246995885
    Line 920, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 228931473758 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 228931473758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

21.otbn_escalate.36846481866588048982808594249624718535895319533382676420243124369536050800579
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 10271819 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  10271819 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  10271819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.otbn_escalate.9498743202633163130763853788324078229994389183247220776203933627926582182819
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/39.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3464806 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   3464806 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   3464806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.46529152954258964899953614403066555082798517719208076380678755436313974015003
    Line 522, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 24643371313 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 24643371313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 1.otbn_stack_addr_integ_chk.106654956750527698810787644798094796128650512954859922720516587952272395055324
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10015932762 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10015932762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 1 failures:

Test otbn_escalate has 1 failures.

20.otbn_escalate.83895552913132837728247512183395463782314109069305726796382558680050186242817
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 34395625 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 34395625 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  34395625 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  34395625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 27.otbn_escalate.40829171140878115253707727864188508343508277241923271671121508987718348071033
    Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/27.otbn_escalate/latest/run.log
```
  UVM_FATAL @   2281912 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   2281912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```