OTP_CTRL Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: ac0bef2ce

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.870s	239.983us	1	1	100.00
V1	smoke	otp_ctrl_smoke	12.750s	2.333ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.090s	119.326us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.370s	622.316us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.050s	1.177ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.870s	2.057ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.200s	1.691ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.370s	622.316us	20	20	100.00
		otp_ctrl_csr_aliasing	5.870s	2.057ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.380s	140.603us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.520s	532.882us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	28.840s	12.917ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.690s	3.208ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	19.490s	1.499ms	10	10	100.00
		otp_ctrl_check_fail	21.490s	1.087ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	11.490s	4.756ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.289m	10.492ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	26.140s	10.507ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	34.660s	12.645ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	15.790s	4.754ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	17.370s	8.449ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.377m	22.621ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	2.836m	23.923ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	3.509m	27.012ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.960s	502.157us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.910s	202.741us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.510s	2.544ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.510s	2.544ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.090s	119.326us	5	5	100.00
		otp_ctrl_csr_rw	2.370s	622.316us	20	20	100.00
		otp_ctrl_csr_aliasing	5.870s	2.057ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	2.990s	441.328us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.090s	119.326us	5	5	100.00
		otp_ctrl_csr_rw	2.370s	622.316us	20	20	100.00
		otp_ctrl_csr_aliasing	5.870s	2.057ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	2.990s	441.328us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
		otp_ctrl_tl_intg_err	39.890s	19.001ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	39.890s	19.001ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	12.750s	2.333ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	12.750s	2.333ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	15.790s	4.754ms	200	200	100.00
		otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	15.790s	4.754ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	15.790s	4.754ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	15.790s	4.754ms	200	200	100.00
		otp_ctrl_macro_errs	1.377m	22.621ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	15.790s	4.754ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	15.790s	4.754ms	200	200	100.00
		otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	15.790s	4.754ms	200	200	100.00
		otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	15.790s	4.754ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	15.790s	4.754ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	15.790s	4.754ms	200	200	100.00
		otp_ctrl_macro_errs	1.377m	22.621ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	15.790s	4.754ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	15.790s	4.754ms	200	200	100.00
		otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.690s	3.208ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	21.490s	1.087ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.289m	10.492ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.289m	10.492ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.289m	10.492ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.289m	10.492ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.289m	10.492ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	12.750s	2.333ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.289m	10.492ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	12.750s	2.333ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.336m	143.392ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	11.490s	4.756ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	12.750s	2.333ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	12.750s	2.333ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.377m	22.621ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	15.910s	6.972ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.994h	5.330s	93	100	93.00
V3		TOTAL			94	101	93.07
		TOTAL			1336	1343	99.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.40	92.61	91.19	92.25	92.68	93.29	96.53	95.27

Failure Buckets

• Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 4 failures.

    • 23.otp_ctrl_stress_all_with_rand_reset.1279080540
      Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:7f681138-781b-40b9-9425-745d3c804eac
      

    • 26.otp_ctrl_stress_all_with_rand_reset.469093293
      Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:766ef041-bcfe-42b0-89b1-01e2213176e7
      

    • ... and 2 more failures.

• UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 3 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

    • 24.otp_ctrl_stress_all_with_rand_reset.2014926806
      Line 2372, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1509802505874 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 1509802505874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 61.otp_ctrl_stress_all_with_rand_reset.928610139
      Line 344, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 431867731130 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 431867731130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

Past Results

• Latest
• 2023.05.17_17.59.32
• 2023.05.16_19.23.36
• 2023.05.15_18.41.17
• 2023.05.14_18.09.01
• 2023.05.13_18.52.45
• 2023.05.12_18.43.45
• 2023.05.12_11.24.22