Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12971	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31461

1

T1

10

T2

276

T3

500

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17997	1			T1	11		T2	73		T3	176
values[0x0]	12655	1			T1	3		T2	115		T3	160
values[0x1]	13780	1			T1	8		T2	218		T3	165

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9524	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

34908

1

T1

14

T2

350

T3

500

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	167	1			T3	8		T6	2		T8	24
valid_sources[0x01]	203	1			T16	1		T13	1		T24	1
valid_sources[0x02]	230	1			T6	1		T4	4		T21	2
valid_sources[0x03]	134	1			T2	1		T13	2		T11	3
valid_sources[0x04]	169	1			T2	4		T3	29		T16	3
valid_sources[0x05]	278	1			T15	1		T8	41		T16	3
valid_sources[0x06]	128	1			T6	5		T16	2		T10	1
valid_sources[0x07]	128	1			T16	2		T13	4		T24	1
valid_sources[0x08]	223	1			T6	10		T14	14		T21	5
valid_sources[0x09]	139	1			T1	1		T2	1		T16	3
valid_sources[0x0a]	177	1			T7	40		T16	1		T69	1
valid_sources[0x0b]	142	1			T16	1		T13	3		T24	2
valid_sources[0x0c]	116	1			T2	1		T8	5		T16	1
valid_sources[0x0d]	183	1			T16	4		T13	2		T25	2
valid_sources[0x0e]	262	1			T16	1		T69	1		T13	5
valid_sources[0x0f]	179	1			T8	11		T16	1		T10	1
valid_sources[0x10]	164	1			T6	9		T16	2		T13	1
valid_sources[0x11]	152	1			T2	5		T21	1		T16	1
valid_sources[0x12]	172	1			T14	1		T8	22		T16	2
valid_sources[0x13]	152	1			T14	22		T16	2		T24	3
valid_sources[0x14]	165	1			T2	3		T8	16		T16	1
valid_sources[0x15]	292	1			T2	3		T14	12		T16	2
valid_sources[0x16]	162	1			T3	12		T17	3		T95	6
valid_sources[0x17]	194	1			T1	1		T8	15		T13	2
valid_sources[0x18]	121	1			T15	1		T14	6		T16	1
valid_sources[0x19]	182	1			T2	1		T6	10		T13	1
valid_sources[0x1a]	227	1			T2	1		T21	1		T16	2
valid_sources[0x1b]	217	1			T1	1		T2	1		T16	1
valid_sources[0x1c]	164	1			T6	21		T8	9		T10	1
valid_sources[0x1d]	155	1			T2	1		T3	23		T6	1
valid_sources[0x1e]	181	1			T2	2		T8	2		T16	3
valid_sources[0x1f]	129	1			T14	1		T8	23		T16	3
valid_sources[0x20]	118	1			T8	1		T16	2		T69	1
valid_sources[0x21]	189	1			T2	4		T14	5		T8	7
valid_sources[0x22]	190	1			T4	3		T16	2		T10	1
valid_sources[0x23]	158	1			T8	7		T25	1		T33	4
valid_sources[0x24]	151	1			T2	3		T5	12		T16	2
valid_sources[0x25]	171	1			T2	5		T14	4		T8	9
valid_sources[0x26]	123	1			T2	6		T6	3		T16	1
valid_sources[0x27]	196	1			T6	11		T5	19		T13	1
valid_sources[0x28]	139	1			T16	1		T13	2		T25	4
valid_sources[0x29]	195	1			T2	1		T14	7		T21	1
valid_sources[0x2a]	135	1			T13	1		T11	1		T25	3
valid_sources[0x2b]	237	1			T69	3		T13	1		T11	12
valid_sources[0x2c]	199	1			T2	1		T5	19		T16	1
valid_sources[0x2d]	150	1			T3	6		T16	2		T13	5
valid_sources[0x2e]	161	1			T2	26		T9	22		T16	1
valid_sources[0x2f]	195	1			T8	7		T13	3		T24	1
valid_sources[0x30]	179	1			T6	1		T15	1		T4	2
valid_sources[0x31]	217	1			T3	12		T6	20		T14	26
valid_sources[0x32]	147	1			T3	1		T6	15		T16	3
valid_sources[0x33]	263	1			T2	2		T13	2		T25	3
valid_sources[0x34]	182	1			T16	1		T13	2		T25	2
valid_sources[0x35]	217	1			T8	1		T5	22		T16	2
valid_sources[0x36]	187	1			T14	50		T25	1		T17	2
valid_sources[0x37]	119	1			T2	4		T8	6		T16	2
valid_sources[0x38]	137	1			T6	6		T4	1		T8	1
valid_sources[0x39]	203	1			T8	2		T16	1		T13	1
valid_sources[0x3a]	264	1			T3	1		T6	19		T14	12
valid_sources[0x3b]	220	1			T2	1		T15	1		T8	21
valid_sources[0x3c]	185	1			T2	3		T6	21		T10	1
valid_sources[0x3d]	171	1			T14	1		T8	11		T16	2
valid_sources[0x3e]	143	1			T2	2		T16	1		T13	1
valid_sources[0x3f]	170	1			T16	2		T69	1		T13	6
valid_sources[0x40]	199	1			T4	5		T8	6		T16	2
valid_sources[0x41]	156	1			T3	7		T4	9		T14	1
valid_sources[0x42]	183	1			T3	10		T8	2		T5	11
valid_sources[0x43]	234	1			T1	2		T2	5		T3	4
valid_sources[0x44]	173	1			T2	12		T8	18		T5	9
valid_sources[0x45]	146	1			T2	3		T3	1		T16	2
valid_sources[0x46]	125	1			T16	2		T25	2		T17	1
valid_sources[0x47]	131	1			T3	4		T21	4		T16	1
valid_sources[0x48]	156	1			T8	7		T10	1		T24	2
valid_sources[0x49]	187	1			T2	1		T16	4		T69	1
valid_sources[0x4a]	94	1			T2	3		T16	2		T25	2
valid_sources[0x4b]	220	1			T2	1		T6	58		T13	3
valid_sources[0x4c]	105	1			T5	6		T16	2		T13	4
valid_sources[0x4d]	246	1			T3	15		T5	86		T16	2
valid_sources[0x4e]	177	1			T8	10		T13	3		T25	1
valid_sources[0x4f]	253	1			T2	5		T16	2		T11	147
valid_sources[0x50]	175	1			T2	2		T3	21		T8	5
valid_sources[0x51]	157	1			T3	14		T4	11		T16	1
valid_sources[0x52]	165	1			T6	3		T8	11		T16	4
valid_sources[0x53]	147	1			T6	41		T14	7		T16	1
valid_sources[0x54]	178	1			T2	2		T3	2		T6	4
valid_sources[0x55]	127	1			T3	14		T14	11		T16	2
valid_sources[0x56]	229	1			T2	1		T3	3		T15	1
valid_sources[0x57]	140	1			T2	14		T16	1		T69	1
valid_sources[0x58]	117	1			T3	12		T4	7		T16	1
valid_sources[0x59]	187	1			T3	8		T16	4		T13	3
valid_sources[0x5a]	95	1			T16	2		T24	1		T25	1
valid_sources[0x5b]	148	1			T2	8		T3	5		T15	1
valid_sources[0x5c]	159	1			T2	7		T14	10		T16	2
valid_sources[0x5d]	142	1			T5	7		T12	4		T17	2
valid_sources[0x5e]	195	1			T8	6		T16	4		T13	1
valid_sources[0x5f]	220	1			T2	2		T14	3		T13	3
valid_sources[0x60]	149	1			T2	1		T16	1		T25	1
valid_sources[0x61]	204	1			T2	2		T6	11		T8	4
valid_sources[0x62]	261	1			T2	2		T8	13		T11	83
valid_sources[0x63]	209	1			T2	2		T3	14		T14	11
valid_sources[0x64]	105	1			T15	1		T13	2		T25	1
valid_sources[0x65]	164	1			T8	2		T16	2		T25	1
valid_sources[0x66]	188	1			T2	1		T3	5		T15	1
valid_sources[0x67]	164	1			T8	10		T16	3		T13	2
valid_sources[0x68]	281	1			T2	7		T8	54		T5	19
valid_sources[0x69]	135	1			T2	3		T3	6		T4	5
valid_sources[0x6a]	202	1			T8	13		T10	1		T13	2
valid_sources[0x6b]	188	1			T1	1		T2	1		T6	29
valid_sources[0x6c]	166	1			T2	1		T4	10		T16	2
valid_sources[0x6d]	173	1			T2	2		T13	2		T12	2
valid_sources[0x6e]	190	1			T6	10		T8	4		T5	1
valid_sources[0x6f]	166	1			T2	1		T3	7		T5	1
valid_sources[0x70]	150	1			T3	12		T16	3		T13	1
valid_sources[0x71]	173	1			T3	4		T15	1		T8	3
valid_sources[0x72]	131	1			T2	1		T16	1		T13	2
valid_sources[0x73]	136	1			T2	1		T69	1		T13	2
valid_sources[0x74]	168	1			T1	1		T15	1		T8	4
valid_sources[0x75]	171	1			T16	1		T13	2		T24	2
valid_sources[0x76]	170	1			T2	3		T6	9		T16	2
valid_sources[0x77]	148	1			T6	4		T13	3		T24	2
valid_sources[0x78]	97	1			T6	2		T10	2		T69	1
valid_sources[0x79]	158	1			T2	1		T8	35		T16	1
valid_sources[0x7a]	180	1			T1	1		T2	1		T3	13
valid_sources[0x7b]	226	1			T5	25		T16	1		T13	3
valid_sources[0x7c]	136	1			T16	2		T10	1		T24	3
valid_sources[0x7d]	189	1			T2	1		T6	25		T16	1
valid_sources[0x7e]	112	1			T16	1		T13	1		T24	1
valid_sources[0x7f]	186	1			T3	9		T21	1		T16	1
valid_sources[0x80]	159	1			T1	1		T2	4		T3	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10339

1

T1

7

T2

70

T3

175

values[0x0]

all_enables

biggest_size

10785

1

T1

2

T2

103

T3

160

values[0x1]

all_enables

biggest_size

10337

1

T1

1

T2

103

T3

165

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12854	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

21809

1

T2

277

T3

142

T6

342

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18363	1			T2	71		T3	73		T6	86
values[0x0]	7902	1			T2	109		T3	32		T6	123
values[0x1]	8398	1			T2	114		T3	37		T6	147

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8750	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

25913

1

T2

289

T3

142

T6

348

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	199	1			T14	1		T8	4		T5	1
valid_sources[0x01]	121	1			T2	3		T8	6		T5	1
valid_sources[0x02]	166	1			T2	2		T6	4		T8	2
valid_sources[0x03]	152	1			T2	3		T14	2		T8	3
valid_sources[0x04]	134	1			T2	4		T14	3		T8	3
valid_sources[0x05]	175	1			T8	7		T5	2		T25	1
valid_sources[0x06]	143	1			T14	2		T8	2		T5	3
valid_sources[0x07]	141	1			T2	1		T14	2		T8	3
valid_sources[0x08]	109	1			T2	4		T6	1		T14	1
valid_sources[0x09]	103	1			T6	2		T14	1		T8	3
valid_sources[0x0a]	104	1			T2	2		T8	4		T5	3
valid_sources[0x0b]	130	1			T4	1		T8	8		T5	4
valid_sources[0x0c]	122	1			T2	3		T14	3		T8	5
valid_sources[0x0d]	133	1			T2	1		T8	7		T11	10
valid_sources[0x0e]	91	1			T8	1		T5	4		T16	2
valid_sources[0x0f]	134	1			T14	2		T8	7		T5	3
valid_sources[0x10]	172	1			T6	1		T4	10		T8	2
valid_sources[0x11]	222	1			T2	1		T6	12		T14	1
valid_sources[0x12]	65	1			T14	2		T8	3		T5	4
valid_sources[0x13]	116	1			T14	1		T8	4		T16	3
valid_sources[0x14]	128	1			T2	3		T6	18		T14	3
valid_sources[0x15]	148	1			T2	1		T4	7		T14	2
valid_sources[0x16]	101	1			T3	5		T14	1		T8	2
valid_sources[0x17]	132	1			T2	1		T6	22		T8	3
valid_sources[0x18]	167	1			T3	3		T14	1		T8	5
valid_sources[0x19]	183	1			T14	2		T8	8		T5	1
valid_sources[0x1a]	138	1			T6	2		T14	2		T8	4
valid_sources[0x1b]	152	1			T2	1		T8	5		T16	1
valid_sources[0x1c]	92	1			T2	1		T14	1		T8	1
valid_sources[0x1d]	125	1			T14	1		T8	3		T11	7
valid_sources[0x1e]	174	1			T14	1		T8	5		T16	4
valid_sources[0x1f]	144	1			T2	3		T3	2		T6	12
valid_sources[0x20]	152	1			T2	6		T6	18		T14	1
valid_sources[0x21]	124	1			T2	1		T14	1		T8	4
valid_sources[0x22]	139	1			T3	2		T6	1		T14	4
valid_sources[0x23]	170	1			T14	3		T8	4		T16	2
valid_sources[0x24]	117	1			T14	1		T8	4		T16	1
valid_sources[0x25]	121	1			T2	3		T3	2		T8	3
valid_sources[0x26]	114	1			T14	1		T8	6		T5	4
valid_sources[0x27]	144	1			T2	1		T14	3		T8	4
valid_sources[0x28]	141	1			T2	1		T14	1		T8	2
valid_sources[0x29]	148	1			T8	6		T5	6		T16	1
valid_sources[0x2a]	120	1			T3	4		T8	4		T5	3
valid_sources[0x2b]	200	1			T2	5		T14	1		T8	5
valid_sources[0x2c]	101	1			T6	1		T16	3		T11	9
valid_sources[0x2d]	143	1			T14	3		T8	4		T16	1
valid_sources[0x2e]	106	1			T3	8		T14	2		T8	9
valid_sources[0x2f]	109	1			T2	2		T14	1		T8	2
valid_sources[0x30]	160	1			T4	10		T8	9		T5	5
valid_sources[0x31]	170	1			T3	1		T6	10		T8	3
valid_sources[0x32]	184	1			T6	9		T14	2		T8	3
valid_sources[0x33]	132	1			T14	2		T8	4		T5	1
valid_sources[0x34]	97	1			T3	4		T8	6		T5	5
valid_sources[0x35]	95	1			T14	1		T8	6		T25	1
valid_sources[0x36]	169	1			T14	3		T8	3		T5	7
valid_sources[0x37]	138	1			T2	3		T8	4		T5	7
valid_sources[0x38]	147	1			T8	1		T5	2		T13	20
valid_sources[0x39]	101	1			T3	4		T14	1		T8	3
valid_sources[0x3a]	241	1			T2	1		T14	1		T8	5
valid_sources[0x3b]	121	1			T14	1		T8	5		T5	5
valid_sources[0x3c]	131	1			T6	1		T14	1		T8	2
valid_sources[0x3d]	112	1			T2	3		T14	1		T8	4
valid_sources[0x3e]	160	1			T2	7		T14	2		T8	7
valid_sources[0x3f]	110	1			T14	2		T8	10		T5	4
valid_sources[0x40]	93	1			T3	1		T14	4		T8	1
valid_sources[0x41]	124	1			T4	10		T8	8		T5	2
valid_sources[0x42]	103	1			T6	2		T14	2		T8	3
valid_sources[0x43]	143	1			T2	1		T14	1		T8	2
valid_sources[0x44]	121	1			T14	2		T8	3		T5	1
valid_sources[0x45]	106	1			T14	2		T8	2		T16	1
valid_sources[0x46]	143	1			T6	1		T14	2		T8	9
valid_sources[0x47]	204	1			T8	5		T5	3		T16	2
valid_sources[0x48]	162	1			T14	2		T8	2		T5	3
valid_sources[0x49]	139	1			T2	1		T14	2		T8	2
valid_sources[0x4a]	215	1			T14	1		T8	1		T5	6
valid_sources[0x4b]	90	1			T5	1		T16	1		T25	3
valid_sources[0x4c]	192	1			T2	2		T4	3		T14	1
valid_sources[0x4d]	126	1			T8	3		T5	3		T16	1
valid_sources[0x4e]	152	1			T2	3		T14	1		T8	4
valid_sources[0x4f]	94	1			T14	4		T8	6		T5	4
valid_sources[0x50]	443	1			T3	1		T6	30		T8	1
valid_sources[0x51]	181	1			T14	1		T8	6		T5	2
valid_sources[0x52]	162	1			T2	12		T14	1		T8	2
valid_sources[0x53]	174	1			T2	4		T6	16		T8	3
valid_sources[0x54]	102	1			T8	2		T5	1		T16	2
valid_sources[0x55]	144	1			T14	1		T8	7		T5	3
valid_sources[0x56]	88	1			T14	3		T8	2		T5	4
valid_sources[0x57]	181	1			T14	2		T8	8		T16	2
valid_sources[0x58]	120	1			T14	2		T8	2		T16	1
valid_sources[0x59]	129	1			T14	4		T8	5		T5	1
valid_sources[0x5a]	143	1			T2	4		T14	3		T8	3
valid_sources[0x5b]	109	1			T2	5		T8	2		T5	1
valid_sources[0x5c]	115	1			T14	2		T8	3		T5	2
valid_sources[0x5d]	104	1			T8	4		T5	5		T16	1
valid_sources[0x5e]	155	1			T14	2		T8	5		T5	1
valid_sources[0x5f]	108	1			T8	2		T5	4		T16	3
valid_sources[0x60]	176	1			T14	3		T8	6		T5	7
valid_sources[0x61]	145	1			T2	1		T14	2		T8	3
valid_sources[0x62]	112	1			T2	1		T14	2		T8	3
valid_sources[0x63]	105	1			T3	1		T6	5		T8	3
valid_sources[0x64]	118	1			T8	2		T5	4		T24	1
valid_sources[0x65]	193	1			T2	1		T3	5		T14	2
valid_sources[0x66]	125	1			T14	1		T8	3		T16	2
valid_sources[0x67]	133	1			T14	1		T8	1		T5	1
valid_sources[0x68]	133	1			T2	1		T3	4		T8	4
valid_sources[0x69]	98	1			T3	1		T14	2		T8	5
valid_sources[0x6a]	140	1			T2	1		T6	3		T8	3
valid_sources[0x6b]	102	1			T2	1		T14	2		T8	2
valid_sources[0x6c]	137	1			T14	1		T8	1		T16	7
valid_sources[0x6d]	130	1			T2	8		T14	1		T8	4
valid_sources[0x6e]	163	1			T2	5		T8	14		T5	1
valid_sources[0x6f]	161	1			T6	12		T8	3		T5	4
valid_sources[0x70]	117	1			T2	3		T14	2		T8	7
valid_sources[0x71]	139	1			T2	1		T14	2		T16	3
valid_sources[0x72]	156	1			T6	16		T14	1		T8	5
valid_sources[0x73]	102	1			T2	2		T8	2		T5	4
valid_sources[0x74]	155	1			T2	1		T3	1		T8	6
valid_sources[0x75]	158	1			T14	1		T8	3		T5	7
valid_sources[0x76]	176	1			T14	1		T8	2		T5	2
valid_sources[0x77]	118	1			T14	1		T8	2		T5	2
valid_sources[0x78]	176	1			T2	1		T14	1		T8	3
valid_sources[0x79]	133	1			T6	3		T14	1		T8	2
valid_sources[0x7a]	156	1			T3	2		T6	9		T8	7
valid_sources[0x7b]	182	1			T2	1		T14	2		T8	7
valid_sources[0x7c]	141	1			T8	1		T5	2		T16	3
valid_sources[0x7d]	139	1			T2	2		T14	1		T8	6
valid_sources[0x7e]	91	1			T8	9		T5	3		T25	1
valid_sources[0x7f]	116	1			T14	1		T8	5		T5	4
valid_sources[0x80]	148	1			T2	4		T3	2		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7633

1

T2

71

T3

73

T6

86

values[0x0]

all_enables

biggest_size

7217

1

T2

108

T3

32

T6

122

values[0x1]

all_enables

biggest_size

6959

1

T2

98

T3

37

T6

134