Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

31764

1

T1

12

T2

1223

T3

1

full_word

32734

1

T1

10

T2

331

T3

500

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	64178	1			T1	22		T2	1554		T3	501
auto[TlIntgErrCmd]	111	1			T5	6		T11	8		T12	6
auto[TlIntgErrData]	111	1			T5	6		T11	9		T12	7
auto[TlIntgErrBoth]	98	1			T5	8		T11	3		T12	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19624

1

T1

11

T2

130

T3

176

auto[1]

44874

1

T1

11

T2

1424

T3

325

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8977	1			T1	4		T2	56		T3	1
auto[TlIntgErrNone]	partial	auto[1]	22496	1			T1	8		T2	1167		T7	18
auto[TlIntgErrNone]	full_word	auto[0]	10496	1			T1	7		T2	74		T3	175
auto[TlIntgErrNone]	full_word	auto[1]	22209	1			T1	3		T2	257		T3	325
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T5	3		T11	4		T12	4
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T5	3		T11	3		T12	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T22	1		T92	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T11	1		T12	1		T70	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T5	3		T11	5		T12	4
auto[TlIntgErrData]	partial	auto[1]	53	1			T5	2		T11	4		T12	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T5	1		T88	1		T90	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T12	1		T87	1		T93	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T5	3		T11	2		T12	4
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T5	5		T11	1		T12	2
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T70	1		T89	1		T94	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T12	1		T22	1		T89	1