Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.62						84.62

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	84.62						84.62

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.62						84.62

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.62						84.62

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
7.86	0.00	0.00	31.46		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	11	84.62
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	11	84.62

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2922894	8229	0	0
check_regwen_rd_A	2922894	1283	0	0
check_timeout_rd_A	2922894	643	0	0
check_trigger_regwen_rd_A	2922894	1290	0	0
consistency_check_period_rd_A	2922894	1215	0	0
creator_sw_cfg_read_lock_rd_A	2922894	777	0	0
direct_access_address_rd_A	2922894	57	0	0
direct_access_wdata_0_rd_A	2922894	0	0	0
direct_access_wdata_1_rd_A	2922894	0	0	0
integrity_check_period_rd_A	2922894	1174	0	0
intr_enable_rd_A	2922894	1626	0	0
owner_sw_cfg_read_lock_rd_A	2922894	899	0	0
vendor_test_read_lock_rd_A	2922894	925	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	8229	0	0
T2	14344	297	0	0
T3	9951	0	0	0
T4	6884	21	0	0
T5	0	5	0	0
T6	18742	843	0	0
T7	3762	0	0	0
T8	22197	0	0	0
T9	3890	0	0	0
T11	0	5	0	0
T12	0	6	0	0
T13	0	179	0	0
T14	12905	368	0	0
T15	3432	0	0	0
T16	0	483	0	0
T17	0	310	0	0
T21	3337	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	1283	0	0
T4	6884	5	0	0
T5	111547	0	0	0
T8	22197	0	0	0
T9	3890	0	0	0
T10	3629	0	0	0
T14	12905	0	0	0
T16	13173	0	0	0
T18	0	6	0	0
T21	3337	0	0	0
T25	0	44	0	0
T28	0	56	0	0
T30	0	61	0	0
T38	0	3	0	0
T39	0	60	0	0
T51	0	25	0	0
T68	3228	0	0	0
T69	3572	0	0	0
T70	0	52	0	0
T71	0	28	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	643	0	0
T4	6884	6	0	0
T5	111547	0	0	0
T8	22197	0	0	0
T9	3890	0	0	0
T10	3629	0	0	0
T14	12905	0	0	0
T16	13173	0	0	0
T21	3337	0	0	0
T25	0	12	0	0
T28	0	25	0	0
T30	0	43	0	0
T39	0	21	0	0
T51	0	19	0	0
T55	0	6	0	0
T68	3228	0	0	0
T69	3572	0	0	0
T71	0	8	0	0
T72	0	4	0	0
T73	0	2	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	1290	0	0
T4	6884	5	0	0
T5	111547	0	0	0
T8	22197	0	0	0
T9	3890	0	0	0
T10	3629	0	0	0
T14	12905	3	0	0
T16	13173	0	0	0
T17	0	3	0	0
T21	3337	0	0	0
T25	0	43	0	0
T28	0	62	0	0
T30	0	70	0	0
T38	0	11	0	0
T39	0	16	0	0
T51	0	6	0	0
T68	3228	0	0	0
T69	3572	0	0	0
T70	0	45	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	1215	0	0
T4	6884	6	0	0
T5	111547	0	0	0
T8	22197	0	0	0
T9	3890	0	0	0
T10	3629	0	0	0
T14	12905	0	0	0
T16	13173	0	0	0
T18	0	5	0	0
T21	3337	0	0	0
T25	0	77	0	0
T28	0	48	0	0
T30	0	80	0	0
T38	0	8	0	0
T39	0	21	0	0
T51	0	3	0	0
T68	3228	0	0	0
T69	3572	0	0	0
T70	0	52	0	0
T71	0	18	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	777	0	0
T2	14344	7	0	0
T3	9951	0	0	0
T4	6884	7	0	0
T6	18742	0	0	0
T7	3762	0	0	0
T8	22197	0	0	0
T9	3890	0	0	0
T14	12905	0	0	0
T15	3432	0	0	0
T21	3337	0	0	0
T25	0	14	0	0
T28	0	30	0	0
T30	0	76	0	0
T39	0	17	0	0
T51	0	32	0	0
T55	0	3	0	0
T71	0	10	0	0
T72	0	7	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	57	0	0
T4	6884	3	0	0
T5	111547	0	0	0
T6	18742	4	0	0
T8	22197	0	0	0
T9	3890	0	0	0
T14	12905	0	0	0
T15	3432	0	0	0
T16	13173	0	0	0
T18	0	4	0	0
T21	3337	0	0	0
T55	0	4	0	0
T68	3228	0	0	0
T71	0	10	0	0
T73	0	2	0	0
T74	0	13	0	0
T75	0	8	0	0
T76	0	5	0	0
T77	0	4	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	1174	0	0
T4	6884	10	0	0
T5	111547	0	0	0
T8	22197	0	0	0
T9	3890	0	0	0
T10	3629	0	0	0
T14	12905	0	0	0
T16	13173	1	0	0
T18	0	1	0	0
T21	3337	0	0	0
T25	0	24	0	0
T28	0	43	0	0
T30	0	36	0	0
T38	0	7	0	0
T39	0	10	0	0
T51	0	9	0	0
T68	3228	0	0	0
T69	3572	0	0	0
T70	0	46	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	1626	0	0
T4	6884	8	0	0
T5	111547	0	0	0
T8	22197	0	0	0
T9	3890	0	0	0
T10	3629	0	0	0
T14	12905	0	0	0
T16	13173	0	0	0
T18	0	7	0	0
T21	3337	0	0	0
T25	0	44	0	0
T28	0	48	0	0
T30	0	72	0	0
T38	0	5	0	0
T50	0	13	0	0
T68	3228	0	0	0
T69	3572	18	0	0
T78	0	18	0	0
T79	0	8	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	899	0	0
T4	6884	8	0	0
T5	111547	0	0	0
T8	22197	0	0	0
T9	3890	0	0	0
T10	3629	0	0	0
T14	12905	0	0	0
T16	13173	0	0	0
T18	0	5	0	0
T21	3337	0	0	0
T25	0	68	0	0
T28	0	51	0	0
T30	0	78	0	0
T39	0	38	0	0
T55	0	3	0	0
T68	3228	0	0	0
T69	3572	0	0	0
T71	0	9	0	0
T72	0	27	0	0
T73	0	1	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	925	0	0
T12	109859	0	0	0
T17	10902	0	0	0
T18	0	5	0	0
T25	8295	32	0	0
T26	3973	0	0	0
T28	0	59	0	0
T30	0	71	0	0
T32	3905	0	0	0
T33	3498	0	0	0
T34	3780	0	0	0
T35	3660	0	0	0
T36	3533	0	0	0
T37	3202	0	0	0
T39	0	40	0	0
T51	0	16	0	0
T55	0	11	0	0
T71	0	10	0	0
T72	0	61	0	0
T80	0	5	0	0