Unified Coverage Report :: Module :: prim_generic_otp

Module : prim_generic_otp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp.gen_generic.u_impl_generic	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.08	66.09	71.21	94.69	0.00	76.47	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_otp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_dec	0.00	0.00	0.00
u_enc	0.00	0.00
u_prim_ram_1p_adv	0.00	0.00	0.00			0.00
u_reg_top	93.34	89.51	92.70	94.69		89.82	100.00
u_state_regs	0.00	0.00				0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_otp

	Line No.	Total	Covered	Percent
TOTAL		97	0	0.00
CONT_ASSIGN	74	1	0	0.00
CONT_ASSIGN	78	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	90	1	0	0.00
CONT_ASSIGN	114	1	0	0.00
CONT_ASSIGN	170	1	0	0.00
CONT_ASSIGN	173	1	0	0.00
CONT_ASSIGN	174	1	0	0.00
ALWAYS	178	60	0	0.00
CONT_ASSIGN	302	1	0	0.00
CONT_ASSIGN	322	1	0	0.00
CONT_ASSIGN	326	1	0	0.00
CONT_ASSIGN	329	1	0	0.00
ALWAYS	333	0	0
ALWAYS	333	3	0	0.00
ALWAYS	366	3	0	0.00
ALWAYS	369	17	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
74	0	1
78	0	1
82	0	1
84	0	1
87	0	1
90	0	1
114	0	1
170	0	1
173	0	1
174	0	1
178	0	1
179	0	1
180	0	1
181	0	1
182	0	1
183	0	1
184	0	1
185	0	1
186	0	1
187	0	1
189	0	1
192	0	1
193	0	1
194	0	1
195	0	1
196	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
202	0	1
203	0	1
204	0	1
208	0	1
209	0	1
210	0	1
211	0	1
212	0	1
213	0	1
214	0	1
215	0	1
			==> MISSING_ELSE
222	0	1
223	0	1
227	0	1
228	0	1
230	0	1
231	0	1
232	0	1
233	0	1
235	0	1
236	0	1
237	0	1
239	0	1
242	0	1
243	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
251	0	1
252	0	1
254	0	1
259	0	1
260	0	1
261	0	1
263	0	1
264	0	1
265	0	1
267	0	1
			==> MISSING_ELSE
274	0	1
275	0	1
276	0	1
277	0	1
278	0	1
			==> MISSING_ELSE
281	0	1
282	0	1
283	0	1
			==> MISSING_ELSE
288	0	1
302	0	1
322	0	1
326	0	1
329	0	1
333	0	1
334	0	1
336	0	1
366	0	3
369	0	1
370	0	1
371	0	1
372	0	1
373	0	1
374	0	1
375	0	1
376	0	1
378	0	1
379	0	1
380	0	1
381	0	1
382	0	1
383	0	1
384	0	1
			==> MISSING_ELSE
386	0	1
387	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_generic_otp

	Total	Covered	Percent
Conditions	22	0	0.00
Logical	22	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       90
 EXPRESSION (intg_err || fsm_err)
             ----1---    ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       170
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       170
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       195
 EXPRESSION (cmd_i == Init)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       235
 EXPRESSION (cnt_q == size_q)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       263
 EXPRESSION (cnt_q == size_q)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       281
 EXPRESSION (cnt_q == size_q)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       322
 EXPRESSION (read_ecc_on ? ({{EccWidth {1'b0}}, rdata_corr}) : rdata_ecc)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       329
 EXPRESSION ((rdata_q[cnt_q] & wdata_ecc) != rdata_q[cnt_q])
            ------------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       381
 EXPRESSION (ready_o && valid_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

FSM Coverage for Module : prim_generic_otp

Summary for FSM :: state_q

	Total	Covered	Percent
States	9	0	0.00	(Not included in score)
Transitions	11	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	287	Not Covered
IdleSt	202	Not Covered
InitSt	196	Not Covered
ReadSt	214	Not Covered
ReadWaitSt	222	Not Covered
ResetSt	191	Not Covered
WriteCheckSt	215	Not Covered
WriteSt	265	Not Covered
WriteWaitSt	251	Not Covered

transitions	Line No.	Covered	Tests
IdleSt->ReadSt	214	Not Covered
IdleSt->WriteCheckSt	215	Not Covered
InitSt->IdleSt	202	Not Covered
ReadSt->ReadWaitSt	222	Not Covered
ReadWaitSt->IdleSt	231	Not Covered
ReadWaitSt->ReadSt	239	Not Covered
ResetSt->InitSt	196	Not Covered
WriteCheckSt->WriteWaitSt	251	Not Covered
WriteSt->IdleSt	283	Not Covered
WriteWaitSt->WriteCheckSt	267	Not Covered
WriteWaitSt->WriteSt	265	Not Covered

---

Branch Coverage for Module : prim_generic_otp

	Line No.	Total	Covered	Percent
Branches		37	0	0.00
TERNARY	170	3	0	0.00
TERNARY	322	2	0	0.00
CASE	189	25	0	0.00
IF	366	2	0	0.00
IF	369	5	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	170	(cnt_clr) ? 
-2-:	170	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	322	(read_ecc_on) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	189	case (state_q)
-2-:	194	if (valid_i)
-3-:	195	if ((cmd_i == Init))
-4-:	210	if (valid_i)
-5-:	213	case (cmd_i)
-6-:	227	if (rvalid)
-7-:	230	if (rerror[1])
-8-:	235	if ((cnt_q == size_q))
-9-:	242	if (rerror[0])
-10-:	260	if (rvalid)
-11-:	263	if ((cnt_q == size_q))
-12-:	277	if (wdata_inconsistent)
-13-:	281	if ((cnt_q == size_q))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	Read	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	Write	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	default	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	1	0	1	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	1	0	0	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	1	0	-	1	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	1	0	-	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
WriteCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	1	1	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	366	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	369	if ((!rst_ni))
-2-:	381	if ((ready_o && valid_i))
-3-:	386	if (rvalid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	-	Not Covered
0	-	1	Not Covered
0	-	0	Not Covered