Unified Coverage Report :: Module :: otp_ctrl_core_reg_top

Module : otp_ctrl_core_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.38	100.00	89.52			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core	97.38	100.00	89.52			100.00	100.00

---

Module Instance : tb.dut.u_reg_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.38	100.00	89.52			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	93.92	92.66	90.32		98.36	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
7.86	0.00	0.00	31.46		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_bus_integ_error	100.00	100.00
u_alert_test_fatal_check_error	100.00	100.00
u_alert_test_fatal_macro_error	100.00	100.00
u_alert_test_fatal_prim_otp_alert	100.00	100.00
u_alert_test_recov_prim_otp_alert	100.00	100.00
u_check_regwen	100.00	100.00	100.00			100.00
u_check_timeout	65.34	88.89	50.00			57.14
u_check_trigger_consistency	100.00	100.00
u_check_trigger_integrity	100.00	100.00
u_check_trigger_regwen	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_consistency_check_period	100.00	100.00	100.00			100.00
u_creator_sw_cfg_digest_0	66.67	66.67
u_creator_sw_cfg_digest_1	66.67	66.67
u_creator_sw_cfg_read_lock	100.00	100.00	100.00			100.00
u_direct_access_address	100.00	100.00	100.00			100.00
u_direct_access_cmd_digest	100.00	100.00
u_direct_access_cmd_rd	100.00	100.00
u_direct_access_cmd_wr	100.00	100.00
u_direct_access_rdata_0	100.00	100.00
u_direct_access_rdata_1	100.00	100.00
u_direct_access_regwen	100.00	100.00
u_direct_access_wdata_0	100.00	100.00	100.00			100.00
u_direct_access_wdata_1	100.00	100.00	100.00			100.00
u_err_code_err_code_0	66.67	66.67
u_err_code_err_code_1	66.67	66.67
u_err_code_err_code_2	66.67	66.67
u_err_code_err_code_3	66.67	66.67
u_err_code_err_code_4	66.67	66.67
u_err_code_err_code_5	66.67	66.67
u_err_code_err_code_6	66.67	66.67
u_err_code_err_code_7	66.67	66.67
u_err_code_err_code_8	66.67	66.67
u_err_code_err_code_9	66.67	66.67
u_hw_cfg_digest_0	66.67	66.67
u_hw_cfg_digest_1	66.67	66.67
u_integrity_check_period	100.00	100.00	100.00			100.00
u_intr_enable_otp_error	100.00	100.00	100.00			100.00
u_intr_enable_otp_operation_done	100.00	100.00	100.00			100.00
u_intr_state_otp_error	100.00	100.00	100.00			100.00
u_intr_state_otp_operation_done	100.00	100.00	100.00			100.00
u_intr_test_otp_error	100.00	100.00
u_intr_test_otp_operation_done	100.00	100.00
u_owner_sw_cfg_digest_0	66.67	66.67
u_owner_sw_cfg_digest_1	100.00	100.00
u_owner_sw_cfg_read_lock	100.00	100.00	100.00			100.00
u_prim_reg_we_check	50.00	100.00		0.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_secret0_digest_0	66.67	66.67
u_secret0_digest_1	66.67	66.67
u_secret1_digest_0	66.67	66.67
u_secret1_digest_1	66.67	66.67
u_secret2_digest_0	66.67	66.67
u_secret2_digest_1	66.67	66.67
u_socket	99.24	98.75	98.21			100.00	100.00
u_status_bus_integ_error	66.67	66.67
u_status_check_pending	66.67	66.67
u_status_creator_sw_cfg_error	66.67	66.67
u_status_dai_error	66.67	66.67
u_status_dai_idle	66.67	66.67
u_status_hw_cfg_error	66.67	66.67
u_status_key_deriv_fsm_error	66.67	66.67
u_status_lci_error	66.67	66.67
u_status_lfsr_fsm_error	66.67	66.67
u_status_life_cycle_error	66.67	66.67
u_status_owner_sw_cfg_error	66.67	66.67
u_status_scrambling_fsm_error	66.67	66.67
u_status_secret0_error	66.67	66.67
u_status_secret1_error	66.67	66.67
u_status_secret2_error	66.67	66.67
u_status_timeout_error	66.67	66.67
u_status_vendor_test_error	66.67	66.67
u_vendor_test_digest_0	66.67	66.67
u_vendor_test_digest_1	66.67	66.67
u_vendor_test_read_lock	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : otp_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
TOTAL		255	255	100.00
ALWAYS	76	4	4	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
ALWAYS	133	3	3	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	483	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	963	1	1	100.00
CONT_ASSIGN	966	1	1	100.00
CONT_ASSIGN	981	1	1	100.00
CONT_ASSIGN	997	1	1	100.00
CONT_ASSIGN	1013	1	1	100.00
CONT_ASSIGN	1019	1	1	100.00
CONT_ASSIGN	1051	1	1	100.00
CONT_ASSIGN	1083	1	1	100.00
CONT_ASSIGN	1176	1	1	100.00
CONT_ASSIGN	1179	1	1	100.00
CONT_ASSIGN	1194	1	1	100.00
CONT_ASSIGN	1210	1	1	100.00
CONT_ASSIGN	1244	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1337	1	1	100.00
CONT_ASSIGN	1368	1	1	100.00
CONT_ASSIGN	1399	1	1	100.00
ALWAYS	1668	37	37	100.00
CONT_ASSIGN	1707	1	1	100.00
ALWAYS	1711	1	1	100.00
CONT_ASSIGN	1751	1	1	100.00
CONT_ASSIGN	1753	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1758	1	1	100.00
CONT_ASSIGN	1760	1	1	100.00
CONT_ASSIGN	1761	1	1	100.00
CONT_ASSIGN	1763	1	1	100.00
CONT_ASSIGN	1765	1	1	100.00
CONT_ASSIGN	1766	1	1	100.00
CONT_ASSIGN	1768	1	1	100.00
CONT_ASSIGN	1770	1	1	100.00
CONT_ASSIGN	1772	1	1	100.00
CONT_ASSIGN	1774	1	1	100.00
CONT_ASSIGN	1776	1	1	100.00
CONT_ASSIGN	1777	1	1	100.00
CONT_ASSIGN	1778	1	1	100.00
CONT_ASSIGN	1779	1	1	100.00
CONT_ASSIGN	1780	1	1	100.00
CONT_ASSIGN	1782	1	1	100.00
CONT_ASSIGN	1784	1	1	100.00
CONT_ASSIGN	1786	1	1	100.00
CONT_ASSIGN	1787	1	1	100.00
CONT_ASSIGN	1789	1	1	100.00
CONT_ASSIGN	1790	1	1	100.00
CONT_ASSIGN	1792	1	1	100.00
CONT_ASSIGN	1793	1	1	100.00
CONT_ASSIGN	1795	1	1	100.00
CONT_ASSIGN	1796	1	1	100.00
CONT_ASSIGN	1797	1	1	100.00
CONT_ASSIGN	1798	1	1	100.00
CONT_ASSIGN	1800	1	1	100.00
CONT_ASSIGN	1801	1	1	100.00
CONT_ASSIGN	1803	1	1	100.00
CONT_ASSIGN	1805	1	1	100.00
CONT_ASSIGN	1806	1	1	100.00
CONT_ASSIGN	1808	1	1	100.00
CONT_ASSIGN	1809	1	1	100.00
CONT_ASSIGN	1811	1	1	100.00
CONT_ASSIGN	1812	1	1	100.00
CONT_ASSIGN	1814	1	1	100.00
CONT_ASSIGN	1815	1	1	100.00
CONT_ASSIGN	1817	1	1	100.00
CONT_ASSIGN	1818	1	1	100.00
CONT_ASSIGN	1820	1	1	100.00
CONT_ASSIGN	1821	1	1	100.00
CONT_ASSIGN	1823	1	1	100.00
CONT_ASSIGN	1824	1	1	100.00
CONT_ASSIGN	1826	1	1	100.00
CONT_ASSIGN	1827	1	1	100.00
CONT_ASSIGN	1828	1	1	100.00
CONT_ASSIGN	1829	1	1	100.00
CONT_ASSIGN	1830	1	1	100.00
CONT_ASSIGN	1831	1	1	100.00
CONT_ASSIGN	1832	1	1	100.00
CONT_ASSIGN	1833	1	1	100.00
CONT_ASSIGN	1834	1	1	100.00
CONT_ASSIGN	1835	1	1	100.00
CONT_ASSIGN	1836	1	1	100.00
CONT_ASSIGN	1837	1	1	100.00
CONT_ASSIGN	1838	1	1	100.00
CONT_ASSIGN	1839	1	1	100.00
CONT_ASSIGN	1840	1	1	100.00
ALWAYS	1844	37	37	100.00
ALWAYS	1885	73	73	100.00
CONT_ASSIGN	2077	0	0
CONT_ASSIGN	2085	1	1	100.00
CONT_ASSIGN	2086	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
76	1	1
77	1	1
78	1	1
79	1	1
			MISSING_ELSE
85	1	1
103	1	1
104	1	1
106	1	1
107	1	1
133	1	1
139	1	1
140	1	1
			MISSING_ELSE
170	1	1
171	1	1
415	1	1
430	1	1
446	1	1
452	1	1
467	1	1
483	1	1
499	1	1
515	1	1
531	1	1
963	1	1
966	1	1
981	1	1
997	1	1
1013	1	1
1019	1	1
1051	1	1
1083	1	1
1176	1	1
1179	1	1
1194	1	1
1210	1	1
1244	1	1
1275	1	1
1306	1	1
1337	1	1
1368	1	1
1399	1	1
1668	1	1
1669	1	1
1670	1	1
1671	1	1
1672	1	1
1673	1	1
1674	1	1
1675	1	1
1676	1	1
1677	1	1
1678	1	1
1679	1	1
1680	1	1
1681	1	1
1682	1	1
1683	1	1
1684	1	1
1685	1	1
1686	1	1
1687	1	1
1688	1	1
1689	1	1
1690	1	1
1691	1	1
1692	1	1
1693	1	1
1694	1	1
1695	1	1
1696	1	1
1697	1	1
1698	1	1
1699	1	1
1700	1	1
1701	1	1
1702	1	1
1703	1	1
1704	1	1
1707	1	1
1711	1	1
1751	1	1
1753	1	1
1755	1	1
1756	1	1
1758	1	1
1760	1	1
1761	1	1
1763	1	1
1765	1	1
1766	1	1
1768	1	1
1770	1	1
1772	1	1
1774	1	1
1776	1	1
1777	1	1
1778	1	1
1779	1	1
1780	1	1
1782	1	1
1784	1	1
1786	1	1
1787	1	1
1789	1	1
1790	1	1
1792	1	1
1793	1	1
1795	1	1
1796	1	1
1797	1	1
1798	1	1
1800	1	1
1801	1	1
1803	1	1
1805	1	1
1806	1	1
1808	1	1
1809	1	1
1811	1	1
1812	1	1
1814	1	1
1815	1	1
1817	1	1
1818	1	1
1820	1	1
1821	1	1
1823	1	1
1824	1	1
1826	1	1
1827	1	1
1828	1	1
1829	1	1
1830	1	1
1831	1	1
1832	1	1
1833	1	1
1834	1	1
1835	1	1
1836	1	1
1837	1	1
1838	1	1
1839	1	1
1840	1	1
1844	1	1
1845	1	1
1846	1	1
1847	1	1
1848	1	1
1849	1	1
1850	1	1
1851	1	1
1852	1	1
1853	1	1
1854	1	1
1855	1	1
1856	1	1
1857	1	1
1858	1	1
1859	1	1
1860	1	1
1861	1	1
1862	1	1
1863	1	1
1864	1	1
1865	1	1
1866	1	1
1867	1	1
1868	1	1
1869	1	1
1870	1	1
1871	1	1
1872	1	1
1873	1	1
1874	1	1
1875	1	1
1876	1	1
1877	1	1
1878	1	1
1879	1	1
1880	1	1
1885	1	1
1886	1	1
1888	1	1
1889	1	1
1893	1	1
1894	1	1
1898	1	1
1899	1	1
1903	1	1
1904	1	1
1905	1	1
1906	1	1
1907	1	1
1911	1	1
1912	1	1
1913	1	1
1914	1	1
1915	1	1
1916	1	1
1917	1	1
1918	1	1
1919	1	1
1920	1	1
1921	1	1
1922	1	1
1923	1	1
1924	1	1
1925	1	1
1926	1	1
1927	1	1
1931	1	1
1932	1	1
1933	1	1
1934	1	1
1935	1	1
1936	1	1
1937	1	1
1938	1	1
1939	1	1
1940	1	1
1944	1	1
1948	1	1
1949	1	1
1950	1	1
1954	1	1
1958	1	1
1962	1	1
1966	1	1
1970	1	1
1974	1	1
1978	1	1
1979	1	1
1983	1	1
1987	1	1
1991	1	1
1995	1	1
1999	1	1
2003	1	1
2007	1	1
2011	1	1
2015	1	1
2019	1	1
2023	1	1
2027	1	1
2031	1	1
2035	1	1
2039	1	1
2043	1	1
2047	1	1
2051	1	1
2055	1	1
2059	1	1
2063	1	1
2077		unreachable
2085	1	1
2086	1	1

---

Cond Coverage for Module : otp_ctrl_core_reg_top

	Total	Covered	Percent
Conditions	420	376	89.52
Logical	420	376	89.52
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T5,T11,T12

 LINE       85
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T5,T11,T12
1	0	0	Covered	T5,T11,T12

 LINE       133
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[4096:6143]}) ? 1'b0 : 1'b1)
             ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T4

 LINE       171
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T11,T12
0	1	0	Covered	T2,T6,T14
1	0	0	Covered	T2,T6,T4

 LINE       171
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T4

 LINE       966
 EXPRESSION (direct_access_cmd_we & direct_access_regwen_qs)
             ----------1---------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T31,T82,T81

 LINE       1019
 EXPRESSION (direct_access_address_we & direct_access_regwen_qs)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T82
1	1	Covered	T3,T4,T5

 LINE       1051
 EXPRESSION (direct_access_wdata_0_we & direct_access_regwen_qs)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T82,T81
1	1	Covered	T3,T4,T5

 LINE       1083
 EXPRESSION (direct_access_wdata_1_we & direct_access_regwen_qs)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       1179
 EXPRESSION (check_trigger_we & check_trigger_regwen_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T5
1	1	Covered	T4,T5,T13

 LINE       1244
 EXPRESSION (check_timeout_we & check_regwen_qs)
             --------1-------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1275
 EXPRESSION (integrity_check_period_we & check_regwen_qs)
             ------------1------------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T5
1	1	Covered	T3,T4,T5

 LINE       1306
 EXPRESSION (consistency_check_period_we & check_regwen_qs)
             -------------1-------------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T5
1	1	Covered	T3,T4,T5

 LINE       1337
 EXPRESSION (vendor_test_read_lock_we & direct_access_regwen_qs)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T82
1	1	Covered	T31,T81,T55

 LINE       1368
 EXPRESSION (creator_sw_cfg_read_lock_we & direct_access_regwen_qs)
             -------------1-------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T31,T82,T81

 LINE       1399
 EXPRESSION (owner_sw_cfg_read_lock_we & direct_access_regwen_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T31,T82,T81

 LINE       1669
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1670
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1671
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1672
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1673
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1674
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1675
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1676
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1677
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1678
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1679
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1680
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1681
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1682
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1683
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1684
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1685
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1686
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1687
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1688
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1689
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1690
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1691
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1692
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1693
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1694
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1695
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1696
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1697
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1698
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1699
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1700
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1701
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1702
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1703
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1704
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       1707
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1707
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       1711
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
36 (addr_hit[35] & ((|(4'...	Covered	T2,T6,T4
35 (addr_hit[34] & ((|(4'...	Covered	T2,T6,T14
34 (addr_hit[33] & ((|(4'...	Covered	T2,T6,T4
33 (addr_hit[32] & ((|(4'...	Covered	T2,T6,T14
32 (addr_hit[31] & ((|(4'...	Covered	T2,T6,T4
31 (addr_hit[30] & ((|(4'...	Covered	T2,T6,T14
30 (addr_hit[29] & ((|(4'...	Covered	T2,T6,T14
29 (addr_hit[28] & ((|(4'...	Covered	T2,T6,T14
28 (addr_hit[27] & ((|(4'...	Covered	T2,T6,T14
27 (addr_hit[26] & ((|(4'...	Covered	T2,T6,T14
26 (addr_hit[25] & ((|(4'...	Covered	T2,T6,T14
25 (addr_hit[24] & ((|(4'...	Covered	T2,T6,T4
24 (addr_hit[23] & ((|(4'...	Covered	T2,T6,T14
23 (addr_hit[22] & ((|(4'...	Covered	T2,T6,T14
22 (addr_hit[21] & ((|(4'...	Covered	T2,T6,T4
21 (addr_hit[20] & ((|(4'...	Covered	T2,T6,T14
20 (addr_hit[19] & ((|(4'...	Covered	T2,T6,T14
19 (addr_hit[18] & ((|(4'...	Covered	T2,T6,T14
18 (addr_hit[17] & ((|(4'...	Covered	T2,T6,T4
17 (addr_hit[16] & ((|(4'...	Covered	T2,T6,T4
16 (addr_hit[15] & ((|(4'...	Covered	T2,T6,T14
15 (addr_hit[14] & ((|(4'...	Covered	T2,T6,T4
14 (addr_hit[13] & ((|(4'...	Covered	T2,T6,T4
13 (addr_hit[12] & ((|(4'...	Covered	T2,T6,T4
12 (addr_hit[11] & ((|(4'...	Covered	T2,T6,T4
11 (addr_hit[10] & ((|(4'...	Covered	T2,T6,T14
10 (addr_hit[9] & ((|(4'b...	Covered	T2,T6,T14
9 (addr_hit[8] & ((|(4'b...	Covered	T2,T6,T4
8 (addr_hit[7] & ((|(4'b...	Covered	T2,T6,T4
7 (addr_hit[6] & ((|(4'b...	Covered	T2,T6,T4
6 (addr_hit[5] & ((|(4'b...	Covered	T2,T6,T4
5 (addr_hit[4] & ((|(4'b...	Covered	T2,T6,T14
4 (addr_hit[3] & ((|(4'b...	Covered	T2,T6,T4
3 (addr_hit[2] & ((|(4'b...	Covered	T1,T2,T7
2 (addr_hit[1] & ((|(4'b...	Covered	T1,T2,T7
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T3

 LINE       1711
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       1711
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

 LINE       1711
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

 LINE       1711
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T4
1	1	Covered	T2,T6,T4

 LINE       1711
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T6,T4

 LINE       1711
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T6,T4

 LINE       1711
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T16,T13
1	1	Covered	T2,T6,T4

 LINE       1711
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T4
1	1	Covered	T2,T6,T4

 LINE       1711
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T14
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T2,T6,T4

 LINE       1711
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T14
1	1	Covered	T2,T6,T4

 LINE       1711
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T6,T4

 LINE       1711
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T6,T4

 LINE       1711
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T13
1	1	Covered	T2,T6,T4

 LINE       1711
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T2,T6,T4

 LINE       1711
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T5
1	1	Covered	T2,T6,T4

 LINE       1711
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T14
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T6,T4

 LINE       1711
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T4
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T4
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T4
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T6,T4

 LINE       1711
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T4
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T6,T4

 LINE       1711
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T6,T14

 LINE       1711
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T6,T4

 LINE       1751
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T6,T14
1	1	1	Covered	T1,T7,T15

 LINE       1756
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T6,T13
1	1	1	Covered	T1,T3,T7

 LINE       1761
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T14,T13,T17
1	1	1	Covered	T1,T7,T15

 LINE       1766
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T14,T16,T13
1	1	1	Covered	T3,T4,T8

 LINE       1777
 EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1778
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1779
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T13,T18

 LINE       1780
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T6,T16
1	1	1	Covered	T31,T82,T81

 LINE       1787
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T13,T80,T83
1	1	1	Covered	T3,T4,T5

 LINE       1790
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T6,T13
1	1	1	Covered	T3,T4,T5

 LINE       1793
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T14,T13
1	1	1	Covered	T3,T4,T5

 LINE       1796
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T8

 LINE       1797
 EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T8

 LINE       1798
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T6,T16
1	1	1	Covered	T3,T4,T8

 LINE       1801
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T19,T83
1	1	1	Covered	T3,T4,T8

 LINE       1806
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T16,T17
1	1	1	Covered	T3,T4,T8

 LINE       1809
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T6,T14
1	1	1	Not Covered

 LINE       1812
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T14,T49
1	1	1	Covered	T3,T4,T8

 LINE       1815
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T6,T16
1	1	1	Covered	T3,T4,T8

 LINE       1818
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T6,T13
1	1	1	Covered	T31,T82,T81

 LINE       1821
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T14,T16
1	1	1	Covered	T31,T82,T81

 LINE       1824
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T14,T19
1	1	1	Covered	T31,T82,T81

 LINE       1827
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1828
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1829
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1830
 EXPRESSION (addr_hit[25] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1831
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1832
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1833
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1834
 EXPRESSION (addr_hit[29] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1835
 EXPRESSION (addr_hit[30] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1836
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1837
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1838
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1839
 EXPRESSION (addr_hit[34] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1840
 EXPRESSION (addr_hit[35] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Not Covered

---

Branch Coverage for Module : otp_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
Branches		46	46	100.00
TERNARY	1707	2	2	100.00
IF	76	3	3	100.00
TERNARY	133	2	2	100.00
IF	139	2	2	100.00
CASE	1886	37	37	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1707	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T11,T12
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	133	((tl_i.a_address[(AW - 1):0] inside {[4096:6143]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	139	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1886	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_core_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2922894	37108	0	0
reAfterRv	2922894	37108	0	0
rePulse	2922894	16380	0	0
wePulse	2922894	20728	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	37108	0	0
T1	3665	22	0	0
T2	14344	59	0	0
T3	9951	501	0	0
T4	6884	60	0	0
T6	18742	45	0	0
T7	3762	40	0	0
T8	22197	1153	0	0
T9	3890	22	0	0
T14	12905	37	0	0
T15	3432	20	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	37108	0	0
T1	3665	22	0	0
T2	14344	59	0	0
T3	9951	501	0	0
T4	6884	60	0	0
T6	18742	45	0	0
T7	3762	40	0	0
T8	22197	1153	0	0
T9	3890	22	0	0
T14	12905	37	0	0
T15	3432	20	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	16380	0	0
T1	3665	11	0	0
T2	14344	3	0	0
T3	9951	176	0	0
T4	6884	30	0	0
T6	18742	10	0	0
T7	3762	20	0	0
T8	22197	577	0	0
T9	3890	11	0	0
T14	12905	4	0	0
T15	3432	10	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922894	20728	0	0
T1	3665	11	0	0
T2	14344	56	0	0
T3	9951	325	0	0
T4	6884	30	0	0
T6	18742	35	0	0
T7	3762	20	0	0
T8	22197	576	0	0
T9	3890	11	0	0
T14	12905	33	0	0
T15	3432	10	0	0