OTP_CTRL Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: `671f2b57e2`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.780s	147.931us	1	1	100.00
V1	smoke	otp_ctrl_smoke	11.620s	4.512ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.360s	290.413us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.990s	513.356us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.060s	1.029ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	3.530s	1.122ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.580s	273.657us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.990s	513.356us	20	20	100.00
		otp_ctrl_csr_aliasing	3.530s	1.122ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.600s	506.220us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.890s	509.403us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	17.160s	1.288ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.270s	2.635ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	28.880s	3.452ms	10	10	100.00
		otp_ctrl_check_fail	29.800s	10.895ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	11.650s	3.815ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	30.350s	10.265ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	29.750s	10.721ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	23.940s	8.544ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	13.650s	5.651ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	23.320s	7.201ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	29.530s	3.688ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	42.390s	8.320ms	49	50	98.00
V2	stress_all	otp_ctrl_stress_all	3.445m	26.282ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.220s	546.271us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.500s	978.860us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.590s	2.288ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.590s	2.288ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.360s	290.413us	5	5	100.00
		otp_ctrl_csr_rw	1.990s	513.356us	20	20	100.00
		otp_ctrl_csr_aliasing	3.530s	1.122ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.000s	1.428ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.360s	290.413us	5	5	100.00
		otp_ctrl_csr_rw	1.990s	513.356us	20	20	100.00
		otp_ctrl_csr_aliasing	3.530s	1.122ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.000s	1.428ms	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
		otp_ctrl_tl_intg_err	36.930s	19.083ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	36.930s	19.083ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	11.620s	4.512ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	11.620s	4.512ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.650s	5.651ms	200	200	100.00
		otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.650s	5.651ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.650s	5.651ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.650s	5.651ms	200	200	100.00
		otp_ctrl_macro_errs	29.530s	3.688ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.650s	5.651ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.650s	5.651ms	200	200	100.00
		otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.650s	5.651ms	200	200	100.00
		otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.650s	5.651ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.650s	5.651ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.650s	5.651ms	200	200	100.00
		otp_ctrl_macro_errs	29.530s	3.688ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.650s	5.651ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.650s	5.651ms	200	200	100.00
		otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.270s	2.635ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	29.800s	10.895ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	30.350s	10.265ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	30.350s	10.265ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	30.350s	10.265ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	30.350s	10.265ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	30.350s	10.265ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	11.620s	4.512ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	30.350s	10.265ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	11.620s	4.512ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.301m	131.472ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	11.650s	3.815ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	11.620s	4.512ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	11.620s	4.512ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	29.530s	3.688ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.360s	3.428ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.980h	1.749s	91	100	91.00
V3		TOTAL			92	101	91.09
		TOTAL			1333	1343	99.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.63	92.61	91.57	92.42	93.52	93.49	96.53	95.27

Failure Buckets

Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 30.otp_ctrl_stress_all_with_rand_reset.15980594679651203468367138709325025301802844434866513321903435911325922940322
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8667a4f5-5a6a-4473-8526-2d91af734de7
```
  - 43.otp_ctrl_stress_all_with_rand_reset.103264187366945041428967531684173262705469709435940750257096474997310058508820
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:2e707233-6a36-450b-a717-2aca661ee4ac
```
  - ... and 2 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@32218483) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 24.otp_ctrl_stress_all_with_rand_reset.9864845191604701677342832468756816005732052532082024427318293624154148609286
    Line 1495, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 802447937086 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@32218483) { a_addr: 'hb006c58  a_data: 'h7414c47  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hfd  a_opcode: 'h1  a_user: 'h27c70  d_param: 'h0  d_source: 'hfd  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 802447937086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 25.otp_ctrl_stress_all_with_rand_reset.37423722015715159643459277662686345672306953860535870051317950627695932787661
    Line 1215, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 777953197967 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 777953197967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@71390) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_test_access has 1 failures.

28.otp_ctrl_test_access.64185359888253409482278216332452681764002374412515270547260889476888915193658
Line 265, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest/run.log

  UVM_ERROR @ 190226984 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@71390) { a_addr: 'h4885c6a0  a_data: 'h21e2fc9f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h42  a_opcode: 'h0  a_user: 'h24bed  d_param: 'h0  d_source: 'h42  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 190226984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 31.otp_ctrl_stress_all_with_rand_reset.89937112895301038587196175157027637553219561673169343743255384043560905945833
    Line 926, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 119865183299 ps: (otp_ctrl_if.sv:262) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 119865183299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@12120611) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 33.otp_ctrl_stress_all_with_rand_reset.5279944135573859143898550745738682399492670885891560051663885867319769835066
    Line 748, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 581796967366 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@12120611) { a_addr: 'hfde57f4  a_data: 'hff5f0bd1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hdf  a_opcode: 'h0  a_user: 'h279c4  d_param: 'h0  d_source: 'hdf  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 581796967366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@15619748) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 82.otp_ctrl_stress_all_with_rand_reset.55013673096272377700237592584803635105931286987878551311346350113200290323726
    Line 888, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 180480725812 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@15619748) { a_addr: 'h73f354f4  a_data: 'h45631b1a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc5  a_opcode: 'h1  a_user: 'h24c81  d_param: 'h0  d_source: 'hc5  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 180480725812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```