Unified Coverage Report :: Module :: prim_generic_otp

Module : prim_generic_otp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.39	96.91	95.45		100.00	94.59	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp.gen_generic.u_impl_generic	97.39	96.91	95.45		100.00	94.59	100.00

---

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.39	96.91	95.45		100.00	94.59	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.17	91.72	94.58	100.00	100.00	90.71	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_otp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_dec	100.00	100.00	100.00
u_enc	100.00	100.00
u_prim_ram_1p_adv	99.58	98.31	100.00			100.00	100.00
u_reg_top	94.50	89.51	93.19	100.00		89.82	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_otp

	Line No.	Total	Covered	Percent
TOTAL		97	94	96.91
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	78	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
ALWAYS	178	60	60	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	329	1	1	100.00
ALWAYS	333	0	0
ALWAYS	333	3	3	100.00
ALWAYS	366	3	3	100.00
ALWAYS	369	17	17	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
74	1	1
78	0	1
82	0	1
84	0	1
87	1	1
90	1	1
114	1	1
170	1	1
173	1	1
174	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
189	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
			==> MISSING_ELSE
			MISSING_ELSE
202	1	1
203	1	1
204	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
			MISSING_ELSE
222	1	1
223	1	1
227	1	1
228	1	1
230	1	1
231	1	1
232	1	1
233	1	1
235	1	1
236	1	1
237	1	1
239	1	1
242	1	1
243	1	1
			MISSING_ELSE
			MISSING_ELSE
251	1	1
252	1	1
254	1	1
259	1	1
260	1	1
261	1	1
263	1	1
264	1	1
265	1	1
267	1	1
			MISSING_ELSE
274	1	1
275	1	1
276	1	1
277	1	1
278	1	1
			MISSING_ELSE
281	1	1
282	1	1
283	1	1
			MISSING_ELSE
288	1	1
302	1	1
322	1	1
326	1	1
329	1	1
333	1	1
334	1	1
336	1	1
366	3	3
369	1	1
370	1	1
371	1	1
372	1	1
373	1	1
374	1	1
375	1	1
376	1	1
378	1	1
379	1	1
380	1	1
381	1	1
382	1	1
383	1	1
384	1	1
			MISSING_ELSE
386	1	1
387	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_generic_otp

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       90
 EXPRESSION (intg_err || fsm_err)
             ----1---    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T21,T22,T23

 LINE       170
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       170
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (cmd_i == Init)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       235
 EXPRESSION (cnt_q == size_q)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       263
 EXPRESSION (cnt_q == size_q)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       281
 EXPRESSION (cnt_q == size_q)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       322
 EXPRESSION (read_ecc_on ? ({{EccWidth {1'b0}}, rdata_corr}) : rdata_ecc)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       329
 EXPRESSION ((rdata_q[cnt_q] & wdata_ecc) != rdata_q[cnt_q])
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       381
 EXPRESSION (ready_o && valid_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : prim_generic_otp

Summary for FSM :: state_q

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	11	11	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	287	Covered	T18
IdleSt	202	Covered	T18
InitSt	196	Covered	T18
ReadSt	214	Covered	T18
ReadWaitSt	222	Covered	T18
ResetSt	191	Covered	T18
WriteCheckSt	215	Covered	T18
WriteSt	265	Covered	T18
WriteWaitSt	251	Covered	T18

transitions	Line No.	Covered	Tests
IdleSt->ReadSt	214	Covered	T18
IdleSt->WriteCheckSt	215	Covered	T18
InitSt->IdleSt	202	Covered	T18
ReadSt->ReadWaitSt	222	Covered	T18
ReadWaitSt->IdleSt	231	Covered	T18
ReadWaitSt->ReadSt	239	Covered	T18
ResetSt->InitSt	196	Covered	T18
WriteCheckSt->WriteWaitSt	251	Covered	T18
WriteSt->IdleSt	283	Covered	T18
WriteWaitSt->WriteCheckSt	267	Covered	T18
WriteWaitSt->WriteSt	265	Covered	T18

---

Branch Coverage for Module : prim_generic_otp

	Line No.	Total	Covered	Percent
Branches		37	35	94.59
TERNARY	170	3	3	100.00
TERNARY	322	2	2	100.00
CASE	189	25	23	92.00
IF	366	2	2	100.00
IF	369	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	170	(cnt_clr) ? 
-2-:	170	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	322	(read_ecc_on) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	189	case (state_q)
-2-:	194	if (valid_i)
-3-:	195	if ((cmd_i == Init))
-4-:	210	if (valid_i)
-5-:	213	case (cmd_i)
-6-:	227	if (rvalid)
-7-:	230	if (rerror[1])
-8-:	235	if ((cnt_q == size_q))
-9-:	242	if (rerror[0])
-10-:	260	if (rvalid)
-11-:	263	if ((cnt_q == size_q))
-12-:	277	if (wdata_inconsistent)
-13-:	281	if ((cnt_q == size_q))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	1	Read	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	1	Write	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	1	default	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T7
ReadWaitSt	-	-	-	-	1	0	1	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	1	0	0	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	1	0	-	1	-	-	-	-	Covered	T1,T7,T8
ReadWaitSt	-	-	-	-	1	0	-	0	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
WriteCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
WriteWaitSt	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T2,T3
WriteWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T2,T3
WriteWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
WriteSt	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T11
WriteSt	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
WriteSt	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
WriteSt	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	366	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))
-2-:	381	if ((ready_o && valid_i))
-3-:	386	if (rvalid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_otp

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckCommands0_A	2147483647	12081	0	0
CheckCommands1_A	2147483647	1335450	0	0
NoWrapArounds_A	2147483647	4077281	0	0
SecDecWidth_A	1162	1162	0	0
u_state_regs_A	2147483647	2147483647	0	0

CheckCommands0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12081	0	0
T1	587785	164	0	0
T2	17442	4	0	0
T3	23828	8	0	0
T4	194089	6	0	0
T6	35565	13	0	0
T7	16003	3	0	0
T8	10666	3	0	0
T9	14511	3	0	0
T10	203241	17	0	0
T11	431689	13	0	0

CheckCommands1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1335450	0	0
T1	587785	13430	0	0
T2	17442	200	0	0
T3	23828	470	0	0
T4	194089	1626	0	0
T6	35565	1789	0	0
T7	16003	205	0	0
T8	10666	108	0	0
T9	14511	218	0	0
T10	203241	1484	0	0
T11	431689	7974	0	0

NoWrapArounds_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4077281	0	0
T1	587785	44286	0	0
T2	17442	823	0	0
T3	23828	1787	0	0
T4	194089	4246	0	0
T6	35565	4532	0	0
T7	16003	805	0	0
T8	10666	413	0	0
T9	14511	825	0	0
T10	203241	4625	0	0
T11	431689	19556	0	0

SecDecWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162	1162	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	587785	575298	0	0
T2	17442	17181	0	0
T3	23828	23338	0	0
T4	194089	194080	0	0
T6	35565	34615	0	0
T7	16003	15750	0	0
T8	10666	10370	0	0
T9	14511	14247	0	0
T10	203241	201894	0	0
T11	431689	431686	0	0