Unified Coverage Report :: Module :: otp_ctrl_prim_reg_top

Module : otp_ctrl_prim_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	97.03			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top	99.26	100.00	97.03			100.00	100.00

---

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	97.03			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.50	89.51	93.19	100.00		89.82	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	96.91	95.45		100.00	94.59	100.00	gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_chk	100.00	100.00		100.00			100.00
u_csr0_field0	100.00	100.00	100.00			100.00
u_csr0_field1	100.00	100.00	100.00			100.00
u_csr0_field2	100.00	100.00	100.00			100.00
u_csr0_field3	100.00	100.00	100.00			100.00
u_csr0_field4	100.00	100.00	100.00			100.00
u_csr1_field0	100.00	100.00	100.00			100.00
u_csr1_field1	100.00	100.00	100.00			100.00
u_csr1_field2	100.00	100.00	100.00			100.00
u_csr1_field3	100.00	100.00	100.00			100.00
u_csr1_field4	100.00	100.00	100.00			100.00
u_csr2	100.00	100.00	100.00			100.00
u_csr3_field0	93.33	100.00	80.00			100.00
u_csr3_field1	93.33	100.00	80.00			100.00
u_csr3_field2	88.89	100.00	66.67			100.00
u_csr3_field3	55.19	55.56	50.00			60.00
u_csr3_field4	55.19	55.56	50.00			60.00
u_csr3_field5	55.19	55.56	50.00			60.00
u_csr3_field6	55.19	55.56	50.00			60.00
u_csr3_field7	55.19	55.56	50.00			60.00
u_csr3_field8	55.19	55.56	50.00			60.00
u_csr4_field0	100.00	100.00	100.00			100.00
u_csr4_field1	100.00	100.00	100.00			100.00
u_csr4_field2	100.00	100.00	100.00			100.00
u_csr4_field3	100.00	100.00	100.00			100.00
u_csr5_field0	96.30	100.00	88.89			100.00
u_csr5_field1	96.30	100.00	88.89			100.00
u_csr5_field2	55.19	55.56	50.00			60.00
u_csr5_field3	55.19	55.56	50.00			60.00
u_csr5_field4	55.19	55.56	50.00			60.00
u_csr5_field5	55.19	55.56	50.00			60.00
u_csr5_field6	96.30	100.00	88.89			100.00
u_csr6_field0	100.00	100.00	100.00			100.00
u_csr6_field1	100.00	100.00	100.00			100.00
u_csr6_field2	100.00	100.00	100.00			100.00
u_csr6_field3	100.00	100.00	100.00			100.00
u_csr7_field0	55.19	55.56	50.00			60.00
u_csr7_field1	55.19	55.56	50.00			60.00
u_csr7_field2	55.19	55.56	50.00			60.00
u_csr7_field3	55.19	55.56	50.00			60.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : otp_ctrl_prim_reg_top

	Line No.	Total	Covered	Percent
TOTAL		104	104	100.00
ALWAYS	71	4	4	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
ALWAYS	1271	9	9	100.00
CONT_ASSIGN	1282	1	1	100.00
ALWAYS	1286	1	1	100.00
CONT_ASSIGN	1298	1	1	100.00
CONT_ASSIGN	1300	1	1	100.00
CONT_ASSIGN	1302	1	1	100.00
CONT_ASSIGN	1304	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1308	1	1	100.00
CONT_ASSIGN	1309	1	1	100.00
CONT_ASSIGN	1311	1	1	100.00
CONT_ASSIGN	1313	1	1	100.00
CONT_ASSIGN	1315	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1319	1	1	100.00
CONT_ASSIGN	1320	1	1	100.00
CONT_ASSIGN	1322	1	1	100.00
CONT_ASSIGN	1323	1	1	100.00
CONT_ASSIGN	1325	1	1	100.00
CONT_ASSIGN	1327	1	1	100.00
CONT_ASSIGN	1329	1	1	100.00
CONT_ASSIGN	1330	1	1	100.00
CONT_ASSIGN	1332	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1336	1	1	100.00
CONT_ASSIGN	1338	1	1	100.00
CONT_ASSIGN	1339	1	1	100.00
CONT_ASSIGN	1341	1	1	100.00
CONT_ASSIGN	1343	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1346	1	1	100.00
CONT_ASSIGN	1348	1	1	100.00
CONT_ASSIGN	1350	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
CONT_ASSIGN	1354	1	1	100.00
ALWAYS	1358	9	9	100.00
ALWAYS	1371	41	41	100.00
CONT_ASSIGN	1447	0	0
CONT_ASSIGN	1455	1	1	100.00
CONT_ASSIGN	1456	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
80	1	1
92	1	1
93	1	1
121	1	1
122	1	1
1271	1	1
1272	1	1
1273	1	1
1274	1	1
1275	1	1
1276	1	1
1277	1	1
1278	1	1
1279	1	1
1282	1	1
1286	1	1
1298	1	1
1300	1	1
1302	1	1
1304	1	1
1306	1	1
1308	1	1
1309	1	1
1311	1	1
1313	1	1
1315	1	1
1317	1	1
1319	1	1
1320	1	1
1322	1	1
1323	1	1
1325	1	1
1327	1	1
1329	1	1
1330	1	1
1332	1	1
1334	1	1
1336	1	1
1338	1	1
1339	1	1
1341	1	1
1343	1	1
1345	1	1
1346	1	1
1348	1	1
1350	1	1
1352	1	1
1354	1	1
1358	1	1
1359	1	1
1360	1	1
1361	1	1
1362	1	1
1363	1	1
1364	1	1
1365	1	1
1366	1	1
1371	1	1
1372	1	1
1374	1	1
1375	1	1
1376	1	1
1377	1	1
1378	1	1
1382	1	1
1383	1	1
1384	1	1
1385	1	1
1386	1	1
1390	1	1
1394	1	1
1395	1	1
1396	1	1
1397	1	1
1398	1	1
1399	1	1
1400	1	1
1401	1	1
1402	1	1
1406	1	1
1407	1	1
1408	1	1
1409	1	1
1413	1	1
1414	1	1
1415	1	1
1416	1	1
1417	1	1
1418	1	1
1419	1	1
1423	1	1
1424	1	1
1425	1	1
1426	1	1
1430	1	1
1431	1	1
1432	1	1
1433	1	1
1447		unreachable
1455	1	1
1456	1	1

---

Cond Coverage for Module : otp_ctrl_prim_reg_top

	Total	Covered	Percent
Conditions	101	98	97.03
Logical	101	98	97.03
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T18,T97,T98
1	0	Not Covered
1	1	Covered	T18,T97,T98

 LINE       73
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T97,T98
0	1	Covered	T21,T22,T23
1	0	Covered	T105,T176,T177

 LINE       80
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T18,T97,T98
0	0	1	Covered	T21,T22,T23
0	1	0	Covered	T105,T176,T177
1	0	0	Covered	T105,T176,T177

 LINE       122
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T18,T97,T98
0	0	1	Covered	T105,T176,T177
0	1	0	Covered	T18,T154,T155
1	0	0	Not Covered

 LINE       122
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T18,T97,T98
1	1	Not Covered

 LINE       1272
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR0_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T18,T97,T98
1	Covered	T18,T97,T98

 LINE       1273
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR1_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T18,T97,T98
1	Covered	T18,T97,T98

 LINE       1274
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR2_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T18,T97,T98
1	Covered	T18,T97,T98

 LINE       1275
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR3_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T18,T97,T98
1	Covered	T18,T97,T98

 LINE       1276
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR4_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T18,T97,T98
1	Covered	T18,T97,T98

 LINE       1277
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR5_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T18,T97,T98
1	Covered	T18,T97,T98

 LINE       1278
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR6_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T18,T97,T98
1	Covered	T18,T97,T98

 LINE       1279
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR7_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T18,T97,T98
1	Covered	T18,T97,T98

 LINE       1282
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T18,T97,T98
1	Covered	T18,T97,T98

 LINE       1282
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T18,T97,T98
0	1	Covered	T18,T97,T98
1	0	Covered	T97,T98,T99

 LINE       1286
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T18,T97,T98
1	0	Covered	T97,T98,T99
1	1	Covered	T18,T105,T154

 LINE       1286
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
0	0	0	0	0	0	0	0	Covered	T18,T97,T98
0	0	0	0	0	0	0	1	Covered	T18,T97,T98
0	0	0	0	0	0	1	0	Covered	T18,T97,T98
0	0	0	0	0	1	0	0	Covered	T18,T97,T98
0	0	0	0	1	0	0	0	Covered	T18,T97,T98
0	0	0	1	0	0	0	0	Covered	T18,T97,T98
0	0	1	0	0	0	0	0	Covered	T18,T97,T98
0	1	0	0	0	0	0	0	Covered	T18,T97,T98
1	0	0	0	0	0	0	0	Covered	T18,T97,T98

 LINE       1286
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T97,T98
1	0	Covered	T18,T97,T98
1	1	Covered	T18,T97,T98

 LINE       1286
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T97,T98
1	0	Covered	T18,T97,T98
1	1	Covered	T18,T97,T98

 LINE       1286
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T18,T97,T98
1	0	Covered	T18,T97,T98
1	1	Covered	T18,T97,T98

 LINE       1286
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T97,T98
1	0	Covered	T18,T97,T98
1	1	Covered	T18,T97,T98

 LINE       1286
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T97,T98
1	0	Covered	T18,T97,T98
1	1	Covered	T18,T97,T98

 LINE       1286
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T97,T98
1	0	Covered	T18,T97,T98
1	1	Covered	T18,T97,T98

 LINE       1286
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T97,T98
1	0	Covered	T18,T97,T98
1	1	Covered	T18,T97,T98

 LINE       1286
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T97,T98
1	0	Covered	T18,T97,T98
1	1	Covered	T18,T97,T98

 LINE       1298
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T97,T98,T99
1	0	1	Covered	T18,T97,T98
1	1	0	Covered	T105,T157,T158
1	1	1	Covered	T97,T98,T99

 LINE       1309
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T97,T98,T99
1	0	1	Covered	T18,T97,T98
1	1	0	Covered	T18,T154,T155
1	1	1	Covered	T97,T98,T99

 LINE       1320
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T97,T98,T99
1	0	1	Covered	T18,T97,T98
1	1	0	Covered	T18,T154,T156
1	1	1	Covered	T97,T98,T99

 LINE       1323
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T97,T98,T99
1	0	1	Covered	T18,T97,T98
1	1	0	Covered	T18,T154,T156
1	1	1	Covered	T97,T98,T99

 LINE       1330
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T97,T98,T99
1	0	1	Covered	T18,T97,T98
1	1	0	Covered	T18,T155,T157
1	1	1	Covered	T97,T98,T99

 LINE       1339
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T97,T98,T99
1	0	1	Covered	T18,T97,T98
1	1	0	Covered	T18,T105,T155
1	1	1	Covered	T97,T98,T99

 LINE       1346
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T97,T98,T99
1	0	1	Covered	T18,T97,T98
1	1	0	Covered	T18,T105,T154
1	1	1	Covered	T97,T98,T99

---

Branch Coverage for Module : otp_ctrl_prim_reg_top

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	1282	2	2	100.00
IF	71	3	3	100.00
CASE	1372	9	9	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1282	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T97,T98
0	Covered	T18,T97,T98

	LineNo.	Expression
-1-:	71	if ((!rst_ni))
-2-:	73	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T97,T98
0	1	Covered	T105,T176,T177
0	0	Covered	T18,T97,T98

	LineNo.	Expression
-1-:	1372	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T18,T97,T98
addr_hit[1]	Covered	T18,T97,T98
addr_hit[2]	Covered	T18,T97,T98
addr_hit[3]	Covered	T18,T97,T98
addr_hit[4]	Covered	T18,T97,T98
addr_hit[5]	Covered	T18,T97,T98
addr_hit[6]	Covered	T18,T97,T98
addr_hit[7]	Covered	T18,T97,T98
default	Covered	T18,T99,T104

---

Assert Coverage for Module : otp_ctrl_prim_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	250350	0	0
reAfterRv	2147483647	250350	0	0
rePulse	2147483647	26155	0	0
wePulse	2147483647	224195	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	250350	0	0
T18	7410	15	0	0
T97	4507	304	0	0
T98	3741	56	0	0
T99	6830	304	0	0
T100	3380	0	0	0
T101	3495	0	0	0
T102	3655	0	0	0
T103	3875	0	0	0
T104	8366	1023	0	0
T105	58468	333	0	0
T106	0	2048	0	0
T107	0	16	0	0
T154	0	52	0	0
T194	0	300	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	250350	0	0
T18	7410	15	0	0
T97	4507	304	0	0
T98	3741	56	0	0
T99	6830	304	0	0
T100	3380	0	0	0
T101	3495	0	0	0
T102	3655	0	0	0
T103	3875	0	0	0
T104	8366	1023	0	0
T105	58468	333	0	0
T106	0	2048	0	0
T107	0	16	0	0
T154	0	52	0	0
T194	0	300	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	26155	0	0
T97	4507	296	0	0
T98	3741	42	0	0
T99	6830	296	0	0
T100	3380	0	0	0
T101	3495	0	0	0
T102	3655	0	0	0
T103	3875	0	0	0
T104	8366	512	0	0
T105	58468	249	0	0
T106	43073	1024	0	0
T107	0	8	0	0
T154	0	38	0	0
T194	0	292	0	0
T206	0	43	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	224195	0	0
T18	7410	15	0	0
T97	4507	8	0	0
T98	3741	14	0	0
T99	6830	8	0	0
T100	3380	0	0	0
T101	3495	0	0	0
T102	3655	0	0	0
T103	3875	0	0	0
T104	8366	511	0	0
T105	58468	84	0	0
T106	0	1024	0	0
T107	0	8	0	0
T154	0	14	0	0
T194	0	8	0	0