Unified Coverage Report :: Module :: prim_lfsr

Module Definition

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Module : prim_lfsr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.70			74.70

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr	74.70			74.70
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr	74.70			74.70

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.70			74.70

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.70			74.70

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_double_lfsr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.70			74.70

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.70			74.70

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_double_lfsr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	124	74.70
Total Bits 0->1	83	62	74.70
Total Bits 1->0	83	62	74.70


Ports	5	4	80.00
Port Bits	166	124	74.70
Port Bits 0->1	83	62	74.70
Port Bits 1->0	83	62	74.70

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[0]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[2:1]	No	No		No		INPUT
entropy_i[7:3]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[9:8]	No	No		No		INPUT
entropy_i[12:10]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[15:13]	No	No		No		INPUT
entropy_i[18:16]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[21:19]	No	No		No		INPUT
entropy_i[23:22]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[26:24]	No	No		No		INPUT
entropy_i[28:27]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[29]	No	No		No		INPUT
entropy_i[30]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[32:31]	No	No		No		INPUT
entropy_i[34:33]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[39:35]	No	No		No		INPUT
state_o[39:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	124	74.70
Total Bits 0->1	83	62	74.70
Total Bits 1->0	83	62	74.70


Ports	5	4	80.00
Port Bits	166	124	74.70
Port Bits 0->1	83	62	74.70
Port Bits 1->0	83	62	74.70

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[0]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[2:1]	No	No		No		INPUT
entropy_i[7:3]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[9:8]	No	No		No		INPUT
entropy_i[12:10]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[15:13]	No	No		No		INPUT
entropy_i[18:16]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[21:19]	No	No		No		INPUT
entropy_i[23:22]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[26:24]	No	No		No		INPUT
entropy_i[28:27]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[29]	No	No		No		INPUT
entropy_i[30]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[32:31]	No	No		No		INPUT
entropy_i[34:33]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[39:35]	No	No		No		INPUT
state_o[39:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	124	74.70
Total Bits 0->1	83	62	74.70
Total Bits 1->0	83	62	74.70


Ports	5	4	80.00
Port Bits	166	124	74.70
Port Bits 0->1	83	62	74.70
Port Bits 1->0	83	62	74.70

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[0]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[2:1]	No	No		No		INPUT
entropy_i[7:3]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[9:8]	No	No		No		INPUT
entropy_i[12:10]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[15:13]	No	No		No		INPUT
entropy_i[18:16]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[21:19]	No	No		No		INPUT
entropy_i[23:22]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[26:24]	No	No		No		INPUT
entropy_i[28:27]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[29]	No	No		No		INPUT
entropy_i[30]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[32:31]	No	No		No		INPUT
entropy_i[34:33]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[39:35]	No	No		No		INPUT
state_o[39:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

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