Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 16514 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 33079 1 T1 327 T2 323 T3 329



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 19333 1 T1 115 T2 75 T3 119
values[0x0] 14435 1 T1 201 T2 119 T3 198
values[0x1] 15825 1 T1 178 T2 205 T3 183



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 12148 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 37445 1 T1 373 T2 368 T3 368



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 128 1 T1 2 T3 8 T11 2
valid_sources[0x01] 165 1 T1 4 T2 1 T3 7
valid_sources[0x02] 206 1 T1 1 T3 2 T11 2
valid_sources[0x03] 199 1 T1 1 T2 3 T3 3
valid_sources[0x04] 117 1 T1 1 T2 2 T3 2
valid_sources[0x05] 138 1 T1 4 T2 5 T3 2
valid_sources[0x06] 199 1 T1 4 T3 3 T11 2
valid_sources[0x07] 109 1 T2 1 T3 2 T4 3
valid_sources[0x08] 319 1 T1 2 T2 1 T3 4
valid_sources[0x09] 167 1 T1 4 T3 1 T11 2
valid_sources[0x0a] 170 1 T1 3 T3 1 T11 1
valid_sources[0x0b] 109 1 T1 1 T2 5 T11 2
valid_sources[0x0c] 144 1 T1 3 T2 1 T3 3
valid_sources[0x0d] 171 1 T1 3 T2 3 T3 1
valid_sources[0x0e] 189 1 T1 2 T2 4 T3 1
valid_sources[0x0f] 101 1 T1 2 T11 1 T12 2
valid_sources[0x10] 117 1 T1 3 T2 5 T3 4
valid_sources[0x11] 120 1 T1 2 T2 1 T3 4
valid_sources[0x12] 127 1 T1 3 T2 1 T3 1
valid_sources[0x13] 199 1 T1 5 T3 3 T11 3
valid_sources[0x14] 168 1 T1 2 T2 1 T11 1
valid_sources[0x15] 196 1 T1 2 T3 3 T11 1
valid_sources[0x16] 282 1 T1 1 T3 1 T11 3
valid_sources[0x17] 149 1 T1 2 T2 2 T3 6
valid_sources[0x18] 134 1 T1 2 T12 3 T14 5
valid_sources[0x19] 108 1 T2 2 T3 2 T4 3
valid_sources[0x1a] 530 1 T2 1 T3 3 T11 1
valid_sources[0x1b] 116 1 T1 4 T2 2 T3 3
valid_sources[0x1c] 413 1 T1 4 T2 2 T3 6
valid_sources[0x1d] 168 1 T1 3 T2 2 T3 1
valid_sources[0x1e] 166 1 T1 4 T2 1 T11 1
valid_sources[0x1f] 137 1 T1 5 T2 1 T3 1
valid_sources[0x20] 233 1 T1 2 T2 1 T11 2
valid_sources[0x21] 224 1 T1 1 T3 3 T11 1
valid_sources[0x22] 234 1 T1 2 T2 1 T11 1
valid_sources[0x23] 236 1 T1 3 T2 1 T3 2
valid_sources[0x24] 201 1 T1 1 T3 3 T5 24
valid_sources[0x25] 221 1 T1 1 T2 1 T3 1
valid_sources[0x26] 153 1 T1 1 T2 2 T3 2
valid_sources[0x27] 127 1 T1 3 T2 1 T3 5
valid_sources[0x28] 165 1 T1 1 T2 3 T3 1
valid_sources[0x29] 205 1 T1 1 T2 1 T3 7
valid_sources[0x2a] 250 1 T1 1 T3 1 T11 1
valid_sources[0x2b] 149 1 T1 3 T3 2 T11 2
valid_sources[0x2c] 154 1 T1 1 T2 2 T3 3
valid_sources[0x2d] 108 1 T1 1 T2 1 T4 2
valid_sources[0x2e] 216 1 T1 1 T2 4 T11 3
valid_sources[0x2f] 260 1 T1 2 T3 4 T11 2
valid_sources[0x30] 296 1 T1 4 T3 2 T11 3
valid_sources[0x31] 161 1 T1 1 T3 1 T11 5
valid_sources[0x32] 359 1 T1 2 T2 1 T3 1
valid_sources[0x33] 389 1 T1 1 T2 1 T3 2
valid_sources[0x34] 196 1 T1 2 T3 1 T4 1
valid_sources[0x35] 238 1 T1 1 T2 5 T4 2
valid_sources[0x36] 239 1 T1 2 T2 1 T11 3
valid_sources[0x37] 181 1 T1 1 T2 1 T11 1
valid_sources[0x38] 169 1 T1 3 T2 2 T3 4
valid_sources[0x39] 156 1 T1 1 T2 1 T3 3
valid_sources[0x3a] 203 1 T1 1 T3 3 T11 1
valid_sources[0x3b] 195 1 T1 5 T3 2 T11 3
valid_sources[0x3c] 261 1 T1 5 T2 1 T3 4
valid_sources[0x3d] 170 1 T2 1 T3 4 T11 5
valid_sources[0x3e] 205 1 T2 2 T3 4 T11 1
valid_sources[0x3f] 160 1 T1 1 T3 3 T11 3
valid_sources[0x40] 103 1 T1 2 T3 1 T11 3
valid_sources[0x41] 120 1 T2 3 T3 1 T11 4
valid_sources[0x42] 168 1 T1 1 T2 3 T3 1
valid_sources[0x43] 344 1 T2 1 T3 1 T11 4
valid_sources[0x44] 163 1 T1 2 T2 2 T3 9
valid_sources[0x45] 137 1 T1 4 T2 1 T11 3
valid_sources[0x46] 133 1 T11 2 T23 1 T22 1
valid_sources[0x47] 154 1 T1 1 T2 4 T3 1
valid_sources[0x48] 206 1 T2 2 T5 51 T11 3
valid_sources[0x49] 137 1 T1 3 T3 2 T11 1
valid_sources[0x4a] 130 1 T1 1 T2 3 T3 5
valid_sources[0x4b] 118 1 T1 1 T11 3 T12 2
valid_sources[0x4c] 135 1 T1 2 T11 2 T12 2
valid_sources[0x4d] 164 1 T1 2 T11 2 T12 2
valid_sources[0x4e] 174 1 T1 2 T2 1 T3 3
valid_sources[0x4f] 191 1 T1 2 T3 2 T4 1
valid_sources[0x50] 311 1 T2 1 T5 24 T11 1
valid_sources[0x51] 167 1 T1 2 T2 4 T3 3
valid_sources[0x52] 223 1 T1 3 T2 1 T3 1
valid_sources[0x53] 176 1 T1 1 T3 2 T12 1
valid_sources[0x54] 193 1 T1 2 T2 4 T11 1
valid_sources[0x55] 183 1 T2 3 T3 2 T11 1
valid_sources[0x56] 78 1 T2 3 T3 4 T14 1
valid_sources[0x57] 265 1 T3 5 T11 1 T12 1
valid_sources[0x58] 139 1 T2 1 T3 2 T11 3
valid_sources[0x59] 178 1 T1 4 T2 1 T3 2
valid_sources[0x5a] 130 1 T1 1 T3 2 T4 1
valid_sources[0x5b] 250 1 T1 2 T3 3 T11 3
valid_sources[0x5c] 151 1 T1 2 T2 3 T11 2
valid_sources[0x5d] 153 1 T1 2 T3 1 T11 1
valid_sources[0x5e] 166 1 T1 2 T2 3 T3 2
valid_sources[0x5f] 256 1 T1 5 T4 2 T11 2
valid_sources[0x60] 151 1 T1 1 T2 4 T3 2
valid_sources[0x61] 214 1 T1 5 T3 2 T11 4
valid_sources[0x62] 145 1 T3 1 T11 3 T12 1
valid_sources[0x63] 181 1 T1 1 T2 1 T3 2
valid_sources[0x64] 614 1 T1 2 T2 1 T11 1
valid_sources[0x65] 287 1 T1 1 T2 4 T3 1
valid_sources[0x66] 265 1 T1 1 T2 3 T3 1
valid_sources[0x67] 172 1 T2 1 T3 1 T11 3
valid_sources[0x68] 727 1 T2 2 T3 1 T11 2
valid_sources[0x69] 152 1 T1 1 T3 3 T11 3
valid_sources[0x6a] 205 1 T2 2 T3 1 T11 2
valid_sources[0x6b] 176 1 T1 1 T5 1 T11 5
valid_sources[0x6c] 147 1 T1 1 T2 2 T11 3
valid_sources[0x6d] 163 1 T1 6 T3 5 T4 4
valid_sources[0x6e] 196 1 T1 4 T3 6 T11 3
valid_sources[0x6f] 155 1 T1 1 T2 2 T3 2
valid_sources[0x70] 121 1 T1 2 T2 2 T3 1
valid_sources[0x71] 319 1 T1 6 T2 3 T3 2
valid_sources[0x72] 187 1 T2 1 T3 3 T11 4
valid_sources[0x73] 148 1 T2 2 T3 1 T11 1
valid_sources[0x74] 171 1 T1 1 T3 2 T11 2
valid_sources[0x75] 396 1 T1 1 T2 4 T3 2
valid_sources[0x76] 235 1 T1 1 T3 4 T4 2
valid_sources[0x77] 197 1 T1 6 T2 1 T3 2
valid_sources[0x78] 204 1 T1 2 T2 1 T3 3
valid_sources[0x79] 78 1 T1 3 T2 1 T11 2
valid_sources[0x7a] 377 1 T2 2 T3 2 T11 1
valid_sources[0x7b] 116 1 T3 4 T11 1 T12 1
valid_sources[0x7c] 104 1 T1 1 T2 2 T11 1
valid_sources[0x7d] 322 1 T1 1 T2 4 T11 1
valid_sources[0x7e] 149 1 T1 1 T2 3 T11 4
valid_sources[0x7f] 271 1 T1 1 T2 2 T3 5
valid_sources[0x80] 155 1 T1 3 T2 2 T11 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 10779 1 T1 46 T2 74 T3 47
values[0x0] all_enables biggest_size 11488 1 T1 153 T2 112 T3 155
values[0x1] all_enables biggest_size 10812 1 T1 128 T2 137 T3 127


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 13348 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 20658 1 T1 71 T2 395 T3 72



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 18703 1 T1 245 T2 98 T3 248
values[0x0] 7557 1 T1 46 T2 152 T3 40
values[0x1] 7746 1 T1 37 T2 154 T3 41



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 9191 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 24815 1 T1 153 T2 399 T3 164



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 151 1 T1 4 T5 8 T12 15
valid_sources[0x01] 82 1 T1 1 T15 3 T24 1
valid_sources[0x02] 391 1 T1 2 T3 3 T11 6
valid_sources[0x03] 113 1 T15 3 T27 26 T24 3
valid_sources[0x04] 160 1 T1 1 T2 5 T5 29
valid_sources[0x05] 346 1 T1 1 T3 1 T11 2
valid_sources[0x06] 133 1 T3 1 T15 4 T27 16
valid_sources[0x07] 134 1 T1 2 T15 5 T27 2
valid_sources[0x08] 120 1 T3 2 T5 7 T15 4
valid_sources[0x09] 79 1 T15 2 T16 1 T24 4
valid_sources[0x0a] 113 1 T1 1 T11 6 T15 3
valid_sources[0x0b] 119 1 T3 2 T14 1 T15 4
valid_sources[0x0c] 100 1 T3 2 T11 2 T15 4
valid_sources[0x0d] 114 1 T1 2 T3 1 T12 5
valid_sources[0x0e] 141 1 T1 4 T3 6 T15 2
valid_sources[0x0f] 140 1 T1 1 T3 2 T15 2
valid_sources[0x10] 104 1 T1 2 T11 1 T16 1
valid_sources[0x11] 99 1 T14 1 T15 5 T24 4
valid_sources[0x12] 78 1 T1 2 T3 2 T15 2
valid_sources[0x13] 106 1 T1 1 T3 1 T15 1
valid_sources[0x14] 100 1 T3 1 T11 1 T15 4
valid_sources[0x15] 85 1 T3 14 T11 6 T15 4
valid_sources[0x16] 136 1 T1 2 T11 1 T14 2
valid_sources[0x17] 79 1 T11 1 T15 2 T24 2
valid_sources[0x18] 94 1 T1 2 T4 7 T5 1
valid_sources[0x19] 123 1 T1 2 T11 3 T15 2
valid_sources[0x1a] 112 1 T1 2 T3 2 T15 4
valid_sources[0x1b] 173 1 T1 2 T15 3 T27 11
valid_sources[0x1c] 125 1 T1 2 T3 2 T14 1
valid_sources[0x1d] 114 1 T3 3 T11 1 T15 3
valid_sources[0x1e] 92 1 T1 1 T14 1 T15 4
valid_sources[0x1f] 161 1 T1 3 T5 28 T14 1
valid_sources[0x20] 141 1 T1 1 T3 1 T15 2
valid_sources[0x21] 122 1 T1 2 T3 5 T15 3
valid_sources[0x22] 121 1 T3 4 T11 1 T12 14
valid_sources[0x23] 179 1 T3 4 T15 1 T24 2
valid_sources[0x24] 105 1 T14 1 T15 6 T16 1
valid_sources[0x25] 67 1 T14 1 T15 3 T24 1
valid_sources[0x26] 171 1 T14 1 T15 1 T27 87
valid_sources[0x27] 126 1 T3 2 T11 1 T15 3
valid_sources[0x28] 121 1 T1 3 T3 4 T15 7
valid_sources[0x29] 200 1 T1 1 T3 1 T11 2
valid_sources[0x2a] 96 1 T1 1 T3 1 T11 1
valid_sources[0x2b] 136 1 T1 1 T12 7 T14 1
valid_sources[0x2c] 126 1 T1 1 T3 3 T15 1
valid_sources[0x2d] 147 1 T15 2 T24 2 T17 1
valid_sources[0x2e] 107 1 T11 2 T15 5 T16 1
valid_sources[0x2f] 106 1 T1 1 T3 1 T14 1
valid_sources[0x30] 88 1 T1 2 T3 3 T11 2
valid_sources[0x31] 166 1 T1 7 T3 2 T15 3
valid_sources[0x32] 141 1 T3 4 T5 13 T15 3
valid_sources[0x33] 227 1 T15 2 T27 82 T24 4
valid_sources[0x34] 203 1 T1 2 T3 3 T11 2
valid_sources[0x35] 91 1 T1 1 T3 3 T15 6
valid_sources[0x36] 148 1 T14 1 T15 3 T27 47
valid_sources[0x37] 134 1 T14 1 T15 2 T24 1
valid_sources[0x38] 100 1 T11 2 T15 4 T24 1
valid_sources[0x39] 265 1 T16 2 T27 14 T24 2
valid_sources[0x3a] 130 1 T3 5 T11 3 T15 4
valid_sources[0x3b] 98 1 T3 3 T11 3 T14 1
valid_sources[0x3c] 103 1 T3 3 T15 5 T24 2
valid_sources[0x3d] 122 1 T1 4 T3 1 T11 4
valid_sources[0x3e] 95 1 T5 1 T23 2 T15 2
valid_sources[0x3f] 99 1 T1 3 T15 4 T24 1
valid_sources[0x40] 102 1 T1 1 T3 1 T11 5
valid_sources[0x41] 152 1 T1 1 T3 2 T11 1
valid_sources[0x42] 200 1 T3 1 T11 6 T15 6
valid_sources[0x43] 98 1 T1 1 T3 3 T11 1
valid_sources[0x44] 176 1 T3 1 T5 4 T15 4
valid_sources[0x45] 121 1 T3 2 T5 4 T15 4
valid_sources[0x46] 78 1 T1 1 T3 1 T11 3
valid_sources[0x47] 131 1 T1 1 T3 1 T11 4
valid_sources[0x48] 102 1 T1 3 T11 1 T16 2
valid_sources[0x49] 97 1 T5 3 T11 2 T14 1
valid_sources[0x4a] 115 1 T14 1 T15 2 T16 1
valid_sources[0x4b] 107 1 T3 1 T11 2 T14 2
valid_sources[0x4c] 96 1 T1 4 T3 2 T11 2
valid_sources[0x4d] 109 1 T1 2 T11 3 T15 3
valid_sources[0x4e] 129 1 T1 1 T2 23 T14 1
valid_sources[0x4f] 121 1 T3 4 T14 1 T15 1
valid_sources[0x50] 137 1 T1 3 T15 4 T16 2
valid_sources[0x51] 158 1 T1 6 T3 1 T5 5
valid_sources[0x52] 231 1 T3 1 T15 4 T16 1
valid_sources[0x53] 126 1 T1 1 T3 5 T15 6
valid_sources[0x54] 128 1 T3 4 T11 1 T15 7
valid_sources[0x55] 81 1 T14 1 T15 4 T24 4
valid_sources[0x56] 106 1 T1 1 T15 2 T24 2
valid_sources[0x57] 139 1 T3 2 T11 6 T15 4
valid_sources[0x58] 124 1 T1 3 T3 1 T11 4
valid_sources[0x59] 119 1 T1 1 T3 1 T15 6
valid_sources[0x5a] 201 1 T1 2 T3 5 T15 3
valid_sources[0x5b] 112 1 T1 2 T3 4 T11 1
valid_sources[0x5c] 222 1 T14 1 T15 1 T27 64
valid_sources[0x5d] 104 1 T1 1 T3 1 T14 1
valid_sources[0x5e] 145 1 T12 11 T15 3 T27 21
valid_sources[0x5f] 147 1 T1 3 T5 24 T15 2
valid_sources[0x60] 124 1 T1 3 T3 3 T11 5
valid_sources[0x61] 88 1 T1 1 T3 1 T11 1
valid_sources[0x62] 213 1 T1 2 T15 2 T17 1
valid_sources[0x63] 116 1 T1 1 T11 2 T14 1
valid_sources[0x64] 153 1 T3 2 T15 7 T16 1
valid_sources[0x65] 126 1 T1 1 T3 1 T5 4
valid_sources[0x66] 137 1 T1 4 T3 1 T15 5
valid_sources[0x67] 125 1 T1 3 T3 2 T15 4
valid_sources[0x68] 136 1 T1 1 T11 7 T14 1
valid_sources[0x69] 102 1 T1 6 T3 1 T11 1
valid_sources[0x6a] 93 1 T3 1 T15 4 T17 1
valid_sources[0x6b] 153 1 T1 2 T14 1 T23 1
valid_sources[0x6c] 261 1 T1 5 T3 3 T4 3
valid_sources[0x6d] 129 1 T15 5 T27 15 T24 3
valid_sources[0x6e] 95 1 T11 2 T15 2 T27 1
valid_sources[0x6f] 160 1 T2 13 T3 3 T15 2
valid_sources[0x70] 88 1 T11 2 T14 1 T15 3
valid_sources[0x71] 274 1 T1 1 T3 1 T15 5
valid_sources[0x72] 179 1 T1 4 T11 1 T15 3
valid_sources[0x73] 141 1 T1 1 T3 11 T11 1
valid_sources[0x74] 101 1 T1 1 T11 3 T15 2
valid_sources[0x75] 131 1 T1 2 T3 3 T15 3
valid_sources[0x76] 120 1 T1 1 T15 4 T27 5
valid_sources[0x77] 95 1 T1 9 T3 3 T15 3
valid_sources[0x78] 157 1 T3 3 T12 1 T15 3
valid_sources[0x79] 96 1 T1 4 T3 1 T14 1
valid_sources[0x7a] 134 1 T1 5 T3 1 T14 2
valid_sources[0x7b] 419 1 T5 21 T11 1 T15 5
valid_sources[0x7c] 131 1 T3 1 T15 3 T24 2
valid_sources[0x7d] 117 1 T1 1 T3 2 T15 2
valid_sources[0x7e] 151 1 T15 1 T24 4 T34 1
valid_sources[0x7f] 143 1 T1 3 T3 1 T5 11
valid_sources[0x80] 103 1 T1 7 T3 4 T11 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 7615 1 T1 13 T2 98 T3 18
values[0x0] all_enables biggest_size 6780 1 T1 35 T2 152 T3 29
values[0x1] all_enables biggest_size 6263 1 T1 23 T2 145 T3 25

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%