Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

34770

1

T1

169

T2

639

T3

173

full_word

34227

1

T1

327

T2

364

T3

330

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68707	1			T1	486		T2	1003		T3	493
auto[TlIntgErrCmd]	100	1			T1	4		T3	3		T5	3
auto[TlIntgErrData]	98	1			T1	5		T3	2		T5	1
auto[TlIntgErrBoth]	92	1			T1	1		T3	5		T5	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20834

1

T1

115

T2

100

T3

121

auto[1]

48163

1

T1

381

T2

903

T3

382

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9785	1			T1	64		T2	24		T3	67
auto[TlIntgErrNone]	partial	auto[1]	24709	1			T1	95		T2	615		T3	97
auto[TlIntgErrNone]	full_word	auto[0]	10919	1			T1	46		T2	76		T3	47
auto[TlIntgErrNone]	full_word	auto[1]	23294	1			T1	281		T2	288		T3	282
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T1	2		T3	3		T11	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T1	2		T5	3		T11	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T11	1		T85	1		T82	3
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T81	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	43	1			T1	3		T3	1		T5	1
auto[TlIntgErrData]	partial	auto[1]	51	1			T1	2		T3	1		T11	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T84	1		T86	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T85	1		T87	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T3	2		T5	2		T11	1
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T1	1		T3	2		T5	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T3	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T5	1		T82	1		-	-