Unified Coverage Report :: Module :: otp_ctrl_dai

Module : otp_ctrl_dai

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_dai	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_otp_ctrl_dai

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
6.75	0.00	0.00	27.01		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_part_sel_idx	0.00	0.00	0.00			0.00
u_prim_count	0.00			0.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Module : otp_ctrl_dai

	Line No.	Total	Covered	Percent
TOTAL		241	0	0.00
CONT_ASSIGN	165	1	0	0.00
CONT_ASSIGN	167	1	0	0.00
CONT_ASSIGN	168	1	0	0.00
CONT_ASSIGN	172	1	0	0.00
ALWAYS	175	199	0	0.00
CONT_ASSIGN	706	1	0	0.00
CONT_ASSIGN	709	1	0	0.00
CONT_ASSIGN	709	1	0	0.00
CONT_ASSIGN	709	1	0	0.00
CONT_ASSIGN	709	1	0	0.00
CONT_ASSIGN	709	1	0	0.00
CONT_ASSIGN	709	1	0	0.00
CONT_ASSIGN	709	1	0	0.00
ALWAYS	741	11	0	0.00
CONT_ASSIGN	784	1	0	0.00
CONT_ASSIGN	785	1	0	0.00
ALWAYS	791	3	0	0.00
ALWAYS	794	14	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
165	0	1
167	0	1
168	0	1
172	0	1
175	0	1
178	0	1
179	0	1
182	0	1
183	0	1
184	0	1
187	0	1
188	0	1
191	0	1
194	0	1
195	0	1
196	0	1
197	0	1
200	0	1
201	0	1
202	0	1
205	0	1
206	0	1
207	0	1
210	0	1
211	0	1
213	0	1
220	0	1
221	0	1
222	0	1
223	0	1
224	0	1
225	0	1
226	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
235	0	1
236	0	1
237	0	1
238	0	1
239	0	1
240	0	1
242	0	1
			==> MISSING_ELSE
251	0	1
252	0	1
253	0	1
254	0	1
255	0	1
			==> MISSING_ELSE
262	0	1
263	0	1
265	0	1
266	0	1
267	0	1
269	0	1
271	0	1
272	0	1
275	0	1
277	0	1
278	0	1
280	0	1
281	0	1
283	0	1
287	0	1
288	0	1
289	0	1
			==> MISSING_ELSE
301	0	1
305	0	1
308	0	1
309	0	1
311	0	1
313	0	1
314	0	1
			==> MISSING_ELSE
317	0	1
318	0	1
319	0	1
329	0	1
333	0	1
335	0	1
336	0	1
338	0	1
339	0	1
341	0	1
342	0	1
345	0	1
346	0	1
			==> MISSING_ELSE
349	0	1
350	0	1
			==> MISSING_ELSE
357	0	1
358	0	1
368	0	1
369	0	1
370	0	1
371	0	1
372	0	1
373	0	1
			==> MISSING_ELSE
381	0	1
382	0	1
383	0	1
384	0	1
385	0	1
386	0	1
387	0	1
			==> MISSING_ELSE
398	0	1
399	0	1
408	0	1
411	0	1
412	0	1
414	0	1
416	0	1
417	0	1
			==> MISSING_ELSE
421	0	1
422	0	1
423	0	1
424	0	1
432	0	1
434	0	1
444	0	1
446	0	1
447	0	1
448	0	1
451	0	1
452	0	1
453	0	1
455	0	1
456	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
464	0	1
465	0	1
475	0	1
477	0	1
483	0	1
484	0	1
485	0	1
486	0	1
487	0	1
			==> MISSING_ELSE
490	0	1
491	0	1
492	0	1
500	0	1
502	0	1
507	0	1
508	0	1
509	0	1
510	0	1
			==> MISSING_ELSE
516	0	1
517	0	1
524	0	1
525	0	1
527	0	1
528	0	1
529	0	1
			==> MISSING_ELSE
537	0	1
538	0	1
541	0	1
544	0	1
545	0	1
547	0	1
549	0	1
550	0	1
			==> MISSING_ELSE
553	0	1
554	0	1
555	0	1
565	0	1
566	0	1
567	0	1
569	0	1
570	0	1
571	0	1
573	0	1
574	0	1
576	0	1
577	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
588	0	1
589	0	1
591	0	1
593	0	1
594	0	1
595	0	1
596	0	1
			==> MISSING_ELSE
599	0	1
600	0	1
			==> MISSING_ELSE
604	0	1
605	0	1
			==> MISSING_ELSE
608	0	1
609	0	1
			==> MISSING_ELSE
618	0	1
619	0	1
620	0	1
621	0	1
622	0	1
			==> MISSING_ELSE
629	0	1
630	0	1
631	0	1
632	0	1
633	0	1
			==> MISSING_ELSE
644	0	1
645	0	1
646	0	1
647	0	1
648	0	1
			==> MISSING_ELSE
656	0	1
657	0	1
			==> MISSING_ELSE
672	0	1
673	0	1
674	0	1
675	0	1
676	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
706	0	1
709	0	7
741	0	1
742	0	1
745	0	1
746	0	1
747	0	1
749	0	1
750	0	1
751	0	1
753	0	1
756	0	1
757	0	1
			==> MISSING_ELSE
784	0	1
785	0	1
791	0	3
794	0	1
795	0	1
796	0	1
797	0	1
799	0	1
800	0	1
803	0	1
804	0	1
805	0	1
806	0	1
807	0	1
808	0	1
809	0	1
811	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_dai

	Total	Covered	Percent
Conditions	73	0	0.00
Logical	73	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       172
 EXPRESSION ((state_q == IdleSt) ? data_q : '0)
             ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       172
 SUB-EXPRESSION (state_q == IdleSt)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       254
 EXPRESSION (part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}})
            ----------------------------1---------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       338
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx]))
             ----------------------1---------------------    --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       338
 SUB-EXPRESSION (otp_addr_o != digest_addr_lut[part_idx])
                --------------------1--------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       345
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       372
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       455
 EXPRESSION (otp_err_e'(otp_err_i) == MacroWriteBlankError)
            -----------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       486
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       528
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       576
 EXPRESSION (otp_err_e'(otp_err_i) == MacroEccCorrError)
            ----------------------1---------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       591
 EXPRESSION (otp_addr_o == digest_addr_lut[part_idx])
            --------------------1--------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       656
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       675
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       709
 EXPRESSION ((dai_addr_i >= 11'b00001000000) & ({1'b0, dai_addr_i} < gen_part_sel[1].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       709
 EXPRESSION ((dai_addr_i >= 11'b01101100000) & ({1'b0, dai_addr_i} < gen_part_sel[2].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       709
 EXPRESSION ((dai_addr_i >= 11'b11010000000) & ({1'b0, dai_addr_i} < gen_part_sel[3].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       709
 EXPRESSION ((dai_addr_i >= 11'b11011010000) & ({1'b0, dai_addr_i} < gen_part_sel[4].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       709
 EXPRESSION ((dai_addr_i >= 11'b11011111000) & ({1'b0, dai_addr_i} < gen_part_sel[5].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       709
 EXPRESSION ((dai_addr_i >= 11'b11101010000) & ({1'b0, dai_addr_i} < gen_part_sel[6].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       709
 EXPRESSION ((dai_addr_i >= 11'b11110101000) & ({1'b0, dai_addr_i} < gen_part_sel[7].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       749
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset))
             -----------------------1-----------------------    -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       749
 SUB-EXPRESSION (base_sel_q == PartOffset)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       753
 EXPRESSION 
 Number  Term
      1  (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest) && 
      2  (base_sel_q == DaiOffset) && 
      3  ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx]))

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       753
 SUB-EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest)
                 -----------------------1-----------------------    -----------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       753
 SUB-EXPRESSION (base_sel_q == DaiOffset)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       753
 SUB-EXPRESSION ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])
                ----------------------------------------------1----------------------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       806
 EXPRESSION (data_sel == ScrmblData)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       808
 EXPRESSION (data_sel == DaiData)
            ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : otp_ctrl_dai

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	0	0.00	(Not included in score)
Transitions	48	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DescrSt	339	Not Covered
DescrWaitSt	373	Not Covered
DigClrSt	287	Not Covered
DigFinSt	596	Not Covered
DigPadSt	600	Not Covered
DigReadSt	529	Not Covered
DigReadWaitSt	550	Not Covered
DigSt	574	Not Covered
DigWaitSt	633	Not Covered
ErrorSt	239	Not Covered
IdleSt	255	Not Covered
InitOtpSt	226	Not Covered
InitPartSt	242	Not Covered
ReadSt	269	Not Covered
ReadWaitSt	314	Not Covered
ResetSt	219	Not Covered
ScrSt	281	Not Covered
ScrWaitSt	487	Not Covered
WriteSt	283	Not Covered
WriteWaitSt	417	Not Covered

transitions	Line No.	Covered	Tests
DescrSt->DescrWaitSt	373	Not Covered
DescrSt->ErrorSt	673	Not Covered
DescrWaitSt->ErrorSt	673	Not Covered
DescrWaitSt->IdleSt	385	Not Covered
DigClrSt->DigReadSt	529	Not Covered
DigClrSt->ErrorSt	673	Not Covered
DigFinSt->DigWaitSt	633	Not Covered
DigFinSt->ErrorSt	673	Not Covered
DigPadSt->DigFinSt	622	Not Covered
DigPadSt->ErrorSt	673	Not Covered
DigReadSt->DigReadWaitSt	550	Not Covered
DigReadSt->ErrorSt	673	Not Covered
DigReadSt->IdleSt	553	Not Covered
DigReadWaitSt->DigSt	574	Not Covered
DigReadWaitSt->ErrorSt	570	Not Covered
DigSt->DigFinSt	596	Not Covered
DigSt->DigPadSt	600	Not Covered
DigSt->DigReadSt	609	Not Covered
DigSt->ErrorSt	673	Not Covered
DigWaitSt->ErrorSt	673	Not Covered
DigWaitSt->WriteSt	647	Not Covered
IdleSt->DigClrSt	287	Not Covered
IdleSt->ErrorSt	673	Not Covered
IdleSt->ReadSt	269	Not Covered
IdleSt->ScrSt	281	Not Covered
IdleSt->WriteSt	283	Not Covered
InitOtpSt->ErrorSt	239	Not Covered
InitOtpSt->InitPartSt	242	Not Covered
InitPartSt->ErrorSt	673	Not Covered
InitPartSt->IdleSt	255	Not Covered
ReadSt->ErrorSt	673	Not Covered
ReadSt->IdleSt	317	Not Covered
ReadSt->ReadWaitSt	314	Not Covered
ReadWaitSt->DescrSt	339	Not Covered
ReadWaitSt->ErrorSt	349	Not Covered
ReadWaitSt->IdleSt	341	Not Covered
ResetSt->ErrorSt	673	Not Covered
ResetSt->InitOtpSt	226	Not Covered
ScrSt->ErrorSt	673	Not Covered
ScrSt->IdleSt	490	Not Covered
ScrSt->ScrWaitSt	487	Not Covered
ScrWaitSt->ErrorSt	516	Not Covered
ScrWaitSt->WriteSt	509	Not Covered
WriteSt->ErrorSt	673	Not Covered
WriteSt->IdleSt	422	Not Covered
WriteSt->WriteWaitSt	417	Not Covered
WriteWaitSt->ErrorSt	447	Not Covered
WriteWaitSt->IdleSt	452	Not Covered

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	0	0.00	(Not included in score)
Transitions	12	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	318	Not Covered
FsmStateError	358	Not Covered
MacroEccCorrError	346	Not Covered
NoError	265	Not Covered

transitions	Line No.	Covered	Tests
AccessError->FsmStateError	358	Not Covered
AccessError->MacroEccCorrError	346	Not Covered
AccessError->NoError	265	Not Covered
FsmStateError->AccessError	318	Not Covered
FsmStateError->MacroEccCorrError	346	Not Covered
FsmStateError->NoError	265	Not Covered
MacroEccCorrError->AccessError	318	Not Covered
MacroEccCorrError->FsmStateError	358	Not Covered
MacroEccCorrError->NoError	265	Not Covered
NoError->AccessError	318	Not Covered
NoError->FsmStateError	358	Not Covered
NoError->MacroEccCorrError	346	Not Covered

---

Branch Coverage for Module : otp_ctrl_dai

	Line No.	Total	Covered	Percent
Branches		91	0	0.00
TERNARY	172	2	0	0.00
CASE	213	74	0	0.00
IF	672	3	0	0.00
IF	745	4	0	0.00
IF	791	2	0	0.00
IF	794	6	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	172	((state_q == IdleSt)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	213	case (state_q)
-2-:	223	if (init_req_i)
-3-:	225	if (otp_gnt_i)
-4-:	237	if (otp_rvalid_i)
-5-:	238	if ((!(otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	254	if ((part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}}))
-7-:	263	if (dai_req_i)
-8-:	267	case (dai_cmd_i)
-9-:	280	if (otp_ctrl_part_pkg::PartInfo[part_idx].secret)
-10-:	301	if ((part_sel_valid && (prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx])))))
-11-:	308	if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity)
-12-:	313	if (otp_gnt_i)
-13-:	329	if ((part_sel_valid && (prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx])))))
-14-:	333	if (otp_rvalid_i)
-15-:	335	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-16-:	338	if ((otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx])))
-17-:	345	if ((otp_err_e'(otp_err_i) != NoError))
-18-:	372	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-19-:	384	if (scrmbl_valid_i)
-20-:	399	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset)))))
-21-:	411	if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity)
-22-:	416	if (otp_gnt_i)
-23-:	434	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset)))))
-24-:	444	if (otp_rvalid_i)
-25-:	446	if ((!(otp_err_e'(otp_err_i) inside {NoError, MacroWriteBlankError})))
-26-:	455	if ((otp_err_e'(otp_err_i) == MacroWriteBlankError))
-27-:	477	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))))
-28-:	486	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-29-:	502	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))))
-30-:	508	if (scrmbl_valid_i)
-31-:	528	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-32-:	538	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock)) && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)))
-33-:	544	if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity)
-34-:	549	if (otp_gnt_i)
-35-:	566	if (otp_rvalid_i)
-36-:	569	if ((!(otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-37-:	576	if ((otp_err_e'(otp_err_i) == MacroEccCorrError))
-38-:	591	if ((otp_addr_o == digest_addr_lut[part_idx]))
-39-:	593	if ((!cnt[0]))
-40-:	595	if (scrmbl_ready_i)
-41-:	599	if (scrmbl_ready_i)
-42-:	604	if ((!cnt[0]))
-43-:	608	if (scrmbl_ready_i)
-44-:	621	if (scrmbl_ready_i)
-45-:	632	if (scrmbl_ready_i)
-46-:	646	if (scrmbl_valid_i)
-47-:	656	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	-41-	-42-	-43-	-44-	-45-	-46-	-47-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitOtpSt	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitOtpSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitOtpSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitPartSt	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitPartSt	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	DaiRead	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	DaiWrite	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	DaiWrite	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	DaiDigest	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DescrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DescrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DescrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DescrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	1	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	0	-	-	-	-	Not Covered
DigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Not Covered
DigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	672	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	675	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	745	if (otp_ctrl_part_pkg::PartInfo[part_idx].secret)
-2-:	749	if ((otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset)))
-3-:	753	if ((((otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest) && (base_sel_q == DaiOffset)) && ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	791	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	794	if ((!rst_ni))
-2-:	803	if (data_clr)
-3-:	805	if (data_en)
-4-:	806	if ((data_sel == ScrmblData))
-5-:	808	if ((data_sel == DaiData))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Not Covered
0	1	-	-	-	Not Covered
0	0	1	1	-	Not Covered
0	0	1	0	1	Not Covered
0	0	1	0	0	Not Covered
0	0	0	-	-	Not Covered

Line Coverage for Instance : tb.dut.u_otp_ctrl_dai

	Line No.	Total	Covered	Percent
TOTAL		241	0	0.00
CONT_ASSIGN	165	1	0	0.00
CONT_ASSIGN	167	1	0	0.00
CONT_ASSIGN	168	1	0	0.00
CONT_ASSIGN	172	1	0	0.00
ALWAYS	175	199	0	0.00
CONT_ASSIGN	706	1	0	0.00
CONT_ASSIGN	709	1	0	0.00
CONT_ASSIGN	709	1	0	0.00
CONT_ASSIGN	709	1	0	0.00
CONT_ASSIGN	709	1	0	0.00
CONT_ASSIGN	709	1	0	0.00
CONT_ASSIGN	709	1	0	0.00
CONT_ASSIGN	709	1	0	0.00
ALWAYS	741	11	0	0.00
CONT_ASSIGN	784	1	0	0.00
CONT_ASSIGN	785	1	0	0.00
ALWAYS	791	3	0	0.00
ALWAYS	794	14	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
165	0	1
167	0	1
168	0	1
172	0	1
175	0	1
178	0	1
179	0	1
182	0	1
183	0	1
184	0	1
187	0	1
188	0	1
191	0	1
194	0	1
195	0	1
196	0	1
197	0	1
200	0	1
201	0	1
202	0	1
205	0	1
206	0	1
207	0	1
210	0	1
211	0	1
213	0	1
220	0	1
221	0	1
222	0	1
223	0	1
224	0	1
225	0	1
226	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
235	0	1
236	0	1
237	0	1
238	0	1
239	0	1
240	0	1
242	0	1
			==> MISSING_ELSE
251	0	1
252	0	1
253	0	1
254	0	1
255	0	1
			==> MISSING_ELSE
262	0	1
263	0	1
265	0	1
266	0	1
267	0	1
269	0	1
271	0	1
272	0	1
275	0	1
277	0	1
278	0	1
280	0	1
281	0	1
283	0	1
287	0	1
288	0	1
289	0	1
			==> MISSING_ELSE
301	0	1
305	0	1
308	0	1
309	0	1
311	0	1
313	0	1
314	0	1
			==> MISSING_ELSE
317	0	1
318	0	1
319	0	1
329	0	1
333	0	1
335	0	1
336	0	1
338	0	1
339	0	1
341	0	1
342	0	1
345	0	1
346	0	1
			==> MISSING_ELSE
349	0	1
350	0	1
			==> MISSING_ELSE
357	0	1
358	0	1
368	0	1
369	0	1
370	0	1
371	0	1
372	0	1
373	0	1
			==> MISSING_ELSE
381	0	1
382	0	1
383	0	1
384	0	1
385	0	1
386	0	1
387	0	1
			==> MISSING_ELSE
398	0	1
399	0	1
408	0	1
411	0	1
412	0	1
414	0	1
416	0	1
417	0	1
			==> MISSING_ELSE
421	0	1
422	0	1
423	0	1
424	0	1
432	0	1
434	0	1
444	0	1
446	0	1
447	0	1
448	0	1
451	0	1
452	0	1
453	0	1
455	0	1
456	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
464	0	1
465	0	1
475	0	1
477	0	1
483	0	1
484	0	1
485	0	1
486	0	1
487	0	1
			==> MISSING_ELSE
490	0	1
491	0	1
492	0	1
500	0	1
502	0	1
507	0	1
508	0	1
509	0	1
510	0	1
			==> MISSING_ELSE
516	0	1
517	0	1
524	0	1
525	0	1
527	0	1
528	0	1
529	0	1
			==> MISSING_ELSE
537	0	1
538	0	1
541	0	1
544	0	1
545	0	1
547	0	1
549	0	1
550	0	1
			==> MISSING_ELSE
553	0	1
554	0	1
555	0	1
565	0	1
566	0	1
567	0	1
569	0	1
570	0	1
571	0	1
573	0	1
574	0	1
576	0	1
577	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
588	0	1
589	0	1
591	0	1
593	0	1
594	0	1
595	0	1
596	0	1
			==> MISSING_ELSE
599	0	1
600	0	1
			==> MISSING_ELSE
604	0	1
605	0	1
			==> MISSING_ELSE
608	0	1
609	0	1
			==> MISSING_ELSE
618	0	1
619	0	1
620	0	1
621	0	1
622	0	1
			==> MISSING_ELSE
629	0	1
630	0	1
631	0	1
632	0	1
633	0	1
			==> MISSING_ELSE
644	0	1
645	0	1
646	0	1
647	0	1
648	0	1
			==> MISSING_ELSE
656	0	1
657	0	1
			==> MISSING_ELSE
672	0	1
673	0	1
674	0	1
675	0	1
676	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
706	0	1
709	0	7
741	0	1
742	0	1
745	0	1
746	0	1
747	0	1
749	0	1
750	0	1
751	0	1
753	0	1
756	0	1
757	0	1
			==> MISSING_ELSE
784	0	1
785	0	1
791	0	3
794	0	1
795	0	1
796	0	1
797	0	1
799	0	1
800	0	1
803	0	1
804	0	1
805	0	1
806	0	1
807	0	1
808	0	1
809	0	1
811	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_otp_ctrl_dai

	Total	Covered	Percent
Conditions	73	0	0.00
Logical	73	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       172
 EXPRESSION ((state_q == IdleSt) ? data_q : '0)
             ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       172
 SUB-EXPRESSION (state_q == IdleSt)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       254
 EXPRESSION (part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}})
            ----------------------------1---------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       338
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx]))
             ----------------------1---------------------    --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       338
 SUB-EXPRESSION (otp_addr_o != digest_addr_lut[part_idx])
                --------------------1--------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       345
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       372
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       455
 EXPRESSION (otp_err_e'(otp_err_i) == MacroWriteBlankError)
            -----------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       486
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       528
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       576
 EXPRESSION (otp_err_e'(otp_err_i) == MacroEccCorrError)
            ----------------------1---------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       591
 EXPRESSION (otp_addr_o == digest_addr_lut[part_idx])
            --------------------1--------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       656
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       675
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       709
 EXPRESSION ((dai_addr_i >= 11'b00001000000) & ({1'b0, dai_addr_i} < gen_part_sel[1].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       709
 EXPRESSION ((dai_addr_i >= 11'b01101100000) & ({1'b0, dai_addr_i} < gen_part_sel[2].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       709
 EXPRESSION ((dai_addr_i >= 11'b11010000000) & ({1'b0, dai_addr_i} < gen_part_sel[3].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       709
 EXPRESSION ((dai_addr_i >= 11'b11011010000) & ({1'b0, dai_addr_i} < gen_part_sel[4].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       709
 EXPRESSION ((dai_addr_i >= 11'b11011111000) & ({1'b0, dai_addr_i} < gen_part_sel[5].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       709
 EXPRESSION ((dai_addr_i >= 11'b11101010000) & ({1'b0, dai_addr_i} < gen_part_sel[6].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       709
 EXPRESSION ((dai_addr_i >= 11'b11110101000) & ({1'b0, dai_addr_i} < gen_part_sel[7].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       749
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset))
             -----------------------1-----------------------    -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       749
 SUB-EXPRESSION (base_sel_q == PartOffset)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       753
 EXPRESSION 
 Number  Term
      1  (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest) && 
      2  (base_sel_q == DaiOffset) && 
      3  ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx]))

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       753
 SUB-EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest)
                 -----------------------1-----------------------    -----------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       753
 SUB-EXPRESSION (base_sel_q == DaiOffset)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       753
 SUB-EXPRESSION ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])
                ----------------------------------------------1----------------------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       806
 EXPRESSION (data_sel == ScrmblData)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       808
 EXPRESSION (data_sel == DaiData)
            ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_otp_ctrl_dai

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	0	0.00	(Not included in score)
Transitions	48	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DescrSt	339	Not Covered
DescrWaitSt	373	Not Covered
DigClrSt	287	Not Covered
DigFinSt	596	Not Covered
DigPadSt	600	Not Covered
DigReadSt	529	Not Covered
DigReadWaitSt	550	Not Covered
DigSt	574	Not Covered
DigWaitSt	633	Not Covered
ErrorSt	239	Not Covered
IdleSt	255	Not Covered
InitOtpSt	226	Not Covered
InitPartSt	242	Not Covered
ReadSt	269	Not Covered
ReadWaitSt	314	Not Covered
ResetSt	219	Not Covered
ScrSt	281	Not Covered
ScrWaitSt	487	Not Covered
WriteSt	283	Not Covered
WriteWaitSt	417	Not Covered

transitions	Line No.	Covered	Tests
DescrSt->DescrWaitSt	373	Not Covered
DescrSt->ErrorSt	673	Not Covered
DescrWaitSt->ErrorSt	673	Not Covered
DescrWaitSt->IdleSt	385	Not Covered
DigClrSt->DigReadSt	529	Not Covered
DigClrSt->ErrorSt	673	Not Covered
DigFinSt->DigWaitSt	633	Not Covered
DigFinSt->ErrorSt	673	Not Covered
DigPadSt->DigFinSt	622	Not Covered
DigPadSt->ErrorSt	673	Not Covered
DigReadSt->DigReadWaitSt	550	Not Covered
DigReadSt->ErrorSt	673	Not Covered
DigReadSt->IdleSt	553	Not Covered
DigReadWaitSt->DigSt	574	Not Covered
DigReadWaitSt->ErrorSt	570	Not Covered
DigSt->DigFinSt	596	Not Covered
DigSt->DigPadSt	600	Not Covered
DigSt->DigReadSt	609	Not Covered
DigSt->ErrorSt	673	Not Covered
DigWaitSt->ErrorSt	673	Not Covered
DigWaitSt->WriteSt	647	Not Covered
IdleSt->DigClrSt	287	Not Covered
IdleSt->ErrorSt	673	Not Covered
IdleSt->ReadSt	269	Not Covered
IdleSt->ScrSt	281	Not Covered
IdleSt->WriteSt	283	Not Covered
InitOtpSt->ErrorSt	239	Not Covered
InitOtpSt->InitPartSt	242	Not Covered
InitPartSt->ErrorSt	673	Not Covered
InitPartSt->IdleSt	255	Not Covered
ReadSt->ErrorSt	673	Not Covered
ReadSt->IdleSt	317	Not Covered
ReadSt->ReadWaitSt	314	Not Covered
ReadWaitSt->DescrSt	339	Not Covered
ReadWaitSt->ErrorSt	349	Not Covered
ReadWaitSt->IdleSt	341	Not Covered
ResetSt->ErrorSt	673	Not Covered
ResetSt->InitOtpSt	226	Not Covered
ScrSt->ErrorSt	673	Not Covered
ScrSt->IdleSt	490	Not Covered
ScrSt->ScrWaitSt	487	Not Covered
ScrWaitSt->ErrorSt	516	Not Covered
ScrWaitSt->WriteSt	509	Not Covered
WriteSt->ErrorSt	673	Not Covered
WriteSt->IdleSt	422	Not Covered
WriteSt->WriteWaitSt	417	Not Covered
WriteWaitSt->ErrorSt	447	Not Covered
WriteWaitSt->IdleSt	452	Not Covered

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	0	0.00	(Not included in score)
Transitions	9	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	318	Not Covered
FsmStateError	358	Not Covered
MacroEccCorrError	346	Not Covered
NoError	265	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->FsmStateError	358	Not Covered
AccessError->MacroEccCorrError	346	Excluded		VC_COV_UNR
AccessError->NoError	265	Not Covered
FsmStateError->AccessError	318	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	346	Excluded		VC_COV_UNR
FsmStateError->NoError	265	Not Covered
MacroEccCorrError->AccessError	318	Not Covered
MacroEccCorrError->FsmStateError	358	Not Covered
MacroEccCorrError->NoError	265	Not Covered
NoError->AccessError	318	Not Covered
NoError->FsmStateError	358	Not Covered
NoError->MacroEccCorrError	346	Not Covered

---

Branch Coverage for Instance : tb.dut.u_otp_ctrl_dai

	Line No.	Total	Covered	Percent
Branches		91	0	0.00
TERNARY	172	2	0	0.00
CASE	213	74	0	0.00
IF	672	3	0	0.00
IF	745	4	0	0.00
IF	791	2	0	0.00
IF	794	6	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	172	((state_q == IdleSt)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	213	case (state_q)
-2-:	223	if (init_req_i)
-3-:	225	if (otp_gnt_i)
-4-:	237	if (otp_rvalid_i)
-5-:	238	if ((!(otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	254	if ((part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}}))
-7-:	263	if (dai_req_i)
-8-:	267	case (dai_cmd_i)
-9-:	280	if (otp_ctrl_part_pkg::PartInfo[part_idx].secret)
-10-:	301	if ((part_sel_valid && (prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx])))))
-11-:	308	if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity)
-12-:	313	if (otp_gnt_i)
-13-:	329	if ((part_sel_valid && (prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx])))))
-14-:	333	if (otp_rvalid_i)
-15-:	335	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-16-:	338	if ((otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx])))
-17-:	345	if ((otp_err_e'(otp_err_i) != NoError))
-18-:	372	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-19-:	384	if (scrmbl_valid_i)
-20-:	399	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset)))))
-21-:	411	if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity)
-22-:	416	if (otp_gnt_i)
-23-:	434	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset)))))
-24-:	444	if (otp_rvalid_i)
-25-:	446	if ((!(otp_err_e'(otp_err_i) inside {NoError, MacroWriteBlankError})))
-26-:	455	if ((otp_err_e'(otp_err_i) == MacroWriteBlankError))
-27-:	477	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))))
-28-:	486	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-29-:	502	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))))
-30-:	508	if (scrmbl_valid_i)
-31-:	528	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-32-:	538	if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock)) && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)))
-33-:	544	if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity)
-34-:	549	if (otp_gnt_i)
-35-:	566	if (otp_rvalid_i)
-36-:	569	if ((!(otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-37-:	576	if ((otp_err_e'(otp_err_i) == MacroEccCorrError))
-38-:	591	if ((otp_addr_o == digest_addr_lut[part_idx]))
-39-:	593	if ((!cnt[0]))
-40-:	595	if (scrmbl_ready_i)
-41-:	599	if (scrmbl_ready_i)
-42-:	604	if ((!cnt[0]))
-43-:	608	if (scrmbl_ready_i)
-44-:	621	if (scrmbl_ready_i)
-45-:	632	if (scrmbl_ready_i)
-46-:	646	if (scrmbl_valid_i)
-47-:	656	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	-41-	-42-	-43-	-44-	-45-	-46-	-47-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitOtpSt	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitOtpSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitOtpSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitPartSt	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitPartSt	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	DaiRead	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	DaiWrite	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	DaiWrite	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	DaiDigest	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DescrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DescrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DescrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DescrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	1	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	0	-	-	-	-	Not Covered
DigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Not Covered
DigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	672	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	675	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	745	if (otp_ctrl_part_pkg::PartInfo[part_idx].secret)
-2-:	749	if ((otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset)))
-3-:	753	if ((((otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest) && (base_sel_q == DaiOffset)) && ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	791	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	794	if ((!rst_ni))
-2-:	803	if (data_clr)
-3-:	805	if (data_en)
-4-:	806	if ((data_sel == ScrmblData))
-5-:	808	if ((data_sel == DaiData))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Not Covered
0	1	-	-	-	Not Covered
0	0	1	1	-	Not Covered
0	0	1	0	1	Not Covered
0	0	1	0	0	Not Covered
0	0	0	-	-	Not Covered