Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
6.75	0.00	0.00	27.01		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_otp_ctrl_ecc_reg	0.00	0.00		0.00		0.00
u_prim_count	0.00			0.00
u_prim_mubi8_sender_read_lock_pre	0.00	0.00				0.00
u_prim_mubi8_sender_write_lock_pre	0.00	0.00				0.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

	Line No.	Total	Covered	Percent
TOTAL		130	0	0.00
CONT_ASSIGN	182	1	0	0.00
ALWAYS	195	111	0	0.00
CONT_ASSIGN	625	1	0	0.00
CONT_ASSIGN	630	1	0	0.00
CONT_ASSIGN	631	1	0	0.00
CONT_ASSIGN	635	1	0	0.00
CONT_ASSIGN	641	1	0	0.00
CONT_ASSIGN	664	1	0	0.00
CONT_ASSIGN	667	1	0	0.00
CONT_ASSIGN	669	1	0	0.00
CONT_ASSIGN	712	1	0	0.00
CONT_ASSIGN	732	1	0	0.00
ALWAYS	739	3	0	0.00
ALWAYS	742	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
182	0	1
195	0	1
198	0	1
201	0	1
204	0	1
207	0	1
208	0	1
209	0	1
210	0	1
213	0	1
214	0	1
215	0	1
218	0	1
219	0	1
222	0	1
223	0	1
226	0	1
227	0	1
229	0	1
234	0	1
235	0	1
			==> MISSING_ELSE
243	0	1
244	0	1
245	0	1
			==> MISSING_ELSE
254	0	1
255	0	1
256	0	1
260	0	1
261	0	1
264	0	1
265		unreachable
267	0	1
268	0	1
271	0	1
272	0	1
			==> MISSING_ELSE
275	0	1
276	0	1
			==> MISSING_ELSE
287	0	1
288	0	1
289	0	1
290	0	1
291	0	1
292		unreachable
			==> MISSING_ELSE
300	0	1
301	0	1
302	0	1
303	0	1
304		unreachable
305		unreachable
306		unreachable
			==> MISSING_ELSE
313	0	1
314	0	1
315		unreachable
320	0	1
322	0	1
323	0	1
324	0	1
			==> MISSING_ELSE
332	0	1
337	0	1
338		unreachable
			==> MISSING_ELSE
340	0	1
341	0	1
			==> MISSING_ELSE
351	0	1
352	0	1
355	0	1
357		unreachable
358		unreachable
359		unreachable
362		unreachable
363		unreachable
365		unreachable
370	0	1
374	0	1
375	0	1
376	0	1
379	0	1
380	0	1
383	0	1
384	0	1
386	0	1
390	0	1
391	0	1
			==> MISSING_ELSE
394	0	1
395	0	1
397	0	1
			==> MISSING_ELSE
406	0	1
407		unreachable
408		unreachable
409		unreachable
412		unreachable
413		unreachable
414		unreachable
415		unreachable
416		unreachable
			==> MISSING_ELSE
421		unreachable
422		unreachable
423		unreachable
			==> MISSING_ELSE
432	0	1
433	0	1
434	0	1
			==> MISSING_ELSE
444	0	1
445	0	1
446	0	1
447	0	1
448	0	1
449		unreachable
			==> MISSING_ELSE
456	0	1
457	0	1
458	0	1
459		unreachable
			==> MISSING_ELSE
469	0	1
470	0	1
471	0	1
472		unreachable
474		unreachable
478		unreachable
479		unreachable
480		unreachable
482		unreachable
483		unreachable
487		unreachable
488		unreachable
			==> MISSING_ELSE
492		unreachable
493		unreachable
			==> MISSING_ELSE
			==> MISSING_ELSE
505	0	1
506	0	1
507	0	1
508	0	1
509		unreachable
			==> MISSING_ELSE
517	0	1
518	0	1
519	0	1
520	0	1
521		unreachable
			==> MISSING_ELSE
531	0	1
532	0	1
533	0	1
536		unreachable
537		unreachable
540		unreachable
541		unreachable
545		unreachable
549		unreachable
550		unreachable
552		unreachable
			==> MISSING_ELSE
561	0	1
562	0	1
563	0	1
			==> MISSING_ELSE
567	0	1
568	0	1
584	0	1
585	0	1
586	0	1
587	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
591	0	1
592	0	1
593	0	1
594	0	1
595	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
625	0	1
630	0	1
631	0	1
635	0	1
641	0	1
664	0	1
667	0	1
669	0	1
712	0	1
732	0	1
739	0	3
742	0	1
743	0	1
745	0	1
747	0	1
748	0	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

	Total	Covered	Percent
Conditions	24	0	0.00
Logical	24	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       260
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       271
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       291
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       357
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       357
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       357
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       374
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       390
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       415
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       422
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       474
 EXPRESSION (cnt == PenultimateScrmblBlock)
            ---------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       536
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       536
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       536
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       562
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       586
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       594
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       625
 EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11110101000)
             -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       625
 SUB-EXPRESSION (base_sel == DigOffset)
                -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       641
 EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       641
 SUB-EXPRESSION (data_sel == ScrmblData)
                ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       667
 EXPRESSION (init_done_o ? data : DataDefault)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	0	0.00	(Not included in score)
Transitions	16	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CnstyReadSt	323	Not Covered
CnstyReadWaitSt	341	Not Covered
ErrorSt	275	Not Covered
IdleSt	358	Not Covered
InitDescrSt	265	Excluded
InitDescrWaitSt	292	Excluded
InitSt	235	Not Covered
InitWaitSt	245	Not Covered
IntegDigClrSt	261	Not Covered
IntegDigFinSt	480	Excluded
IntegDigPadSt	482	Excluded
IntegDigSt	423	Excluded
IntegDigWaitSt	521	Excluded
IntegScrSt	416	Excluded
IntegScrWaitSt	449	Excluded
ResetSt	233	Not Covered

transitions	Line No.	Covered	Tests
CnstyReadSt->CnstyReadWaitSt	341	Not Covered
CnstyReadSt->ErrorSt	585	Not Covered
CnstyReadWaitSt->CnstyReadSt	379	Not Covered
CnstyReadWaitSt->ErrorSt	362	Not Covered
CnstyReadWaitSt->IdleSt	358	Not Covered
IdleSt->CnstyReadSt	323	Not Covered
IdleSt->ErrorSt	585	Not Covered
IdleSt->IntegDigClrSt	315	Excluded
InitDescrSt->ErrorSt	585	Excluded
InitDescrSt->InitDescrWaitSt	292	Excluded
InitDescrWaitSt->ErrorSt	585	Excluded
InitDescrWaitSt->InitSt	304	Excluded
InitSt->ErrorSt	585	Not Covered
InitSt->InitWaitSt	245	Not Covered
InitWaitSt->ErrorSt	275	Not Covered
InitWaitSt->InitDescrSt	265	Excluded
InitWaitSt->InitSt	267	Not Covered
InitWaitSt->IntegDigClrSt	261	Not Covered
IntegDigClrSt->ErrorSt	585	Not Covered
IntegDigClrSt->IdleSt	432	Not Covered
IntegDigClrSt->IntegDigSt	423	Excluded
IntegDigClrSt->IntegScrSt	416	Excluded
IntegDigFinSt->ErrorSt	585	Excluded
IntegDigFinSt->IntegDigWaitSt	521	Excluded
IntegDigPadSt->ErrorSt	585	Excluded
IntegDigPadSt->IntegDigFinSt	509	Excluded
IntegDigSt->ErrorSt	585	Excluded
IntegDigSt->IntegDigFinSt	480	Excluded
IntegDigSt->IntegDigPadSt	482	Excluded
IntegDigSt->IntegScrSt	493	Excluded
IntegDigWaitSt->ErrorSt	549	Excluded
IntegDigWaitSt->IdleSt	537	Excluded
IntegScrSt->ErrorSt	585	Excluded
IntegScrSt->IntegScrWaitSt	449	Excluded
IntegScrWaitSt->ErrorSt	585	Excluded
IntegScrWaitSt->IntegDigSt	459	Excluded
ResetSt->ErrorSt	585	Not Covered
ResetSt->InitSt	235	Not Covered

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	0	0.00	(Not included in score)
Transitions	5	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
CheckFailError	363	Not Covered
FsmStateError	563	Not Covered
MacroEccCorrError	272	Not Covered
NoError	562	Not Covered

transitions	Line No.	Covered	Tests
CheckFailError->FsmStateError	595	Excluded
CheckFailError->MacroEccCorrError	272	Excluded
FsmStateError->CheckFailError	363	Excluded
FsmStateError->MacroEccCorrError	272	Excluded
MacroEccCorrError->CheckFailError	363	Not Covered
MacroEccCorrError->FsmStateError	595	Not Covered
NoError->CheckFailError	363	Not Covered
NoError->FsmStateError	563	Not Covered
NoError->MacroEccCorrError	272	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

	Line No.	Total	Covered	Percent
Branches		54	0	0.00
TERNARY	625	1	0	0.00
TERNARY	641	2	0	0.00
TERNARY	667	2	0	0.00
CASE	229	40	0	0.00
IF	584	2	0	0.00
IF	591	3	0	0.00
IF	739	2	0	0.00
IF	742	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	625	((base_sel == DigOffset)) ? 

Branches:

-1-	Status	Tests
1	Excluded
0	Not Covered

	LineNo.	Expression
-1-:	641	((data_sel == ScrmblData)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	667	(init_done_o) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	229	case (state_q)
-2-:	234	if (init_req_i)
-3-:	244	if (otp_gnt_i)
-4-:	254	if (otp_rvalid_i)
-5-:	256	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-6-:	260	if ((cnt == LastScrmblBlock))
-7-:	264	if (1'b0)
-8-:	271	if ((otp_err_e'(otp_err_i) != NoError))
-9-:	291	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-10-:	303	if (scrmbl_valid_i)
-11-:	313	if (integ_chk_req_i)
-12-:	314	if (1'b0)
-13-:	322	if (cnsty_chk_req_i)
-14-:	337	if (1'b0)
-15-:	340	if (otp_gnt_i)
-16-:	351	if (otp_rvalid_i)
-17-:	352	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-18-:	355	if (1'b0)
-19-:	357	if (((digest_o == data_mux) || (digest_o == '0)))
-20-:	370	if (((scrmbl_data_o == data_mux) || lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i)))
-21-:	374	if ((cnt == LastScrmblBlock))
-22-:	390	if ((otp_err_e'(otp_err_i) != NoError))
-23-:	406	if (1'b0)
-24-:	413	if (1'b0)
-25-:	415	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-26-:	422	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-27-:	433	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-28-:	448	if (scrmbl_ready_i)
-29-:	458	if (scrmbl_valid_i)
-30-:	471	if (scrmbl_ready_i)
-31-:	474	if ((cnt == PenultimateScrmblBlock))
-32-:	478	if (cnt[0])
-33-:	487	if (cnt[0])
-34-:	492	if (1'b0)
-35-:	508	if (scrmbl_ready_i)
-36-:	520	if (scrmbl_ready_i)
-37-:	533	if (scrmbl_valid_i)
-38-:	536	if (((digest_o == data_mux) || (digest_o == '0)))
-39-:	540	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-40-:	562	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitWaitSt	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitDescrSt	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitDescrSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitDescrWaitSt	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitDescrWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	-	-	-	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	-	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	1	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	0	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Unreachable
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Unreachable
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	Unreachable
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	Unreachable
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Unreachable
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	584	if (ecc_err)
-2-:	586	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Excluded
0	-	Not Covered

	LineNo.	Expression
-1-:	591	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	594	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	739	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	742	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered