Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[6].gen_buffered.u_part_buf

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.42	78.75	81.25		58.33	71.43	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.94	83.57	81.25	95.40	58.33	74.70	86.36

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.26	96.15	86.96	87.90		93.10	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	93.83	100.00		95.33		80.00	100.00
u_prim_count	100.00			100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
TOTAL		160	126	78.75
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
ALWAYS	206	140	106	75.71
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	641	1	1	100.00
CONT_ASSIGN	642	1	1	100.00
CONT_ASSIGN	646	1	1	100.00
CONT_ASSIGN	652	1	1	100.00
CONT_ASSIGN	675	1	1	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	743	1	1	100.00
ALWAYS	750	3	3	100.00
ALWAYS	753	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
182	1	1
193	1	1
206	1	1
209	1	1
212	1	1
215	1	1
218	1	1
219	1	1
220	1	1
221	1	1
224	1	1
225	1	1
226	1	1
229	1	1
230	1	1
233	1	1
234	1	1
237	1	1
238	1	1
240	1	1
245	1	1
246	1	1
			MISSING_ELSE
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
265	1	1
266	1	1
267	1	1
271	1	1
272	1	1
275	1	1
276		unreachable
278	1	1
279	1	1
282	1	1
283	1	1
			MISSING_ELSE
286	1	1
287	1	1
			MISSING_ELSE
298	0	1
299	0	1
300	0	1
301	0	1
302	0	1
303	0	1
			==> MISSING_ELSE
311	0	1
312	0	1
313	0	1
314	0	1
315	0	1
316	0	1
317	0	1
			==> MISSING_ELSE
324	1	1
325	1	1
326	1	1
331		unreachable
333	1	1
334	1	1
335	1	1
			MISSING_ELSE
343	1	1
348	1	1
349	1	1
			==> MISSING_ELSE
351	1	1
352	1	1
			MISSING_ELSE
362	1	1
363	1	1
366	1	1
368	1	1
369	1	1
370	1	1
373	0	1
374	0	1
376	0	1
381		unreachable
385		unreachable
386		unreachable
387		unreachable
390		unreachable
391		unreachable
394		unreachable
395		unreachable
397		unreachable
401	1	1
402	1	1
			MISSING_ELSE
405	1	1
406	1	1
408	1	1
			MISSING_ELSE
417	1	1
418	1	1
419	1	1
420	1	1
423	1	1
424	1	1
425		unreachable
426		unreachable
427		unreachable
			==> MISSING_ELSE
432	1	1
433	1	1
434	1	1
			MISSING_ELSE
443		unreachable
444		unreachable
445		unreachable
			==> MISSING_ELSE
455	0	1
456	0	1
457	0	1
458	0	1
459	0	1
460	0	1
			==> MISSING_ELSE
467	0	1
468	0	1
469	0	1
470	0	1
			==> MISSING_ELSE
480	1	1
481	1	1
482	1	1
483	1	1
485	1	1
489	1	1
490	0	1
491	0	1
493	1	1
494	1	1
498	0	1
499	0	1
			==> MISSING_ELSE
503	0	1
504		unreachable
			==> MISSING_ELSE
			==> MISSING_ELSE
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
			==> MISSING_ELSE
528	1	1
529	1	1
530	1	1
531	1	1
532	1	1
			MISSING_ELSE
542	1	1
543	1	1
544	1	1
547	1	1
548	1	1
551	1	1
552	1	1
556	1	1
560	1	1
561	1	1
563	1	1
			MISSING_ELSE
572	1	1
573	1	1
574	1	1
			MISSING_ELSE
578	1	1
579	1	1
595	1	1
596	0	1
597	0	1
598	0	1
			==> MISSING_ELSE
			MISSING_ELSE
602	1	1
603	1	1
604	1	1
605	1	1
606	1	1
			MISSING_ELSE
			MISSING_ELSE
636	1	1
641	1	1
642	1	1
646	1	1
652	1	1
675	1	1
678	1	1
680	1	1
709	1	1
743	1	1
750	3	3
753	1	1
754	1	1
756	1	1
758	1	1
759	1	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Total	Covered	Percent
Conditions	48	39	81.25
Logical	48	39	81.25
Non-Logical	0	0
Event	0	0

 LINE       271
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       282
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T31,T39,T20

 LINE       302
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       368
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T6,T7,T15
1	0	Covered	T1,T22,T40

 LINE       368
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Covered	T6,T7,T15
1	Covered	T1,T2,T3

 LINE       368
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T22,T40
1	Covered	T1,T2,T3

 LINE       385
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       401
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T41,T42,T43

 LINE       426
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       433
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       485
 EXPRESSION (cnt == PenultimateScrmblBlock)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       547
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T44,T45,T46
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       547
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       547
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       573
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T9,T10,T12
1	Covered	T28,T29,T30

 LINE       597
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       605
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T9,T10,T12
1	Covered	T9,T10,T12

 LINE       636
 EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11011000000)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       636
 SUB-EXPRESSION (base_sel == DigOffset)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       652
 EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       652
 SUB-EXPRESSION (data_sel == ScrmblData)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       678
 EXPRESSION (init_done_o ? data : DataDefault)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       709
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       709
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

Summary for FSM :: state_q

	Total	Covered	Percent
States	15	11	73.33	(Not included in score)
Transitions	31	17	54.84
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CnstyReadSt	334	Covered	T1,T2,T3
CnstyReadWaitSt	352	Covered	T1,T2,T3
ErrorSt	286	Covered	T9,T10,T12
IdleSt	369	Covered	T1,T2,T3
InitDescrSt	276	Not Covered
InitDescrWaitSt	303	Not Covered
InitSt	246	Covered	T1,T2,T3
InitWaitSt	256	Covered	T1,T2,T3
IntegDigClrSt	272	Covered	T1,T2,T3
IntegDigFinSt	491	Covered	T1,T2,T3
IntegDigPadSt	493	Excluded	T1,T2,T3
IntegDigSt	434	Covered	T1,T2,T3
IntegDigWaitSt	532	Covered	T1,T2,T3
IntegScrSt	427	Not Covered
IntegScrWaitSt	460	Not Covered
ResetSt	244	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
CnstyReadSt->CnstyReadWaitSt	352	Covered	T1,T2,T3
CnstyReadSt->ErrorSt	596	Covered	T23,T65,T6
CnstyReadWaitSt->CnstyReadSt	390	Excluded
CnstyReadWaitSt->ErrorSt	373	Covered	T23,T65,T48
CnstyReadWaitSt->IdleSt	369	Covered	T1,T2,T3
IdleSt->CnstyReadSt	334	Covered	T1,T2,T3
IdleSt->ErrorSt	596	Covered	T9,T12,T66
IdleSt->IntegDigClrSt	326	Covered	T1,T3,T4
InitDescrSt->ErrorSt	596	Not Covered
InitDescrSt->InitDescrWaitSt	303	Not Covered
InitDescrWaitSt->ErrorSt	596	Not Covered
InitDescrWaitSt->InitSt	315	Not Covered
InitSt->ErrorSt	596	Covered	T10,T14,T106
InitSt->InitWaitSt	256	Covered	T1,T2,T3
InitWaitSt->ErrorSt	286	Covered	T80,T81,T82
InitWaitSt->InitDescrSt	276	Not Covered
InitWaitSt->InitSt	278	Excluded	T1,T2,T3
InitWaitSt->IntegDigClrSt	272	Covered	T1,T2,T3
IntegDigClrSt->ErrorSt	596	Covered	T23,T65,T71
IntegDigClrSt->IdleSt	443	Excluded
IntegDigClrSt->IntegDigSt	434	Excluded	T1,T2,T3
IntegDigClrSt->IntegScrSt	427	Not Covered
IntegDigFinSt->ErrorSt	596	Not Covered
IntegDigFinSt->IntegDigWaitSt	532	Covered	T1,T2,T3
IntegDigPadSt->ErrorSt	596	Excluded	T70
IntegDigPadSt->IntegDigFinSt	520	Excluded	T1,T2,T3
IntegDigSt->ErrorSt	596	Not Covered
IntegDigSt->IntegDigFinSt	491	Not Covered
IntegDigSt->IntegDigPadSt	493	Excluded	T1,T2,T3
IntegDigSt->IntegScrSt	504	Not Covered
IntegDigWaitSt->ErrorSt	560	Covered	T44,T45,T46
IntegDigWaitSt->IdleSt	548	Covered	T1,T2,T3
IntegScrSt->ErrorSt	596	Not Covered
IntegScrSt->IntegScrWaitSt	460	Not Covered
IntegScrWaitSt->ErrorSt	596	Not Covered
IntegScrWaitSt->IntegDigSt	470	Not Covered
ResetSt->ErrorSt	596	Covered	T13,T74,T75
ResetSt->InitSt	246	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	5	4	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
CheckFailError	374	Covered	T44,T45,T46
FsmStateError	574	Covered	T9,T10,T12
MacroEccCorrError	283	Covered	T31,T41,T39
NoError	573	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
CheckFailError->FsmStateError	606	Excluded
CheckFailError->MacroEccCorrError	283	Excluded
FsmStateError->CheckFailError	374	Excluded
FsmStateError->MacroEccCorrError	283	Excluded
MacroEccCorrError->CheckFailError	374	Not Covered
MacroEccCorrError->FsmStateError	606	Covered	T31,T39,T20
NoError->CheckFailError	374	Covered	T44,T45,T46
NoError->FsmStateError	574	Covered	T9,T10,T12
NoError->MacroEccCorrError	283	Covered	T31,T41,T39

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
Branches		70	50	71.43
TERNARY	636	2	2	100.00
TERNARY	652	2	2	100.00
TERNARY	678	2	2	100.00
TERNARY	709	2	2	100.00
CASE	240	52	34	65.38
IF	595	3	1	33.33
IF	602	3	3	100.00
IF	750	2	2	100.00
IF	753	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	636	((base_sel == DigOffset)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	652	((data_sel == ScrmblData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	678	(init_done_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	709	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	240	case (state_q)
-2-:	245	if (init_req_i)
-3-:	255	if (otp_gnt_i)
-4-:	265	if (otp_rvalid_i)
-5-:	267	if ((otp_err inside {NoError, MacroEccCorrError}))
-6-:	271	if ((cnt == LastScrmblBlock))
-7-:	275	if (1'b0)
-8-:	282	if ((otp_err != NoError))
-9-:	302	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-10-:	314	if (scrmbl_valid_i)
-11-:	324	if (integ_chk_req_i)
-12-:	325	if (1'b1)
-13-:	333	if (cnsty_chk_req_i)
-14-:	348	if (1'b1)
-15-:	351	if (otp_gnt_i)
-16-:	362	if (otp_rvalid_i)
-17-:	363	if ((otp_err inside {NoError, MacroEccCorrError}))
-18-:	366	if (1'b1)
-19-:	368	if (((digest_o == data_mux) || (digest_o == '0)))
-20-:	381	if (((scrmbl_data_o == data_mux) || lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i)))
-21-:	385	if ((cnt == LastScrmblBlock))
-22-:	401	if ((otp_err != NoError))
-23-:	417	if (1'b1)
-24-:	424	if (1'b0)
-25-:	426	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-26-:	433	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-27-:	444	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-28-:	459	if (scrmbl_ready_i)
-29-:	469	if (scrmbl_valid_i)
-30-:	482	if (scrmbl_ready_i)
-31-:	485	if ((cnt == PenultimateScrmblBlock))
-32-:	489	if (cnt[0])
-33-:	498	if (cnt[0])
-34-:	503	if (1'b0)
-35-:	519	if (scrmbl_ready_i)
-36-:	531	if (scrmbl_ready_i)
-37-:	544	if (scrmbl_valid_i)
-38-:	547	if (((digest_o == data_mux) || (digest_o == '0)))
-39-:	551	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-40-:	573	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitWaitSt	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T31,T39,T20
InitWaitSt	-	-	1	1	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T80,T81,T82
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrSt	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitDescrSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitDescrWaitSt	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitDescrWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	-	-	-	-	-	-	-	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T41,T42,T43
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T48
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	1	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	0	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	Covered	T1,T2,T3
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	Covered	T1,T3,T4
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T44,T45,T46
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T28,T29,T30
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T9,T10,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	595	if (ecc_err)
-2-:	597	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	602	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	605	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T9,T10,T12
1	0	Covered	T9,T10,T12
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	753	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	34	33	97.06	28	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	34	33	97.06	28	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	1584582250	1583735421	0	0
BypassEnable0_A	1584582250	0	0	0
BypassEnable1_A	1584582250	1583735421	0	0
CnstyChkAckKnown_A	1584582250	1583735421	0	0
DataKnown_A	1584582250	1583735421	0	0
DigestKnown_A	1584582250	1583735421	0	0
DigestOffsetMustBeRepresentable_A	1127	1127	0	0
EccErrorState_A	1584582250	0	0	0
ErrorKnown_A	1584582250	1583735421	0	0
InitDoneKnown_A	1584582250	1583735421	0	0
InitReadLocksPartition_A	1584582250	294763624	0	0
InitWriteLocksPartition_A	1584582250	294763624	0	0
IntegChkAckKnown_A	1584582250	1583735421	0	0
OffsetMustBeBlockAligned_A	1127	1127	0	0
OtpAddrKnown_A	1584582250	1583735421	0	0
OtpCmdKnown_A	1584582250	1583735421	0	0
OtpErrorState_A	0	0	0	0
OtpReqKnown_A	1584582250	1583735421	0	0
OtpSizeKnown_A	1584582250	1583735421	0	0
OtpWdataKnown_A	1584582250	1583735421	0	0
ReadLockImpliesDigest_A	1584582250	1583735421	0	0
ReadLockPropagation_A	1584582250	0	0	0
ScrambledImpliesDigest_A	1584582250	0	0	0
ScrmblCmdKnown_A	1584582250	1583735421	0	0
ScrmblDataKnown_A	1584165760	1583318931	0	0
ScrmblModeKnown_A	1584582250	1583735421	0	0
ScrmblMtxReqKnown_A	1584582250	1583735421	0	0
ScrmblSelKnown_A	1584582250	1583735421	0	0
ScrmblValidKnown_A	1584582250	1583735421	0	0
SizeMustBeBlockAligned_A	1127	1127	0	0
WriteLockImpliesDigest_A	1584582250	0	0	0
WriteLockPropagation_A	1584582250	2651529	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	1584582250	32972958	0	0
u_state_regs_A	1584582250	1583735421	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

BypassEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	0	0	0

BypassEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

CnstyChkAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	294763624	0	0
T1	187260	12504	0	0
T2	11915	1005	0	0
T3	13072	1028	0	0
T4	44826	2629	0	0
T9	83429	73924	0	0
T10	11172	4309	0	0
T11	4848	361	0	0
T12	15054	6863	0	0
T13	14393	5541	0	0
T14	12081	4774	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	294763624	0	0
T1	187260	12504	0	0
T2	11915	1005	0	0
T3	13072	1028	0	0
T4	44826	2629	0	0
T9	83429	73924	0	0
T10	11172	4309	0	0
T11	4848	361	0	0
T12	15054	6863	0	0
T13	14393	5541	0	0
T14	12081	4774	0	0

IntegChkAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

ReadLockImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	0	0	0

ScrambledImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	0	0	0

ScrmblCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

ScrmblDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584165760	1583318931	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

ScrmblModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

ScrmblMtxReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

ScrmblSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

ScrmblValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

WriteLockImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	0	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	2651529	0	0
T1	187260	6677	0	0
T2	11915	0	0	0
T3	13072	0	0	0
T4	44826	0	0	0
T9	83429	0	0	0
T10	11172	0	0	0
T11	4848	0	0	0
T12	15054	0	0	0
T13	14393	0	0	0
T14	12081	0	0	0
T40	0	4240	0	0
T65	0	10564	0	0
T93	0	7660	0	0
T94	0	18875	0	0
T95	0	629	0	0
T97	0	9205	0	0
T98	0	2179	0	0
T102	0	26655	0	0
T111	0	3613	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	32972958	0	0
T1	187260	124252	0	0
T2	11915	3071	0	0
T3	13072	2966	0	0
T4	44826	0	0	0
T9	83429	0	0	0
T10	11172	0	0	0
T11	4848	0	0	0
T12	15054	0	0	0
T13	14393	2745	0	0
T14	12081	0	0	0
T22	0	397225	0	0
T23	0	7270	0	0
T44	0	3931	0	0
T51	0	3988	0	0
T103	0	7777	0	0
T104	0	4891	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0