Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18999	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

39909

1

T1

17

T2

30

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	22412	1			T1	20		T2	11		T3	11
values[0x0]	17531	1			T1	12		T2	25		T3	5
values[0x1]	18965	1			T1	8		T2	21		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14178	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

44730

1

T1

18

T2

36

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	235	1			T9	13		T5	4		T12	1
valid_sources[0x01]	506	1			T4	17		T9	8		T6	3
valid_sources[0x02]	269	1			T9	8		T10	5		T6	3
valid_sources[0x03]	200	1			T9	17		T6	3		T7	2
valid_sources[0x04]	188	1			T9	5		T6	3		T7	6
valid_sources[0x05]	237	1			T4	5		T9	10		T6	4
valid_sources[0x06]	218	1			T4	1		T9	10		T6	2
valid_sources[0x07]	289	1			T4	10		T9	9		T16	4
valid_sources[0x08]	172	1			T4	12		T9	8		T6	1
valid_sources[0x09]	297	1			T4	20		T9	8		T12	1
valid_sources[0x0a]	494	1			T9	9		T6	1		T7	8
valid_sources[0x0b]	206	1			T9	8		T6	1		T11	1
valid_sources[0x0c]	227	1			T9	21		T6	4		T19	1
valid_sources[0x0d]	187	1			T9	9		T16	4		T11	1
valid_sources[0x0e]	356	1			T3	1		T4	16		T9	11
valid_sources[0x0f]	264	1			T9	8		T6	1		T19	2
valid_sources[0x10]	258	1			T9	11		T12	2		T6	1
valid_sources[0x11]	260	1			T9	9		T6	1		T19	1
valid_sources[0x12]	247	1			T9	8		T6	2		T11	1
valid_sources[0x13]	458	1			T4	3		T9	4		T12	1
valid_sources[0x14]	176	1			T9	5		T6	3		T16	1
valid_sources[0x15]	162	1			T4	10		T9	8		T6	2
valid_sources[0x16]	240	1			T9	13		T6	1		T19	1
valid_sources[0x17]	251	1			T9	9		T7	14		T16	6
valid_sources[0x18]	160	1			T9	5		T6	3		T27	9
valid_sources[0x19]	217	1			T9	11		T6	1		T7	3
valid_sources[0x1a]	233	1			T4	15		T9	4		T12	1
valid_sources[0x1b]	426	1			T9	7		T7	3		T27	8
valid_sources[0x1c]	239	1			T9	11		T6	2		T16	1
valid_sources[0x1d]	238	1			T4	8		T9	6		T6	5
valid_sources[0x1e]	226	1			T9	11		T12	1		T6	3
valid_sources[0x1f]	187	1			T3	11		T4	1		T9	5
valid_sources[0x20]	180	1			T4	6		T9	14		T12	1
valid_sources[0x21]	303	1			T9	10		T6	4		T27	12
valid_sources[0x22]	228	1			T9	8		T12	1		T6	1
valid_sources[0x23]	248	1			T9	7		T12	1		T6	2
valid_sources[0x24]	182	1			T4	12		T9	5		T6	7
valid_sources[0x25]	194	1			T9	6		T12	3		T6	4
valid_sources[0x26]	260	1			T9	11		T12	1		T6	2
valid_sources[0x27]	207	1			T9	7		T6	2		T7	2
valid_sources[0x28]	216	1			T9	16		T19	3		T27	11
valid_sources[0x29]	217	1			T4	2		T9	17		T16	23
valid_sources[0x2a]	295	1			T9	7		T5	9		T6	1
valid_sources[0x2b]	274	1			T9	7		T12	2		T6	2
valid_sources[0x2c]	158	1			T9	6		T6	4		T7	4
valid_sources[0x2d]	189	1			T4	2		T9	17		T6	5
valid_sources[0x2e]	320	1			T9	16		T6	2		T7	7
valid_sources[0x2f]	219	1			T4	1		T9	15		T6	1
valid_sources[0x30]	157	1			T9	10		T6	5		T11	1
valid_sources[0x31]	169	1			T9	13		T5	3		T6	1
valid_sources[0x32]	166	1			T9	8		T6	4		T7	2
valid_sources[0x33]	254	1			T9	14		T6	8		T7	2
valid_sources[0x34]	254	1			T9	9		T6	4		T27	5
valid_sources[0x35]	210	1			T4	4		T9	5		T6	7
valid_sources[0x36]	161	1			T9	5		T12	2		T6	8
valid_sources[0x37]	195	1			T9	10		T6	3		T16	8
valid_sources[0x38]	278	1			T9	6		T6	4		T16	7
valid_sources[0x39]	200	1			T2	5		T9	5		T6	2
valid_sources[0x3a]	229	1			T9	12		T7	9		T27	9
valid_sources[0x3b]	176	1			T9	12		T6	3		T19	1
valid_sources[0x3c]	199	1			T9	12		T6	3		T11	1
valid_sources[0x3d]	196	1			T9	5		T16	7		T19	1
valid_sources[0x3e]	168	1			T9	7		T19	2		T27	7
valid_sources[0x3f]	193	1			T9	7		T5	9		T6	1
valid_sources[0x40]	218	1			T9	10		T10	12		T19	2
valid_sources[0x41]	356	1			T9	14		T6	1		T7	19
valid_sources[0x42]	212	1			T4	9		T9	6		T6	4
valid_sources[0x43]	291	1			T9	4		T16	25		T27	14
valid_sources[0x44]	236	1			T4	10		T9	8		T6	3
valid_sources[0x45]	172	1			T4	1		T9	8		T6	1
valid_sources[0x46]	317	1			T9	13		T6	1		T16	4
valid_sources[0x47]	191	1			T9	9		T12	1		T6	4
valid_sources[0x48]	249	1			T9	11		T6	1		T27	9
valid_sources[0x49]	172	1			T9	8		T6	4		T19	2
valid_sources[0x4a]	267	1			T9	8		T5	48		T6	4
valid_sources[0x4b]	163	1			T9	7		T6	3		T7	12
valid_sources[0x4c]	203	1			T4	10		T9	6		T6	1
valid_sources[0x4d]	191	1			T9	16		T6	2		T7	7
valid_sources[0x4e]	291	1			T9	7		T6	3		T16	4
valid_sources[0x4f]	147	1			T9	4		T6	4		T7	1
valid_sources[0x50]	192	1			T9	9		T6	2		T27	8
valid_sources[0x51]	238	1			T4	12		T9	9		T12	2
valid_sources[0x52]	208	1			T9	11		T6	2		T16	11
valid_sources[0x53]	195	1			T9	9		T6	7		T27	24
valid_sources[0x54]	221	1			T9	8		T6	2		T27	8
valid_sources[0x55]	275	1			T9	9		T6	1		T7	13
valid_sources[0x56]	279	1			T9	9		T6	1		T27	14
valid_sources[0x57]	198	1			T9	11		T12	2		T6	4
valid_sources[0x58]	279	1			T9	11		T19	3		T27	13
valid_sources[0x59]	247	1			T4	7		T9	9		T16	2
valid_sources[0x5a]	200	1			T4	9		T9	9		T27	6
valid_sources[0x5b]	157	1			T9	7		T6	1		T19	2
valid_sources[0x5c]	211	1			T9	6		T6	2		T27	5
valid_sources[0x5d]	291	1			T4	4		T9	11		T6	9
valid_sources[0x5e]	179	1			T9	4		T10	4		T12	1
valid_sources[0x5f]	198	1			T9	9		T6	3		T7	2
valid_sources[0x60]	232	1			T4	2		T9	8		T6	1
valid_sources[0x61]	211	1			T4	1		T9	10		T6	3
valid_sources[0x62]	229	1			T9	11		T6	4		T27	8
valid_sources[0x63]	152	1			T9	10		T12	1		T6	1
valid_sources[0x64]	252	1			T9	3		T6	3		T7	4
valid_sources[0x65]	236	1			T9	10		T6	1		T16	1
valid_sources[0x66]	185	1			T4	11		T9	13		T6	2
valid_sources[0x67]	223	1			T9	9		T10	1		T12	1
valid_sources[0x68]	200	1			T9	11		T19	2		T27	9
valid_sources[0x69]	211	1			T9	9		T6	1		T16	14
valid_sources[0x6a]	219	1			T9	8		T12	1		T6	2
valid_sources[0x6b]	219	1			T2	29		T9	10		T6	4
valid_sources[0x6c]	310	1			T4	2		T9	14		T27	12
valid_sources[0x6d]	251	1			T9	10		T12	2		T6	1
valid_sources[0x6e]	231	1			T9	8		T12	1		T6	3
valid_sources[0x6f]	176	1			T9	10		T6	3		T19	1
valid_sources[0x70]	168	1			T9	5		T6	2		T19	1
valid_sources[0x71]	237	1			T9	9		T5	49		T6	1
valid_sources[0x72]	202	1			T4	6		T9	6		T16	9
valid_sources[0x73]	185	1			T9	6		T6	7		T11	1
valid_sources[0x74]	172	1			T9	6		T6	2		T26	1
valid_sources[0x75]	152	1			T9	6		T12	1		T6	1
valid_sources[0x76]	237	1			T9	7		T12	1		T6	1
valid_sources[0x77]	205	1			T9	8		T6	2		T16	9
valid_sources[0x78]	231	1			T9	9		T6	2		T27	8
valid_sources[0x79]	179	1			T9	11		T6	1		T27	4
valid_sources[0x7a]	206	1			T9	11		T6	5		T11	1
valid_sources[0x7b]	235	1			T9	5		T6	3		T11	2
valid_sources[0x7c]	187	1			T9	15		T10	5		T12	2
valid_sources[0x7d]	272	1			T9	7		T27	3		T30	1
valid_sources[0x7e]	196	1			T9	8		T16	11		T11	1
valid_sources[0x7f]	406	1			T9	7		T6	4		T16	3
valid_sources[0x80]	164	1			T4	8		T9	6		T19	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

12448

1

T1

9

T2

3

T3

5

values[0x0]

all_enables

biggest_size

14065

1

T1

7

T2

17

T3

2

values[0x1]

all_enables

biggest_size

13396

1

T1

1

T2

10

T4

167

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14412	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

22910

1

T2

7

T4

82

T9

1257

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	20646	1			T2	31		T4	240		T9	1024
values[0x0]	8146	1			T2	5		T4	41		T9	491
values[0x1]	8530	1			T2	3		T4	41		T9	532

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9969	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

27353

1

T2

18

T4

164

T9

1430

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	91	1			T9	9		T6	7		T7	1
valid_sources[0x01]	253	1			T9	10		T6	4		T7	6
valid_sources[0x02]	114	1			T9	11		T7	1		T20	1
valid_sources[0x03]	180	1			T2	1		T9	8		T16	3
valid_sources[0x04]	150	1			T4	1		T9	11		T6	4
valid_sources[0x05]	161	1			T4	10		T9	7		T7	1
valid_sources[0x06]	108	1			T4	1		T9	9		T20	2
valid_sources[0x07]	112	1			T4	2		T9	7		T7	2
valid_sources[0x08]	161	1			T9	12		T6	3		T7	3
valid_sources[0x09]	163	1			T4	5		T9	12		T6	6
valid_sources[0x0a]	118	1			T4	8		T9	7		T7	1
valid_sources[0x0b]	87	1			T2	2		T9	10		T7	3
valid_sources[0x0c]	130	1			T9	6		T7	2		T20	2
valid_sources[0x0d]	98	1			T4	4		T9	12		T16	1
valid_sources[0x0e]	117	1			T2	2		T9	9		T7	1
valid_sources[0x0f]	96	1			T4	5		T9	6		T7	2
valid_sources[0x10]	208	1			T4	1		T9	10		T7	2
valid_sources[0x11]	133	1			T4	2		T9	7		T7	1
valid_sources[0x12]	115	1			T4	3		T9	6		T7	3
valid_sources[0x13]	187	1			T9	9		T7	3		T13	12
valid_sources[0x14]	115	1			T4	4		T9	5		T7	1
valid_sources[0x15]	126	1			T9	8		T6	3		T7	2
valid_sources[0x16]	188	1			T4	4		T9	8		T6	3
valid_sources[0x17]	100	1			T9	9		T6	3		T7	2
valid_sources[0x18]	91	1			T2	2		T9	6		T6	1
valid_sources[0x19]	288	1			T4	2		T9	10		T7	2
valid_sources[0x1a]	132	1			T4	3		T9	6		T7	4
valid_sources[0x1b]	148	1			T4	1		T9	8		T7	3
valid_sources[0x1c]	157	1			T9	9		T6	1		T7	3
valid_sources[0x1d]	111	1			T9	9		T20	2		T14	2
valid_sources[0x1e]	124	1			T4	4		T9	10		T6	3
valid_sources[0x1f]	178	1			T4	1		T9	3		T20	2
valid_sources[0x20]	132	1			T4	1		T9	6		T7	3
valid_sources[0x21]	141	1			T9	6		T7	2		T20	1
valid_sources[0x22]	114	1			T4	3		T9	8		T7	1
valid_sources[0x23]	106	1			T9	13		T7	1		T16	3
valid_sources[0x24]	112	1			T9	9		T7	1		T21	8
valid_sources[0x25]	179	1			T4	2		T9	7		T31	1
valid_sources[0x26]	126	1			T4	7		T9	8		T12	4
valid_sources[0x27]	155	1			T9	7		T7	1		T21	1
valid_sources[0x28]	160	1			T9	6		T6	2		T7	3
valid_sources[0x29]	96	1			T9	10		T7	3		T16	2
valid_sources[0x2a]	142	1			T9	8		T6	6		T7	2
valid_sources[0x2b]	126	1			T4	2		T9	5		T7	5
valid_sources[0x2c]	137	1			T9	8		T7	3		T29	15
valid_sources[0x2d]	241	1			T4	1		T9	6		T7	3
valid_sources[0x2e]	125	1			T9	7		T7	1		T29	20
valid_sources[0x2f]	160	1			T9	4		T7	2		T19	1
valid_sources[0x30]	84	1			T9	7		T7	2		T16	1
valid_sources[0x31]	103	1			T9	9		T5	23		T7	1
valid_sources[0x32]	128	1			T4	8		T9	5		T7	2
valid_sources[0x33]	225	1			T9	8		T7	3		T30	18
valid_sources[0x34]	120	1			T9	9		T7	1		T31	3
valid_sources[0x35]	151	1			T9	4		T7	1		T20	2
valid_sources[0x36]	147	1			T9	8		T6	1		T7	1
valid_sources[0x37]	128	1			T9	11		T7	3		T16	1
valid_sources[0x38]	168	1			T9	3		T7	1		T17	38
valid_sources[0x39]	121	1			T2	2		T9	7		T7	3
valid_sources[0x3a]	158	1			T4	1		T9	9		T7	2
valid_sources[0x3b]	104	1			T9	7		T7	3		T20	2
valid_sources[0x3c]	122	1			T9	10		T7	3		T19	4
valid_sources[0x3d]	143	1			T4	5		T9	6		T6	5
valid_sources[0x3e]	136	1			T4	2		T9	7		T6	7
valid_sources[0x3f]	107	1			T4	1		T9	11		T16	3
valid_sources[0x40]	278	1			T2	2		T4	3		T9	7
valid_sources[0x41]	103	1			T4	5		T9	12		T19	5
valid_sources[0x42]	155	1			T4	1		T9	7		T6	2
valid_sources[0x43]	203	1			T4	6		T9	10		T6	6
valid_sources[0x44]	104	1			T2	1		T4	3		T9	11
valid_sources[0x45]	1079	1			T9	11		T6	4		T7	3
valid_sources[0x46]	90	1			T9	5		T7	1		T20	1
valid_sources[0x47]	123	1			T4	1		T9	11		T6	3
valid_sources[0x48]	123	1			T9	9		T16	3		T14	1
valid_sources[0x49]	107	1			T2	1		T9	10		T6	7
valid_sources[0x4a]	187	1			T4	11		T9	5		T19	14
valid_sources[0x4b]	178	1			T9	8		T7	2		T21	1
valid_sources[0x4c]	100	1			T4	5		T9	8		T6	12
valid_sources[0x4d]	169	1			T4	1		T9	11		T7	1
valid_sources[0x4e]	112	1			T4	1		T9	4		T6	5
valid_sources[0x4f]	104	1			T9	8		T7	1		T16	1
valid_sources[0x50]	159	1			T9	9		T7	3		T20	1
valid_sources[0x51]	133	1			T4	5		T9	17		T7	4
valid_sources[0x52]	120	1			T9	7		T7	2		T30	30
valid_sources[0x53]	70	1			T9	4		T6	1		T7	3
valid_sources[0x54]	108	1			T9	12		T6	8		T7	1
valid_sources[0x55]	206	1			T4	10		T9	9		T7	3
valid_sources[0x56]	138	1			T4	6		T9	11		T7	5
valid_sources[0x57]	188	1			T9	2		T6	9		T7	2
valid_sources[0x58]	84	1			T9	8		T7	4		T32	3
valid_sources[0x59]	138	1			T9	11		T7	3		T19	3
valid_sources[0x5a]	207	1			T2	1		T9	10		T7	1
valid_sources[0x5b]	184	1			T9	6		T7	1		T20	1
valid_sources[0x5c]	139	1			T9	11		T7	2		T20	2
valid_sources[0x5d]	176	1			T9	10		T6	28		T7	4
valid_sources[0x5e]	116	1			T9	9		T6	8		T7	2
valid_sources[0x5f]	127	1			T2	1		T9	11		T7	2
valid_sources[0x60]	106	1			T9	9		T7	2		T20	2
valid_sources[0x61]	133	1			T9	3		T16	2		T31	2
valid_sources[0x62]	139	1			T4	1		T9	8		T5	41
valid_sources[0x63]	110	1			T9	8		T7	1		T20	1
valid_sources[0x64]	174	1			T2	2		T4	1		T9	7
valid_sources[0x65]	143	1			T9	7		T7	2		T19	2
valid_sources[0x66]	75	1			T2	1		T9	6		T7	2
valid_sources[0x67]	157	1			T9	5		T7	5		T19	8
valid_sources[0x68]	323	1			T4	2		T9	5		T7	5
valid_sources[0x69]	178	1			T9	8		T6	11		T7	2
valid_sources[0x6a]	173	1			T4	1		T9	6		T7	1
valid_sources[0x6b]	125	1			T4	2		T9	9		T7	2
valid_sources[0x6c]	125	1			T9	3		T5	4		T7	4
valid_sources[0x6d]	227	1			T9	2		T7	5		T32	1
valid_sources[0x6e]	113	1			T9	15		T6	1		T7	2
valid_sources[0x6f]	166	1			T4	2		T9	11		T7	2
valid_sources[0x70]	124	1			T4	7		T9	8		T7	1
valid_sources[0x71]	120	1			T4	2		T9	4		T6	2
valid_sources[0x72]	121	1			T4	4		T9	6		T6	2
valid_sources[0x73]	87	1			T2	1		T9	6		T20	1
valid_sources[0x74]	161	1			T9	3		T7	5		T52	1
valid_sources[0x75]	139	1			T9	10		T7	3		T20	3
valid_sources[0x76]	180	1			T4	5		T9	13		T7	2
valid_sources[0x77]	184	1			T2	3		T9	3		T7	1
valid_sources[0x78]	124	1			T4	3		T9	5		T7	1
valid_sources[0x79]	165	1			T4	5		T9	10		T7	4
valid_sources[0x7a]	174	1			T4	4		T9	3		T7	1
valid_sources[0x7b]	106	1			T9	16		T7	2		T16	1
valid_sources[0x7c]	169	1			T9	6		T7	2		T21	11
valid_sources[0x7d]	129	1			T4	1		T9	8		T7	2
valid_sources[0x7e]	99	1			T9	9		T7	2		T16	2
valid_sources[0x7f]	179	1			T9	6		T7	1		T16	2
valid_sources[0x80]	225	1			T4	1		T9	7		T7	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8649

1

T2

1

T4

19

T9

518

values[0x0]

all_enables

biggest_size

7350

1

T2

3

T4

34

T9

392

values[0x1]

all_enables

biggest_size

6911

1

T2

3

T4

29

T9

347