Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

35850

1

T1

23

T2

27

T3

15

full_word

40858

1

T1

17

T2

30

T3

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	76398	1			T1	40		T2	57		T3	22
auto[TlIntgErrCmd]	98	1			T4	3		T6	2		T17	6
auto[TlIntgErrData]	109	1			T4	4		T6	3		T17	8
auto[TlIntgErrBoth]	103	1			T4	3		T6	5		T17	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23595

1

T1

20

T2

11

T3

11

auto[1]

53113

1

T1

20

T2

46

T3

11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	10910	1			T1	11		T2	8		T3	6
auto[TlIntgErrNone]	partial	auto[1]	24655	1			T1	12		T2	19		T3	9
auto[TlIntgErrNone]	full_word	auto[0]	12537	1			T1	9		T2	3		T3	5
auto[TlIntgErrNone]	full_word	auto[1]	28296	1			T1	8		T2	27		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T4	2		T6	2		T17	4
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T4	1		T17	1		T78	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T17	1		T82	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T75	1		T74	2		T64	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T4	3		T6	3		T17	4
auto[TlIntgErrData]	partial	auto[1]	47	1			T4	1		T17	4		T28	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T78	1		T74	1		T83	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T78	1		T81	1		T80	2
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T4	1		T6	3		T17	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T4	2		T6	1		T17	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T6	1		T17	1		T75	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T28	1		T79	1		T75	1