Module Definition
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Module : prim_packer_fifo
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_edn_req.u_prim_packer_fifo 0.00 0.00 0.00 0.00


Module Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 u_prim_edn_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_packer_fifo
Line No.TotalCoveredPercent
TOTAL1700.00
ALWAYS81700.00
CONT_ASSIGN9300
CONT_ASSIGN95100.00
CONT_ASSIGN100100.00
CONT_ASSIGN101100.00
CONT_ASSIGN102100.00
CONT_ASSIGN103100.00
CONT_ASSIGN105100.00
CONT_ASSIGN109100.00
CONT_ASSIGN114100.00
CONT_ASSIGN115100.00
CONT_ASSIGN116100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
81 0 1
82 0 1
83 0 1
84 0 1
86 0 1
87 0 1
88 0 1
93 unreachable
95 0 1
100 0 1
101 0 1
102 0 1
103 0 1
105 0 1
109 0 1
114 0 1
115 0 1
116 0 1

Cond Coverage for Module : prim_packer_fifo
TotalCoveredPercent
Conditions3000.00
Logical3000.00
Non-Logical00
Event00

 LINE       101
 EXPRESSION ((rready_i && rvalid_o) || clr_q)
             -----------1----------    --2--
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       101
 SUB-EXPRESSION (rready_i && rvalid_o)
                 ----1---    ----2---
-1--2-StatusTests
01Unreachable
10Not Covered
11Not Covered 

 LINE       102
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00Not Covered
01Not Covered
10Unreachable 

 LINE       103
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       105
 EXPRESSION (clear_status ? '0 : (load_data ? ((depth_q + 1)) : depth_q))
             ------1-----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       105
 SUB-EXPRESSION (load_data ? ((depth_q + 1)) : depth_q)
                 ----1----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       109
 EXPRESSION (clear_data ? '0 : (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q))
             -----1----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       109
 SUB-EXPRESSION (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q)
                 ----1----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       114
 EXPRESSION (( ! (depth_q == FullDepth) ) && ((!clr_q)))
             --------------1-------------    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       114
 SUB-EXPRESSION ( ! (depth_q == FullDepth) )
                    -----------1----------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       114
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       116
 EXPRESSION ((depth_q == FullDepth) && ((!clr_q)))
             -----------1----------    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       116
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------
-1-StatusTests
0Not Covered
1Not Covered
Branch Coverage for Module : prim_packer_fifo
Line No.TotalCoveredPercent
Branches 8 0 0.00
TERNARY 105 3 0 0.00
TERNARY 109 3 0 0.00
IF 81 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	105	(clear_status) ? 
-2-:	105	(load_data) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	109	(clear_data) ? 
-2-:	109	(load_data) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo
Line No.TotalCoveredPercent
TOTAL1700.00
ALWAYS81700.00
CONT_ASSIGN9300
CONT_ASSIGN95100.00
CONT_ASSIGN100100.00
CONT_ASSIGN101100.00
CONT_ASSIGN102100.00
CONT_ASSIGN103100.00
CONT_ASSIGN105100.00
CONT_ASSIGN109100.00
CONT_ASSIGN114100.00
CONT_ASSIGN115100.00
CONT_ASSIGN116100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
81 0 1
82 0 1
83 0 1
84 0 1
86 0 1
87 0 1
88 0 1
93 unreachable
95 0 1
100 0 1
101 0 1
102 0 1
103 0 1
105 0 1
109 0 1
114 0 1
115 0 1
116 0 1

Cond Coverage for Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo
TotalCoveredPercent
Conditions2900.00
Logical2900.00
Non-Logical00
Event00

 LINE       101
 EXPRESSION ((rready_i && rvalid_o) || clr_q)
             -----------1----------    --2--
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       101
 SUB-EXPRESSION (rready_i && rvalid_o)
                 ----1---    ----2---
-1--2-StatusTests
01Unreachable
10Not Covered
11Not Covered 

 LINE       102
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00Not Covered
01Not Covered
10Unreachable 

 LINE       103
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       105
 EXPRESSION (clear_status ? '0 : (load_data ? ((depth_q + 1)) : depth_q))
             ------1-----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       105
 SUB-EXPRESSION (load_data ? ((depth_q + 1)) : depth_q)
                 ----1----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       109
 EXPRESSION (clear_data ? '0 : (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q))
             -----1----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       109
 SUB-EXPRESSION (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q)
                 ----1----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       114
 EXPRESSION (( ! (depth_q == FullDepth) ) && ((!clr_q)))
             --------------1-------------    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       114
 SUB-EXPRESSION ( ! (depth_q == FullDepth) )
                    -----------1----------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       114
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       116
 EXPRESSION ((depth_q == FullDepth) && ((!clr_q)))
             -----------1----------    -----2----
-1--2-StatusTestsExclude Annotation
01Not Covered
10Excluded VC_COV_UNR
11Not Covered 

 LINE       116
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------
-1-StatusTests
0Not Covered
1Not Covered
Branch Coverage for Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo
Line No.TotalCoveredPercent
Branches 8 0 0.00
TERNARY 105 3 0 0.00
TERNARY 109 3 0 0.00
IF 81 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	105	(clear_status) ? 
-2-:	105	(load_data) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	109	(clear_data) ? 
-2-:	109	(load_data) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

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