Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1457020
Category 01457020


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1457020
Severity 01457020


Summary for Assertions
NUMBERPERCENT
Total Number1457100.00
Uncovered543.71
Success140396.29
Failure00.00
Incomplete110.75
Without Attempts50.34


Summary for Cover Sequences
NUMBERPERCENT
Total Number20100.00
Uncovered00.00
All Matches20100.00
First Matches20100.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_otp_ctrl_dai.PartInitReqKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_dai.PartSelMustBeOnehot_A 0046277291446183024000
tb.dut.u_otp_ctrl_dai.ScrmblBlockWidthGe8_A 0046277291446183024000
tb.dut.u_otp_ctrl_dai.ScrmblCmdKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_dai.ScrmblDataKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_dai.ScrmblModeKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_dai.ScrmblMtxReqKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_dai.ScrmblSelKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_dai.ScrmblValidKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_dai.gen_part_sel[0].PartEndMax_A 001155115500
tb.dut.u_otp_ctrl_dai.gen_part_sel[10].PartEndMax_A 001155115500
tb.dut.u_otp_ctrl_dai.gen_part_sel[1].PartEndMax_A 001155115500
tb.dut.u_otp_ctrl_dai.gen_part_sel[2].PartEndMax_A 001155115500
tb.dut.u_otp_ctrl_dai.gen_part_sel[3].PartEndMax_A 001155115500
tb.dut.u_otp_ctrl_dai.gen_part_sel[4].PartEndMax_A 001155115500
tb.dut.u_otp_ctrl_dai.gen_part_sel[5].PartEndMax_A 001155115500
tb.dut.u_otp_ctrl_dai.gen_part_sel[6].PartEndMax_A 001155115500
tb.dut.u_otp_ctrl_dai.gen_part_sel[7].PartEndMax_A 001155115500
tb.dut.u_otp_ctrl_dai.gen_part_sel[8].PartEndMax_A 001155115500
tb.dut.u_otp_ctrl_dai.gen_part_sel[9].PartEndMax_A 001155115500
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.CheckHotOne_A 0046277291446183024000
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.CheckNGreaterZero_A 001155115500
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.GrantKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.IdxKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.Priority_A 0046277291446183024000
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ReqImpliesValid_A 0046277291446183024000
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ValidKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_dai.u_state_regs.AssertConnected_A 001155115500
tb.dut.u_otp_ctrl_dai.u_state_regs_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.EdnReqKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.EntropyWidthDividesDigestBlockWidth_A 001155115500
tb.dut.u_otp_ctrl_kdi.FlashOtpKeyRspKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.FsmErrKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.KeyNonceSize0_A 001155115500
tb.dut.u_otp_ctrl_kdi.KeyNonceSize1_A 001155115500
tb.dut.u_otp_ctrl_kdi.KeyNonceSize2_A 001155115500
tb.dut.u_otp_ctrl_kdi.KeyNonceSize3_A 001155115500
tb.dut.u_otp_ctrl_kdi.KeyNonceSize4_A 001155115500
tb.dut.u_otp_ctrl_kdi.KeyNonceSize5_A 001155115500
tb.dut.u_otp_ctrl_kdi.KeyNonceSize6_A 001155115500
tb.dut.u_otp_ctrl_kdi.NonceWidth_A 001155115500
tb.dut.u_otp_ctrl_kdi.OtbnOtpKeyRspKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.ScrmblCmdKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.ScrmblDataKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.ScrmblModeKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.ScrmblMtxReqKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.ScrmblSelKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.ScrmblValidKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.SramOtpKeyRspKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.u_req_arb.CheckHotOne_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.u_req_arb.CheckNGreaterZero_A 001155115500
tb.dut.u_otp_ctrl_kdi.u_req_arb.GntImpliesReady_A 004627729144767500
tb.dut.u_otp_ctrl_kdi.u_req_arb.GntImpliesValid_A 004627729144767500
tb.dut.u_otp_ctrl_kdi.u_req_arb.GrantKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.u_req_arb.IdxKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.u_req_arb.IndexIsCorrect_A 004627729144767500
tb.dut.u_otp_ctrl_kdi.u_req_arb.LockArbDecision_A 004627729147701334800
tb.dut.u_otp_ctrl_kdi.u_req_arb.NoReadyValidNoGrant_A 0046277291438476689900
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReadyAndValidImplyGrant_A 004627729144767500
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqAndReadyImplyGrant_A 004627729144767500
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqImpliesValid_A 004627729147706334100
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqStaysHighUntilGranted0_M 004627729147701334800
tb.dut.u_otp_ctrl_kdi.u_req_arb.ValidKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_kdi.u_req_arb.gen_data_port_assertion.DataFlow_A 004627729144767500
tb.dut.u_otp_ctrl_kdi.u_state_regs.AssertConnected_A 001155115500
tb.dut.u_otp_ctrl_kdi.u_state_regs_A 0046277291446183024000
tb.dut.u_otp_ctrl_lci.ErrorKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_lci.LcAckKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_lci.LcErrKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_lci.LcValueMustBeWiderThanNativeOtpWidth_A 001155115500
tb.dut.u_otp_ctrl_lci.LciIdleKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_lci.OtpAddrKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_lci.OtpCmdKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_lci.OtpReqKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_lci.OtpSizeKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_lci.OtpWdataKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_lci.u_state_regs.AssertConnected_A 001155115500
tb.dut.u_otp_ctrl_lci.u_state_regs_A 0046277291446183024000
tb.dut.u_otp_ctrl_lfsr_timer.ChkPendingKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_lfsr_timer.ChkTimeoutKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_lfsr_timer.CnstyChkReqKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_lfsr_timer.EdnIsWideEnough_A 001155115500
tb.dut.u_otp_ctrl_lfsr_timer.EdnReqKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_lfsr_timer.IntegChkReqKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.AssertConnected_A 001155115500
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs.AssertConnected_A 001155115500
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs_A 0046277291446183024000
tb.dut.u_otp_ctrl_scrmbl.CheckNumDecKeys_A 0046277291427082700
tb.dut.u_otp_ctrl_scrmbl.CheckNumDigest1_A 0046277291416430600
tb.dut.u_otp_ctrl_scrmbl.CheckNumEncKeys_A 0046277291429155000
tb.dut.u_otp_ctrl_scrmbl.DecKeyLutKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_scrmbl.DigestConstLutKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_scrmbl.DigestIvLutKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_scrmbl.EncKeyLutKnown_A 0046277291446183024000
tb.dut.u_otp_ctrl_scrmbl.NumMaxPresentRounds_A 001155115500
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds0_A 001155115500
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds1_A 001155115500
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumRounds_A 001155115500
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedWidths_A 001155115500
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds0_A 001155115500
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds1_A 001155115500
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumRounds_A 001155115500
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedWidths_A 001155115500
tb.dut.u_otp_ctrl_scrmbl.u_state_regs.AssertConnected_A 001155115500
tb.dut.u_otp_ctrl_scrmbl.u_state_regs_A 0046277291446183024000
tb.dut.u_otp_rsp_fifo.DataKnown_A 004627729141934921200
tb.dut.u_otp_rsp_fifo.DepthKnown_A 0046277291446183024000
tb.dut.u_otp_rsp_fifo.RvalidKnown_A 0046277291446183024000
tb.dut.u_otp_rsp_fifo.WreadyKnown_A 0046277291446183024000
tb.dut.u_otp_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 004627729141934921200
tb.dut.u_part_sel_idx.CheckHotOne_A 0046277291446183024000
tb.dut.u_part_sel_idx.CheckNGreaterZero_A 001155115500
tb.dut.u_part_sel_idx.GrantKnown_A 0046277291446183024000
tb.dut.u_part_sel_idx.IdxKnown_A 0046277291446183024000
tb.dut.u_part_sel_idx.Priority_A 0046277291446183024000
tb.dut.u_part_sel_idx.ReqImpliesValid_A 0046277291446183024000
tb.dut.u_part_sel_idx.ValidKnown_A 0046277291446183024000
tb.dut.u_prim_edn_req.DataOutputDiffFromPrev_A 0046277291424008353400
tb.dut.u_prim_edn_req.DataOutputValid_A 0046277291430352200
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 0046277291460755100
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 0046277291460746500
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq 00160552820160779500
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq 0046277291430325300
tb.dut.u_prim_lc_sync_check_byp_en.NumCopiesMustBeGreaterZero_A 001155115500
tb.dut.u_prim_lc_sync_check_byp_en.OutputsKnown_A 0046277291446183024000
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A 0046277291446178630003465
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A 001155115500
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.OutputsKnown_A 0046277291446183024000
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A 0046277291446178630003465
tb.dut.u_prim_lc_sync_dft_en.NumCopiesMustBeGreaterZero_A 001155115500
tb.dut.u_prim_lc_sync_dft_en.OutputsKnown_A 0046277291446183024000
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A 0046277291446178630003465
tb.dut.u_prim_lc_sync_escalate_en.NumCopiesMustBeGreaterZero_A 001155115500
tb.dut.u_prim_lc_sync_escalate_en.OutputsKnown_A 0046277291446183024000
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A 0046277291446178630003465
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A 001155115500
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.OutputsKnown_A 0046277291446183024000
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A 0046277291446178630003465
tb.dut.u_prim_lc_sync_seed_hw_rd_en.NumCopiesMustBeGreaterZero_A 001155115500
tb.dut.u_prim_lc_sync_seed_hw_rd_en.OutputsKnown_A 0046277291446183024000
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A 0046277291446178630003465
tb.dut.u_reg_core.en2addrHit 00465736056987500800
tb.dut.u_reg_core.reAfterRv 00465736056987500800
tb.dut.u_reg_core.rePulse 00465736056795451500
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck 001329132900
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A 001329132900
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert 001329132900
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A 001329132900
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001329132900
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001329132900
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A 001329132900
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck 001329132900
tb.dut.u_reg_core.u_socket.NotOverflowed_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A 004657360566025306500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 001329132900
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A 004657360565698545300
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 001329132900
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 004657360562503323000
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001329132900
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 004657360561996576900
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001329132900
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 004657360562610175900
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001329132900
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 004657360563701968400
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 0046573605646474378500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001329132900
tb.dut.u_reg_core.u_socket.maxN 001329132900
tb.dut.u_reg_core.wePulse 00465736056192049300
tb.dut.u_scrmbl_mtx.CheckHotOne_A 0046277291446183024000
tb.dut.u_scrmbl_mtx.CheckNGreaterZero_A 001155115500
tb.dut.u_scrmbl_mtx.GrantKnown_A 0046277291446183024000
tb.dut.u_scrmbl_mtx.IdxKnown_A 0046277291446183024000
tb.dut.u_scrmbl_mtx.NoReadyValidNoGrant_A 0046277291441471349000
tb.dut.u_scrmbl_mtx.ReqImpliesValid_A 004627729144711675000
tb.dut.u_scrmbl_mtx.ValidKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.AddrOutKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.DataIntgOptions_A 001155115500
tb.dut.u_tlul_adapter_sram.ReqOutKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.SramDwHasByteGranularity_A 001155115500
tb.dut.u_tlul_adapter_sram.SramDwIsMultipleOfTlulWidth_A 001155115500
tb.dut.u_tlul_adapter_sram.TlOutKnownIfFifoKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.TlOutValidKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.WdataOutKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.WeOutKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.WmaskOutKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.adapterNoReadOrWrite 001155115500
tb.dut.u_tlul_adapter_sram.rvalidHighReqFifoEmpty 0046277291411118400
tb.dut.u_tlul_adapter_sram.rvalidHighWhenRspFifoFull 0046277291411118400
tb.dut.u_tlul_adapter_sram.u_err.dataWidthOnly32_A 001155115500
tb.dut.u_tlul_adapter_sram.u_reqfifo.DataKnown_A 004627729142055791600
tb.dut.u_tlul_adapter_sram.u_reqfifo.DepthKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.u_reqfifo.RvalidKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.u_reqfifo.WreadyKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 004627729142055791600
tb.dut.u_tlul_adapter_sram.u_rsp_gen.DataWidthCheck_A 001155115500
tb.dut.u_tlul_adapter_sram.u_rsp_gen.PayLoadWidthCheck 001155115500
tb.dut.u_tlul_adapter_sram.u_rspfifo.DataKnown_A 0046277291426621400
tb.dut.u_tlul_adapter_sram.u_rspfifo.DepthKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.u_rspfifo.RvalidKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.u_rspfifo.WreadyKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0046277291426621400
tb.dut.u_tlul_adapter_sram.u_sram_byte.SramReadbackAndIntg 001155115500
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DataKnown_A 0046277291472824900
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DepthKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.RvalidKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.WreadyKnown_A 0046277291446183024000
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0046277291472824900
tb.dut.u_tlul_lc_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001155115500
tb.dut.u_tlul_lc_gate.u_err_en_sync.OutputsKnown_A 0046277291446183024000
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 0046277291446183024000
tb.dut.u_tlul_lc_gate.u_state_regs.AssertConnected_A 001155115500
tb.dut.u_tlul_lc_gate.u_state_regs_A 0046277291446183024000
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001155115500
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001155115500

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_edn_arb.RoundRobin_A 00462772914001155
tb.dut.u_otp_arb.RoundRobin_A 00462772914001155
tb.dut.u_otp_ctrl_kdi.u_req_arb.RoundRobin_A 00462772914001155
tb.dut.u_prim_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A 00462772914001155
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A 0046277291446178630003465
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A 0046277291446178630003465
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A 0046277291446178630003465
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A 0046277291446178630003465
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A 0046277291446178630003465
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A 0046277291446178630003465
tb.dut.u_scrmbl_mtx.RoundRobin_A 00462772914001155

Assertions Without Attempts:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpErrorState_A 000000


Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 004657369879279270
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 004657369872952950
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 004657369872962960
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 004657369871891890
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 0046573698734340
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 004657369871551550
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 004657369871841840
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00465736987439243920
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C 00465736987870687060
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C 00465736987359795835979581227
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 004657369873433430
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 004657369871131131
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 004657369871171171
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0046573698778781
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00465736987661
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0046573698756561
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0046573698718181
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00465736987126812680
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C 00465736987305730570
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C 00465736987604846048458

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 004657369879279270
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 004657369872952950
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 004657369872962960
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 004657369871891890
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 0046573698734340
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 004657369871551550
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 004657369871841840
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00465736987439243920
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C 00465736987870687060
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C 00465736987359795835979581227
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 004657369873433430
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 004657369871131131
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 004657369871171171
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0046573698778781
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00465736987661
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0046573698756561
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0046573698718181
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00465736987126812680
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C 00465736987305730570
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C 00465736987604846048458