Unified Coverage Report :: Module :: otp_ctrl_lfsr_timer

Module : otp_ctrl_lfsr_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
7.74	0.00	0.00	30.95		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count_cnsty	0.00			0.00
u_prim_count_integ	0.00			0.00
u_prim_double_lfsr	0.00	0.00	0.00	0.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Module : otp_ctrl_lfsr_timer

	Line No.	Total	Covered	Percent
TOTAL		91	0	0.00
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	77	1	0	0.00
CONT_ASSIGN	78	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	114	1	0	0.00
CONT_ASSIGN	132	1	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	135	1	0	0.00
CONT_ASSIGN	136	1	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	142	1	0	0.00
CONT_ASSIGN	143	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	189	1	0	0.00
CONT_ASSIGN	190	1	0	0.00
CONT_ASSIGN	191	1	0	0.00
CONT_ASSIGN	193	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	202	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
ALWAYS	246	52	0	0.00
ALWAYS	367	3	0	0.00
ALWAYS	370	13	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
72	0	1
77	0	1
78	0	1
87	0	1
114	0	1
132	0	1
133	0	1
134	0	1
135	0	1
136	0	1
138	0	1
139	0	1
141	0	1
142	0	1
143	0	1
144	0	1
189	0	1
190	0	1
191	0	1
193	0	1
201	0	1
202	0	1
243	0	1
246	0	1
249	0	1
250	0	1
251	0	1
252	0	1
253	0	1
254	0	1
257	0	1
258	0	1
261	0	1
262	0	1
263	0	1
266	0	1
267	0	1
269	0	1
274	0	1
275	0	1
276	0	1
			==> MISSING_ELSE
283	0	1
284	0	1
285	0	1
286	0	1
287	0	1
288	0	1
289	0	1
290	0	1
291	0	1
292	0	1
			==> MISSING_ELSE
300	0	1
301	0	1
302	0	1
303	0	1
304	0	1
305	0	1
307	0	1
308	0	1
			==> MISSING_ELSE
316	0	1
322	0	1
323	0	1
324	0	1
325	0	1
326	0	1
327	0	1
329	0	1
330	0	1
			==> MISSING_ELSE
337	0	1
338	0	1
339	0	1
340	0	1
			==> MISSING_ELSE
356	0	1
358	0	1
359	0	1
			==> MISSING_ELSE
367	0	3
370	0	1
371	0	1
372	0	1
373	0	1
374	0	1
375	0	1
376	0	1
378	0	1
379	0	1
380	0	1
381	0	1
382	0	1
383	0	1

---

Cond Coverage for Module : otp_ctrl_lfsr_timer

	Total	Covered	Percent
Conditions	78	0	0.00
Logical	78	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (reseed_en ? '0 : (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)))
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       72
 SUB-EXPRESSION (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q))
                 ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       72
 SUB-EXPRESSION (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)
                 ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       78
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       87
 EXPRESSION (reseed_en ? edn_data_i[(otp_ctrl_pkg::LfsrWidth - 1):0] : '0)
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       101
 EXPRESSION (reseed_en || lfsr_en)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       132
 EXPRESSION (timeout_i == '0)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       133
 EXPRESSION (integ_period_msk_i == '0)
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       134
 EXPRESSION (cnsty_period_msk_i == '0)
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       135
 EXPRESSION (integ_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       136
 EXPRESSION (cnsty_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       138
 EXPRESSION (integ_set_period || integ_set_timeout)
             --------1-------    --------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       139
 EXPRESSION (cnsty_set_period || cnsty_set_timeout)
             --------1-------    --------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       143
 EXPRESSION (integ_set_period ? ((lfsr_state & integ_mask)) : (40'(timeout_i)))
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       144
 EXPRESSION (cnsty_set_period ? ((lfsr_state & cnsty_mask)) : (40'(timeout_i)))
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       167
 EXPRESSION (((!cnsty_cnt_zero)) && ((!cnsty_cnt_pause)))
             ---------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       191
 EXPRESSION (set_all_integ_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((integ_chk_req_q & (~integ_chk_ack_i))))
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       193
 EXPRESSION (set_all_cnsty_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((cnsty_chk_req_q & (~cnsty_chk_ack_i))))
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       201
 EXPRESSION ((integ_chk_trig_q & ((~clr_integ_chk_trig))) | integ_chk_trig_i)
             ----------------------1---------------------   --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       201
 SUB-EXPRESSION (integ_chk_trig_q & ((~clr_integ_chk_trig)))
                 --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       202
 EXPRESSION ((cnsty_chk_trig_q & ((~clr_cnsty_chk_trig))) | cnsty_chk_trig_i)
             ----------------------1---------------------   --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       202
 SUB-EXPRESSION (cnsty_chk_trig_q & ((~clr_cnsty_chk_trig)))
                 --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       262
 EXPRESSION (cnsty_chk_trig_q || integ_chk_trig_q)
             --------1-------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       283
 EXPRESSION ((((!integ_msk_zero)) && integ_cnt_zero) || integ_chk_trig_q)
             -------------------1-------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       283
 SUB-EXPRESSION (((!integ_msk_zero)) && integ_cnt_zero)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       288
 EXPRESSION ((((!cnsty_msk_zero)) && cnsty_cnt_zero) || cnsty_chk_trig_q)
             -------------------1-------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       288
 SUB-EXPRESSION (((!cnsty_msk_zero)) && cnsty_cnt_zero)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       301
 EXPRESSION (((!timeout_zero)) && integ_cnt_zero)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       304
 EXPRESSION (integ_chk_req_q == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       323
 EXPRESSION (((!timeout_zero)) && cnsty_cnt_zero)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       326
 EXPRESSION (cnsty_chk_req_q == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : otp_ctrl_lfsr_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	9	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CnstyWaitSt	289	Not Covered
ErrorSt	302	Not Covered
IdleSt	275	Not Covered
IntegWaitSt	284	Not Covered
ResetSt	273	Not Covered

transitions	Line No.	Covered	Tests
CnstyWaitSt->ErrorSt	324	Not Covered
CnstyWaitSt->IdleSt	327	Not Covered
IdleSt->CnstyWaitSt	289	Not Covered
IdleSt->ErrorSt	358	Not Covered
IdleSt->IntegWaitSt	284	Not Covered
IntegWaitSt->ErrorSt	302	Not Covered
IntegWaitSt->IdleSt	305	Not Covered
ResetSt->ErrorSt	358	Not Covered
ResetSt->IdleSt	275	Not Covered

---

Branch Coverage for Module : otp_ctrl_lfsr_timer

	Line No.	Total	Covered	Percent
Branches		34	0	0.00
TERNARY	72	4	0	0.00
TERNARY	87	2	0	0.00
TERNARY	143	2	0	0.00
TERNARY	144	2	0	0.00
TERNARY	191	2	0	0.00
TERNARY	193	2	0	0.00
CASE	269	14	0	0.00
IF	356	2	0	0.00
IF	367	2	0	0.00
IF	370	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	72	(reseed_en) ? 
-2-:	72	(edn_req_o) ? 
-3-:	72	(lfsr_en) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	87	(reseed_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	143	(integ_set_period) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	144	(cnsty_set_period) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	191	(set_all_integ_reqs) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	193	(set_all_cnsty_reqs) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	269	case (state_q)
-2-:	274	if (timer_en_i)
-3-:	283	if ((((!integ_msk_zero) && integ_cnt_zero) || integ_chk_trig_q))
-4-:	288	if ((((!cnsty_msk_zero) && cnsty_cnt_zero) || cnsty_chk_trig_q))
-5-:	301	if (((!timeout_zero) && integ_cnt_zero))
-6-:	304	if ((integ_chk_req_q == '0))
-7-:	323	if (((!timeout_zero) && cnsty_cnt_zero))
-8-:	326	if ((cnsty_chk_req_q == '0))
-9-:	339	if ((!chk_timeout_q))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	Not Covered
IdleSt	-	1	-	-	-	-	-	-	Not Covered
IdleSt	-	0	1	-	-	-	-	-	Not Covered
IdleSt	-	0	0	-	-	-	-	-	Not Covered
IntegWaitSt	-	-	-	1	-	-	-	-	Not Covered
IntegWaitSt	-	-	-	0	1	-	-	-	Not Covered
IntegWaitSt	-	-	-	0	0	-	-	-	Not Covered
CnstyWaitSt	-	-	-	-	-	1	-	-	Not Covered
CnstyWaitSt	-	-	-	-	-	0	1	-	Not Covered
CnstyWaitSt	-	-	-	-	-	0	0	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	356	if ((((lfsr_err || integ_cnt_err) || cnsty_cnt_err) || lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	367	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	370	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer

	Line No.	Total	Covered	Percent
TOTAL		91	0	0.00
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	77	1	0	0.00
CONT_ASSIGN	78	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	114	1	0	0.00
CONT_ASSIGN	132	1	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	135	1	0	0.00
CONT_ASSIGN	136	1	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	142	1	0	0.00
CONT_ASSIGN	143	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	189	1	0	0.00
CONT_ASSIGN	190	1	0	0.00
CONT_ASSIGN	191	1	0	0.00
CONT_ASSIGN	193	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	202	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
ALWAYS	246	52	0	0.00
ALWAYS	367	3	0	0.00
ALWAYS	370	13	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
72	0	1
77	0	1
78	0	1
87	0	1
114	0	1
132	0	1
133	0	1
134	0	1
135	0	1
136	0	1
138	0	1
139	0	1
141	0	1
142	0	1
143	0	1
144	0	1
189	0	1
190	0	1
191	0	1
193	0	1
201	0	1
202	0	1
243	0	1
246	0	1
249	0	1
250	0	1
251	0	1
252	0	1
253	0	1
254	0	1
257	0	1
258	0	1
261	0	1
262	0	1
263	0	1
266	0	1
267	0	1
269	0	1
274	0	1
275	0	1
276	0	1
			==> MISSING_ELSE
283	0	1
284	0	1
285	0	1
286	0	1
287	0	1
288	0	1
289	0	1
290	0	1
291	0	1
292	0	1
			==> MISSING_ELSE
300	0	1
301	0	1
302	0	1
303	0	1
304	0	1
305	0	1
307	0	1
308	0	1
			==> MISSING_ELSE
316	0	1
322	0	1
323	0	1
324	0	1
325	0	1
326	0	1
327	0	1
329	0	1
330	0	1
			==> MISSING_ELSE
337	0	1
338	0	1
339	0	1
340	0	1
			==> MISSING_ELSE
356	0	1
358	0	1
359	0	1
			==> MISSING_ELSE
367	0	3
370	0	1
371	0	1
372	0	1
373	0	1
374	0	1
375	0	1
376	0	1
378	0	1
379	0	1
380	0	1
381	0	1
382	0	1
383	0	1

---

Cond Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer

	Total	Covered	Percent
Conditions	77	0	0.00
Logical	77	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (reseed_en ? '0 : (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)))
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       72
 SUB-EXPRESSION (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q))
                 ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       72
 SUB-EXPRESSION (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)
                 ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       78
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Not Covered
1	1	Not Covered

 LINE       87
 EXPRESSION (reseed_en ? edn_data_i[(otp_ctrl_pkg::LfsrWidth - 1):0] : '0)
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       101
 EXPRESSION (reseed_en || lfsr_en)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       132
 EXPRESSION (timeout_i == '0)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       133
 EXPRESSION (integ_period_msk_i == '0)
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       134
 EXPRESSION (cnsty_period_msk_i == '0)
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       135
 EXPRESSION (integ_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       136
 EXPRESSION (cnsty_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       138
 EXPRESSION (integ_set_period || integ_set_timeout)
             --------1-------    --------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       139
 EXPRESSION (cnsty_set_period || cnsty_set_timeout)
             --------1-------    --------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       143
 EXPRESSION (integ_set_period ? ((lfsr_state & integ_mask)) : (40'(timeout_i)))
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       144
 EXPRESSION (cnsty_set_period ? ((lfsr_state & cnsty_mask)) : (40'(timeout_i)))
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       167
 EXPRESSION (((!cnsty_cnt_zero)) && ((!cnsty_cnt_pause)))
             ---------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       191
 EXPRESSION (set_all_integ_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((integ_chk_req_q & (~integ_chk_ack_i))))
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       193
 EXPRESSION (set_all_cnsty_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((cnsty_chk_req_q & (~cnsty_chk_ack_i))))
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       201
 EXPRESSION ((integ_chk_trig_q & ((~clr_integ_chk_trig))) | integ_chk_trig_i)
             ----------------------1---------------------   --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       201
 SUB-EXPRESSION (integ_chk_trig_q & ((~clr_integ_chk_trig)))
                 --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       202
 EXPRESSION ((cnsty_chk_trig_q & ((~clr_cnsty_chk_trig))) | cnsty_chk_trig_i)
             ----------------------1---------------------   --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       202
 SUB-EXPRESSION (cnsty_chk_trig_q & ((~clr_cnsty_chk_trig)))
                 --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       262
 EXPRESSION (cnsty_chk_trig_q || integ_chk_trig_q)
             --------1-------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       283
 EXPRESSION ((((!integ_msk_zero)) && integ_cnt_zero) || integ_chk_trig_q)
             -------------------1-------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       283
 SUB-EXPRESSION (((!integ_msk_zero)) && integ_cnt_zero)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       288
 EXPRESSION ((((!cnsty_msk_zero)) && cnsty_cnt_zero) || cnsty_chk_trig_q)
             -------------------1-------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       288
 SUB-EXPRESSION (((!cnsty_msk_zero)) && cnsty_cnt_zero)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       301
 EXPRESSION (((!timeout_zero)) && integ_cnt_zero)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       304
 EXPRESSION (integ_chk_req_q == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       323
 EXPRESSION (((!timeout_zero)) && cnsty_cnt_zero)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       326
 EXPRESSION (cnsty_chk_req_q == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	9	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CnstyWaitSt	289	Not Covered
ErrorSt	302	Not Covered
IdleSt	275	Not Covered
IntegWaitSt	284	Not Covered
ResetSt	273	Not Covered

transitions	Line No.	Covered	Tests
CnstyWaitSt->ErrorSt	324	Not Covered
CnstyWaitSt->IdleSt	327	Not Covered
IdleSt->CnstyWaitSt	289	Not Covered
IdleSt->ErrorSt	358	Not Covered
IdleSt->IntegWaitSt	284	Not Covered
IntegWaitSt->ErrorSt	302	Not Covered
IntegWaitSt->IdleSt	305	Not Covered
ResetSt->ErrorSt	358	Not Covered
ResetSt->IdleSt	275	Not Covered

---

Branch Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer

	Line No.	Total	Covered	Percent
Branches		34	0	0.00
TERNARY	72	4	0	0.00
TERNARY	87	2	0	0.00
TERNARY	143	2	0	0.00
TERNARY	144	2	0	0.00
TERNARY	191	2	0	0.00
TERNARY	193	2	0	0.00
CASE	269	14	0	0.00
IF	356	2	0	0.00
IF	367	2	0	0.00
IF	370	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	72	(reseed_en) ? 
-2-:	72	(edn_req_o) ? 
-3-:	72	(lfsr_en) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	87	(reseed_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	143	(integ_set_period) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	144	(cnsty_set_period) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	191	(set_all_integ_reqs) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	193	(set_all_cnsty_reqs) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	269	case (state_q)
-2-:	274	if (timer_en_i)
-3-:	283	if ((((!integ_msk_zero) && integ_cnt_zero) || integ_chk_trig_q))
-4-:	288	if ((((!cnsty_msk_zero) && cnsty_cnt_zero) || cnsty_chk_trig_q))
-5-:	301	if (((!timeout_zero) && integ_cnt_zero))
-6-:	304	if ((integ_chk_req_q == '0))
-7-:	323	if (((!timeout_zero) && cnsty_cnt_zero))
-8-:	326	if ((cnsty_chk_req_q == '0))
-9-:	339	if ((!chk_timeout_q))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	Not Covered
IdleSt	-	1	-	-	-	-	-	-	Not Covered
IdleSt	-	0	1	-	-	-	-	-	Not Covered
IdleSt	-	0	0	-	-	-	-	-	Not Covered
IntegWaitSt	-	-	-	1	-	-	-	-	Not Covered
IntegWaitSt	-	-	-	0	1	-	-	-	Not Covered
IntegWaitSt	-	-	-	0	0	-	-	-	Not Covered
CnstyWaitSt	-	-	-	-	-	1	-	-	Not Covered
CnstyWaitSt	-	-	-	-	-	0	1	-	Not Covered
CnstyWaitSt	-	-	-	-	-	0	0	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	356	if ((((lfsr_err || integ_cnt_err) || cnsty_cnt_err) || lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	367	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	370	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered