Unified Coverage Report :: Module :: prim_double_lfsr

Module : prim_double_lfsr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_double_lfsr_0/rtl/prim_double_lfsr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr	0.00	0.00	0.00

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_otp_ctrl_lfsr_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_double_lfsr[0].u_prim_buf_input	0.00	0.00
gen_double_lfsr[0].u_prim_buf_output	0.00	0.00
gen_double_lfsr[0].u_prim_lfsr	0.00			0.00
gen_double_lfsr[1].u_prim_buf_input	0.00	0.00
gen_double_lfsr[1].u_prim_buf_output	0.00	0.00
gen_double_lfsr[1].u_prim_lfsr	0.00			0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_double_lfsr

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	102	1	0	0.00
CONT_ASSIGN	103	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_double_lfsr_0/rtl/prim_double_lfsr.sv' or '../src/lowrisc_prim_double_lfsr_0/rtl/prim_double_lfsr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
102	0	1
103	0	1

---

Cond Coverage for Module : prim_double_lfsr

	Total	Covered	Percent
Conditions	2	0	0.00
Logical	2	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (lfsr_state[0] != lfsr_state[1])
            ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered