Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
7.74	0.00	0.00	30.95		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	0.00	0.00				0.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	0.00	0.00		0.00		0.00
u_prim_mubi8_sender_read_lock_pre	0.00	0.00				0.00
u_prim_mubi8_sender_write_lock_pre	0.00	0.00				0.00
u_state_regs	0.00	0.00				0.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
7.74	0.00	0.00	30.95		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	0.00	0.00				0.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	0.00	0.00		0.00		0.00
u_prim_mubi8_sender_read_lock_pre	0.00	0.00				0.00
u_prim_mubi8_sender_write_lock_pre	0.00	0.00				0.00
u_state_regs	0.00	0.00				0.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
7.74	0.00	0.00	30.95		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	0.00	0.00				0.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	0.00	0.00		0.00		0.00
u_prim_mubi8_sender_read_lock_pre	0.00	0.00				0.00
u_prim_mubi8_sender_write_lock_pre	0.00	0.00				0.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	0	0.00
CONT_ASSIGN	138	1	0	0.00
ALWAYS	153	3	0	0.00
ALWAYS	164	61	0	0.00
CONT_ASSIGN	334	1	0	0.00
CONT_ASSIGN	336	1	0	0.00
CONT_ASSIGN	339	1	0	0.00
CONT_ASSIGN	349	1	0	0.00
CONT_ASSIGN	350	1	0	0.00
CONT_ASSIGN	354	1	0	0.00
CONT_ASSIGN	358	1	0	0.00
CONT_ASSIGN	395	1	0	0.00
CONT_ASSIGN	420	1	0	0.00
CONT_ASSIGN	454	1	0	0.00
ALWAYS	461	3	0	0.00
ALWAYS	464	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	0	1
153	0	1
154	0	1
156	0	1
164	0	1
167	0	1
170	0	1
171	0	1
174	0	1
175	0	1
176	0	1
179	0	1
182	0	1
183	0	1
184	0	1
186	0	1
191	0	1
193	0	1
194	0	1
196		unreachable
			==> MISSING_ELSE
205	0	1
206	0	1
207	0	1
			==> MISSING_ELSE
215	0	1
216	0	1
217	0	1
218	0	1
220	0	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
233	0	1
234	0	1
235	0	1
236	0	1
237	0	1
			==> MISSING_ELSE
246	0	1
248	0	1
249	0	1
250	0	1
251	0	1
252	0	1
			==> MISSING_ELSE
255	0	1
256	0	1
257	0	1
258	0	1
266	0	1
267	0	1
268	0	1
269	0	1
270	0	1
272	0	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
288	0	1
289	0	1
			==> MISSING_ELSE
293	0	1
294	0	1
295	0	1
296	0	1
297	0	1
298	0	1
			==> MISSING_ELSE
314	0	1
315	0	1
316	0	1
317	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
321	0	1
322	0	1
323	0	1
324	0	1
325	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
334	0	1
336	0	1
339	0	1
349	0	1
350	0	1
354	0	1
358	0	1
395	0	1
420	0	1
454	0	1
461	0	3
464	0	1
465	0	1
466	0	1
467	0	1
469	0	1
470	0	1
471	0	1
472	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	0	0.00
Logical	29	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Not Covered
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Not Covered
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Not Covered
IdleSt	196	Not Covered
InitSt	194	Not Covered
InitWaitSt	207	Not Covered
ReadSt	236	Not Covered
ReadWaitSt	252	Not Covered
ResetSt	190	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Not Covered
IdleSt->ReadSt	236	Not Covered
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Not Covered
InitWaitSt->ErrorSt	224	Not Covered
InitWaitSt->IdleSt	218	Not Covered
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Not Covered
ReadSt->ReadWaitSt	252	Not Covered
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Not Covered
ResetSt->ErrorSt	315	Not Covered
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Not Covered

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	0	0.00	(Not included in score)
Transitions	7	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Not Covered
CheckFailError	317	Not Covered
FsmStateError	289	Not Covered
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Not Covered
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Not Covered
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Not Covered
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Not Covered
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Not Covered
NoError->CheckFailError	317	Not Covered
NoError->FsmStateError	289	Not Covered
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	0	0.00
TERNARY	336	2	0	0.00
TERNARY	349	2	0	0.00
TERNARY	358	2	0	0.00
TERNARY	395	2	0	0.00
TERNARY	420	2	0	0.00
CASE	186	18	0	0.00
IF	314	3	0	0.00
IF	321	3	0	0.00
IF	461	2	0	0.00
IF	464	3	0	0.00
IF	153	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	149	1	0	0.00
ALWAYS	164	68	0	0.00
CONT_ASSIGN	334	1	0	0.00
CONT_ASSIGN	336	1	0	0.00
CONT_ASSIGN	342	1	0	0.00
CONT_ASSIGN	349	1	0	0.00
CONT_ASSIGN	350	1	0	0.00
CONT_ASSIGN	354	1	0	0.00
CONT_ASSIGN	358	1	0	0.00
CONT_ASSIGN	395	1	0	0.00
CONT_ASSIGN	420	1	0	0.00
CONT_ASSIGN	454	1	0	0.00
ALWAYS	461	3	0	0.00
ALWAYS	464	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	0	1
149	0	1
164	0	1
167	0	1
170	0	1
171	0	1
174	0	1
175	0	1
176	0	1
179	0	1
182	0	1
183	0	1
184	0	1
186	0	1
191	0	1
193	0	1
194	0	1
196		unreachable
			==> MISSING_ELSE
205	0	1
206	0	1
207	0	1
			==> MISSING_ELSE
215	0	1
216	0	1
217	0	1
218	0	1
220	0	1
221	0	1
			==> MISSING_ELSE
224	0	1
225	0	1
			==> MISSING_ELSE
233	0	1
234	0	1
235	0	1
236	0	1
237	0	1
			==> MISSING_ELSE
246	0	1
248	0	1
249	0	1
250	0	1
251	0	1
252	0	1
			==> MISSING_ELSE
255	0	1
256	0	1
257	0	1
258	0	1
266	0	1
267	0	1
268	0	1
269	0	1
270	0	1
272	0	1
273	0	1
			==> MISSING_ELSE
276	0	1
277	0	1
279	0	1
			==> MISSING_ELSE
288	0	1
289	0	1
			==> MISSING_ELSE
293	0	1
294	0	1
295	0	1
296	0	1
297	0	1
298	0	1
			==> MISSING_ELSE
314	0	1
315	0	1
316	0	1
317	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
321	0	1
322	0	1
323	0	1
324	0	1
325	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
334	0	1
336	0	1
342	0	1
349	0	1
350	0	1
354	0	1
358	0	1
395	0	1
420	0	1
454	0	1
461	0	3
464	0	1
465	0	1
466	0	1
467	0	1
469	0	1
470	0	1
471	0	1
472	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	0	0.00
Logical	33	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Not Covered

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Not Covered
IdleSt	196	Not Covered
InitSt	194	Not Covered
InitWaitSt	207	Not Covered
ReadSt	236	Not Covered
ReadWaitSt	252	Not Covered
ResetSt	190	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Not Covered
IdleSt->ReadSt	236	Not Covered
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Not Covered
InitWaitSt->ErrorSt	224	Not Covered
InitWaitSt->IdleSt	218	Not Covered
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Not Covered
ReadSt->ReadWaitSt	252	Not Covered
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Not Covered
ResetSt->ErrorSt	315	Not Covered
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Not Covered

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	11	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Not Covered
CheckFailError	317	Not Covered
FsmStateError	289	Not Covered
MacroEccCorrError	221	Not Covered
NoError	235	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Not Covered
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Not Covered
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Not Covered
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Not Covered
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Not Covered
MacroEccCorrError->NoError	235	Not Covered
NoError->AccessError	256	Not Covered
NoError->CheckFailError	317	Not Covered
NoError->FsmStateError	289	Not Covered
NoError->MacroEccCorrError	221	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	0	0.00
TERNARY	336	2	0	0.00
TERNARY	349	2	0	0.00
TERNARY	358	2	0	0.00
TERNARY	395	2	0	0.00
TERNARY	420	2	0	0.00
CASE	186	23	0	0.00
IF	314	3	0	0.00
IF	321	3	0	0.00
IF	461	2	0	0.00
IF	464	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	149	1	0	0.00
ALWAYS	164	68	0	0.00
CONT_ASSIGN	334	1	0	0.00
CONT_ASSIGN	336	1	0	0.00
CONT_ASSIGN	342	1	0	0.00
CONT_ASSIGN	349	1	0	0.00
CONT_ASSIGN	350	1	0	0.00
CONT_ASSIGN	354	1	0	0.00
CONT_ASSIGN	358	1	0	0.00
CONT_ASSIGN	395	1	0	0.00
CONT_ASSIGN	420	1	0	0.00
CONT_ASSIGN	454	1	0	0.00
ALWAYS	461	3	0	0.00
ALWAYS	464	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	0	1
149	0	1
164	0	1
167	0	1
170	0	1
171	0	1
174	0	1
175	0	1
176	0	1
179	0	1
182	0	1
183	0	1
184	0	1
186	0	1
191	0	1
193	0	1
194	0	1
196		unreachable
			==> MISSING_ELSE
205	0	1
206	0	1
207	0	1
			==> MISSING_ELSE
215	0	1
216	0	1
217	0	1
218	0	1
220	0	1
221	0	1
			==> MISSING_ELSE
224	0	1
225	0	1
			==> MISSING_ELSE
233	0	1
234	0	1
235	0	1
236	0	1
237	0	1
			==> MISSING_ELSE
246	0	1
248	0	1
249	0	1
250	0	1
251	0	1
252	0	1
			==> MISSING_ELSE
255	0	1
256	0	1
257	0	1
258	0	1
266	0	1
267	0	1
268	0	1
269	0	1
270	0	1
272	0	1
273	0	1
			==> MISSING_ELSE
276	0	1
277	0	1
279	0	1
			==> MISSING_ELSE
288	0	1
289	0	1
			==> MISSING_ELSE
293	0	1
294	0	1
295	0	1
296	0	1
297	0	1
298	0	1
			==> MISSING_ELSE
314	0	1
315	0	1
316	0	1
317	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
321	0	1
322	0	1
323	0	1
324	0	1
325	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
334	0	1
336	0	1
342	0	1
349	0	1
350	0	1
354	0	1
358	0	1
395	0	1
420	0	1
454	0	1
461	0	3
464	0	1
465	0	1
466	0	1
467	0	1
469	0	1
470	0	1
471	0	1
472	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	0	0.00
Logical	34	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Not Covered
IdleSt	196	Not Covered
InitSt	194	Not Covered
InitWaitSt	207	Not Covered
ReadSt	236	Not Covered
ReadWaitSt	252	Not Covered
ResetSt	190	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Not Covered
IdleSt->ReadSt	236	Not Covered
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Not Covered
InitWaitSt->ErrorSt	224	Not Covered
InitWaitSt->IdleSt	218	Not Covered
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Not Covered
ReadSt->ReadWaitSt	252	Not Covered
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Not Covered
ResetSt->ErrorSt	315	Not Covered
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Not Covered

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	11	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Not Covered
CheckFailError	317	Not Covered
FsmStateError	289	Not Covered
MacroEccCorrError	221	Not Covered
NoError	235	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Not Covered
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Not Covered
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Not Covered
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Not Covered
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Not Covered
MacroEccCorrError->NoError	235	Not Covered
NoError->AccessError	256	Not Covered
NoError->CheckFailError	317	Not Covered
NoError->FsmStateError	289	Not Covered
NoError->MacroEccCorrError	221	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	0	0.00
TERNARY	336	2	0	0.00
TERNARY	349	2	0	0.00
TERNARY	358	2	0	0.00
TERNARY	395	2	0	0.00
TERNARY	420	2	0	0.00
CASE	186	23	0	0.00
IF	314	3	0	0.00
IF	321	3	0	0.00
IF	461	2	0	0.00
IF	464	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered