Module Definition
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Module : prim_present
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc 0.00 0.00 0.00 0.00
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec 0.00 0.00 0.00 0.00


Module Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 0.00 u_otp_ctrl_scrmbl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 0.00 u_otp_ctrl_scrmbl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_present ( parameter DataWidth=64,KeyWidth=128,NumRounds=31,NumPhysRounds=1,Decrypt=0 )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc

Line No.TotalCoveredPercent
TOTAL1100.00
CONT_ASSIGN62100.00
CONT_ASSIGN63100.00
CONT_ASSIGN64100.00
CONT_ASSIGN69100.00
CONT_ASSIGN106100.00
CONT_ASSIGN109100.00
CONT_ASSIGN111100.00
CONT_ASSIGN123100.00
CONT_ASSIGN139100.00
CONT_ASSIGN144100.00
CONT_ASSIGN145100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 0 1
63 0 1
64 0 1
69 0 1
106 0 1
109 0 1
111 0 1
123 0 1
139 0 1
144 0 1
145 0 1

Line Coverage for Module : prim_present ( parameter DataWidth=64,KeyWidth=128,NumRounds=31,NumPhysRounds=1,Decrypt=1 )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec

Line No.TotalCoveredPercent
TOTAL1100.00
CONT_ASSIGN62100.00
CONT_ASSIGN63100.00
CONT_ASSIGN64100.00
CONT_ASSIGN69100.00
CONT_ASSIGN74100.00
CONT_ASSIGN77100.00
CONT_ASSIGN79100.00
CONT_ASSIGN91100.00
CONT_ASSIGN139100.00
CONT_ASSIGN144100.00
CONT_ASSIGN145100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 0 1
63 0 1
64 0 1
69 0 1
74 0 1
77 0 1
79 0 1
91 0 1
139 0 1
144 0 1
145 0 1

Cond Coverage for Module : prim_present
TotalCoveredPercent
Conditions200.00
Logical200.00
Non-Logical00
Event00

 LINE       139
 EXPRESSION 
 Number  Term
      1  (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])
-1-StatusTests
0Unreachable
1Not Covered 

 LINE       139
 SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
                --------------1--------------
-1-StatusTests
0Unreachable
1Not Covered
Branch Coverage for Module : prim_present
Line No.TotalCoveredPercent
Branches 1 0 0.00
TERNARY 139 1 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	139	((int'(idx_o) == LastRoundIdx)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable

Line Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc
Line No.TotalCoveredPercent
TOTAL1100.00
CONT_ASSIGN62100.00
CONT_ASSIGN63100.00
CONT_ASSIGN64100.00
CONT_ASSIGN69100.00
CONT_ASSIGN106100.00
CONT_ASSIGN109100.00
CONT_ASSIGN111100.00
CONT_ASSIGN123100.00
CONT_ASSIGN139100.00
CONT_ASSIGN144100.00
CONT_ASSIGN145100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 0 1
63 0 1
64 0 1
69 0 1
106 0 1
109 0 1
111 0 1
123 0 1
139 0 1
144 0 1
145 0 1

Cond Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc
TotalCoveredPercent
Conditions200.00
Logical200.00
Non-Logical00
Event00

 LINE       139
 EXPRESSION 
 Number  Term
      1  (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])
-1-StatusTests
0Unreachable
1Not Covered 

 LINE       139
 SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
                --------------1--------------
-1-StatusTests
0Unreachable
1Not Covered
Branch Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc
Line No.TotalCoveredPercent
Branches 1 0 0.00
TERNARY 139 1 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	139	((int'(idx_o) == LastRoundIdx)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable

Line Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec
Line No.TotalCoveredPercent
TOTAL1100.00
CONT_ASSIGN62100.00
CONT_ASSIGN63100.00
CONT_ASSIGN64100.00
CONT_ASSIGN69100.00
CONT_ASSIGN74100.00
CONT_ASSIGN77100.00
CONT_ASSIGN79100.00
CONT_ASSIGN91100.00
CONT_ASSIGN139100.00
CONT_ASSIGN144100.00
CONT_ASSIGN145100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 0 1
63 0 1
64 0 1
69 0 1
74 0 1
77 0 1
79 0 1
91 0 1
139 0 1
144 0 1
145 0 1

Cond Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec
TotalCoveredPercent
Conditions200.00
Logical200.00
Non-Logical00
Event00

 LINE       139
 EXPRESSION 
 Number  Term
      1  (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])
-1-StatusTests
0Unreachable
1Not Covered 

 LINE       139
 SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
                --------------1--------------
-1-StatusTests
0Unreachable
1Not Covered
Branch Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec
Line No.TotalCoveredPercent
Branches 1 0 0.00
TERNARY 139 1 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	139	((int'(idx_o) == LastRoundIdx)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable

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