Unified Coverage Report :: Module :: otp_ctrl_scrmbl

Module : otp_ctrl_scrmbl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_scrmbl	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_otp_ctrl_scrmbl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
7.74	0.00	0.00	30.95		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_anchor_digests[0].u_const_anchor_buf	0.00	0.00
gen_anchor_digests[0].u_iv_anchor_buf	0.00	0.00
gen_anchor_digests[1].u_const_anchor_buf	0.00	0.00
gen_anchor_digests[1].u_iv_anchor_buf	0.00	0.00
gen_anchor_digests[2].u_const_anchor_buf	0.00	0.00
gen_anchor_digests[2].u_iv_anchor_buf	0.00	0.00
gen_anchor_digests[3].u_const_anchor_buf	0.00	0.00
gen_anchor_digests[3].u_iv_anchor_buf	0.00	0.00
gen_anchor_keys[0].u_key_anchor_buf	0.00	0.00
gen_anchor_keys[1].u_key_anchor_buf	0.00	0.00
gen_anchor_keys[2].u_key_anchor_buf	0.00	0.00
u_prim_count	0.00			0.00
u_prim_present_dec	0.00	0.00	0.00			0.00
u_prim_present_enc	0.00	0.00	0.00			0.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Module : otp_ctrl_scrmbl

	Line No.	Total	Covered	Percent
TOTAL		120	0	0.00
ALWAYS	141	10	0	0.00
CONT_ASSIGN	199	1	0	0.00
CONT_ASSIGN	200	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	202	1	0	0.00
CONT_ASSIGN	209	1	0	0.00
CONT_ASSIGN	215	1	0	0.00
CONT_ASSIGN	224	1	0	0.00
CONT_ASSIGN	230	1	0	0.00
CONT_ASSIGN	231	1	0	0.00
CONT_ASSIGN	234	1	0	0.00
CONT_ASSIGN	281	1	0	0.00
ALWAYS	302	75	0	0.00
ALWAYS	476	3	0	0.00
ALWAYS	479	21	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
141	0	1
142	0	1
143	0	1
144	0	1
146	0	1
148	0	1
151	0	1
155	0	1
156	0	1
157	0	1
199	0	1
200	0	1
201	0	1
202	0	1
209	0	1
215	0	1
224	0	1
230	0	1
231	0	1
234	0	1
281	0	1
302	0	1
303	0	1
304	0	1
305	0	1
306	0	1
307	0	1
308	0	1
309	0	1
310	0	1
311	0	1
312	0	1
313	0	1
314	0	1
315	0	1
316	0	1
318	0	1
323	0	1
324	0	1
326	0	1
327	0	1
329	0	1
330	0	1
331	0	1
332	0	1
335	0	1
336	0	1
337	0	1
338	0	1
341	0	1
342	0	1
344	0	1
348	0	1
349	0	1
350	0	1
351	0	1
352	0	1
355	0	1
356	0	1
357	0	1
360	0	1
361	0	1
362	0	1
363	0	1
364	0	1
365	0	1
			==> MISSING_ELSE
374	0	1
375	0	1
376	0	1
377	0	1
378	0	1
379	0	1
380	0	1
381	0	1
			==> MISSING_ELSE
387	0	1
388	0	1
389	0	1
390	0	1
391	0	1
392	0	1
393	0	1
394	0	1
			==> MISSING_ELSE
401	0	1
402	0	1
403	0	1
404	0	1
405	0	1
406	0	1
407	0	1
408	0	1
410	0	1
414	0	1
			==> MISSING_ELSE
420	0	1
434	0	1
435	0	1
436	0	1
			==> MISSING_ELSE
476	0	3
479	0	1
480	0	1
481	0	1
482	0	1
483	0	1
484	0	1
485	0	1
486	0	1
488	0	1
489	0	1
492	0	1
493	0	1
494	0	1
			==> MISSING_ELSE
496	0	1
497	0	1
			==> MISSING_ELSE
499	0	1
500	0	1
501	0	1
502	0	1
			==> MISSING_ELSE
504	0	1
505	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_scrmbl

	Total	Covered	Percent
Conditions	68	0	0.00
Logical	68	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION 
 Number  Term
      1  (data_state_sel == SelEncDataOut) ? enc_data_out : ((data_state_sel == SelDecDataOut) ? dec_data_out : ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelEncDataOut)
                ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       209
 SUB-EXPRESSION 
 Number  Term
      1  (data_state_sel == SelDecDataOut) ? dec_data_out : ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i)))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelDecDataOut)
                ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       209
 SUB-EXPRESSION ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i))
                 -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelDigestState)
                -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       209
 SUB-EXPRESSION ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i)
                 ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelEncDataOutXor)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDecKeyOut) ? dec_key_out : ((key_state_sel == SelEncKeyOut) ? enc_key_out : ((key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDecKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelEncKeyOut) ? enc_key_out : ((key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelEncKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDecKeyInit)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelEncKeyInit)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDigestConst)
                ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))
                 -----------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDigestChained)
                -----------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDecKeyOut) ? dec_idx_out : ((key_state_sel == SelEncKeyOut) ? enc_idx_out : ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1)))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 SUB-EXPRESSION (key_state_sel == SelDecKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 SUB-EXPRESSION ((key_state_sel == SelEncKeyOut) ? enc_idx_out : ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1))
                 ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 SUB-EXPRESSION (key_state_sel == SelEncKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 SUB-EXPRESSION ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1)
                 ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 SUB-EXPRESSION (key_state_sel == SelDecKeyInit)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       231
 EXPRESSION (digest_init ? otp_digest_iv_mux : enc_data_out_xor)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       234
 EXPRESSION (valid_q ? data_state_q : 0)
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       341
 EXPRESSION (digest_mode_q == ChainedMode)
            ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       350
 EXPRESSION ((digest_mode_q == ChainedMode) ? SelDigestChained : SelDigestInput)
             ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       350
 SUB-EXPRESSION (digest_mode_q == ChainedMode)
                ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       379
 EXPRESSION (cnt == LastPresentRound)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       392
 EXPRESSION (cnt == LastPresentRound)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       406
 EXPRESSION (cnt == LastPresentRound)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : otp_ctrl_scrmbl

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	10	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DecryptSt	329	Not Covered
DigestSt	348	Not Covered
EncryptSt	335	Not Covered
ErrorSt	435	Not Covered
IdleSt	380	Not Covered

transitions	Line No.	Covered	Tests
DecryptSt->ErrorSt	435	Not Covered
DecryptSt->IdleSt	380	Not Covered
DigestSt->ErrorSt	435	Not Covered
DigestSt->IdleSt	407	Not Covered
EncryptSt->ErrorSt	435	Not Covered
EncryptSt->IdleSt	393	Not Covered
IdleSt->DecryptSt	329	Not Covered
IdleSt->DigestSt	348	Not Covered
IdleSt->EncryptSt	335	Not Covered
IdleSt->ErrorSt	435	Not Covered

---

Branch Coverage for Module : otp_ctrl_scrmbl

	Line No.	Total	Covered	Percent
Branches		52	0	0.00
TERNARY	209	5	0	0.00
TERNARY	215	7	0	0.00
TERNARY	224	4	0	0.00
TERNARY	231	2	0	0.00
TERNARY	234	2	0	0.00
CASE	318	18	0	0.00
IF	434	2	0	0.00
IF	476	2	0	0.00
IF	479	10	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	209	((data_state_sel == SelEncDataOut)) ? 
-2-:	209	((data_state_sel == SelDecDataOut)) ? 
-3-:	209	((data_state_sel == SelDigestState)) ? 
-4-:	209	((data_state_sel == SelEncDataOutXor)) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	215	((key_state_sel == SelDecKeyOut)) ? 
-2-:	215	((key_state_sel == SelEncKeyOut)) ? 
-3-:	215	((key_state_sel == SelDecKeyInit)) ? 
-4-:	215	((key_state_sel == SelEncKeyInit)) ? 
-5-:	215	((key_state_sel == SelDigestConst)) ? 
-6-:	215	((key_state_sel == SelDigestChained)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Not Covered
0	1	-	-	-	-	Not Covered
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Not Covered
0	0	0	0	1	-	Not Covered
0	0	0	0	0	1	Not Covered
0	0	0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	224	((key_state_sel == SelDecKeyOut)) ? 
-2-:	224	((key_state_sel == SelEncKeyOut)) ? 
-3-:	224	((key_state_sel == SelDecKeyInit)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	231	(digest_init) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	234	(valid_q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	318	case (state_q)
-2-:	326	if (valid_i)
-3-:	327	case (cmd_i)
-4-:	341	if ((digest_mode_q == ChainedMode))
-5-:	350	((digest_mode_q == ChainedMode)) ? 
-6-:	379	if ((cnt == LastPresentRound))
-7-:	392	if ((cnt == LastPresentRound))
-8-:	406	if ((cnt == LastPresentRound))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	Decrypt	-	-	-	-	-	Not Covered
IdleSt	1	Encrypt	-	-	-	-	-	Not Covered
IdleSt	1	LoadShadow	1	-	-	-	-	Not Covered
IdleSt	1	LoadShadow	0	-	-	-	-	Not Covered
IdleSt	1	Digest	-	1	-	-	-	Not Covered
IdleSt	1	Digest	-	0	-	-	-	Not Covered
IdleSt	1	DigestInit	-	-	-	-	-	Not Covered
IdleSt	1	DigestFinalize	-	-	-	-	-	Not Covered
IdleSt	1	default	-	-	-	-	-	Not Covered
IdleSt	0	-	-	-	-	-	-	Not Covered
DecryptSt	-	-	-	-	1	-	-	Not Covered
DecryptSt	-	-	-	-	0	-	-	Not Covered
EncryptSt	-	-	-	-	-	1	-	Not Covered
EncryptSt	-	-	-	-	-	0	-	Not Covered
DigestSt	-	-	-	-	-	-	1	Not Covered
DigestSt	-	-	-	-	-	-	0	Not Covered
ErrorSt	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	434	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	476	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	479	if ((!rst_ni))
-2-:	492	if (key_state_en)
-3-:	496	if (data_state_en)
-4-:	499	if (data_shadow_copy)
-5-:	501	if (data_shadow_load)
-6-:	504	if (digest_state_en)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Not Covered
0	1	-	-	-	-	Not Covered
0	0	-	-	-	-	Not Covered
0	-	1	-	-	-	Not Covered
0	-	0	-	-	-	Not Covered
0	-	-	1	-	-	Not Covered
0	-	-	0	1	-	Not Covered
0	-	-	0	0	-	Not Covered
0	-	-	-	-	1	Not Covered
0	-	-	-	-	0	Not Covered

Line Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl

	Line No.	Total	Covered	Percent
TOTAL		120	0	0.00
ALWAYS	141	10	0	0.00
CONT_ASSIGN	199	1	0	0.00
CONT_ASSIGN	200	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	202	1	0	0.00
CONT_ASSIGN	209	1	0	0.00
CONT_ASSIGN	215	1	0	0.00
CONT_ASSIGN	224	1	0	0.00
CONT_ASSIGN	230	1	0	0.00
CONT_ASSIGN	231	1	0	0.00
CONT_ASSIGN	234	1	0	0.00
CONT_ASSIGN	281	1	0	0.00
ALWAYS	302	75	0	0.00
ALWAYS	476	3	0	0.00
ALWAYS	479	21	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
141	0	1
142	0	1
143	0	1
144	0	1
146	0	1
148	0	1
151	0	1
155	0	1
156	0	1
157	0	1
199	0	1
200	0	1
201	0	1
202	0	1
209	0	1
215	0	1
224	0	1
230	0	1
231	0	1
234	0	1
281	0	1
302	0	1
303	0	1
304	0	1
305	0	1
306	0	1
307	0	1
308	0	1
309	0	1
310	0	1
311	0	1
312	0	1
313	0	1
314	0	1
315	0	1
316	0	1
318	0	1
323	0	1
324	0	1
326	0	1
327	0	1
329	0	1
330	0	1
331	0	1
332	0	1
335	0	1
336	0	1
337	0	1
338	0	1
341	0	1
342	0	1
344	0	1
348	0	1
349	0	1
350	0	1
351	0	1
352	0	1
355	0	1
356	0	1
357	0	1
360	0	1
361	0	1
362	0	1
363	0	1
364	0	1
365	0	1
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
374	0	1
375	0	1
376	0	1
377	0	1
378	0	1
379	0	1
380	0	1
381	0	1
			==> MISSING_ELSE
387	0	1
388	0	1
389	0	1
390	0	1
391	0	1
392	0	1
393	0	1
394	0	1
			==> MISSING_ELSE
401	0	1
402	0	1
403	0	1
404	0	1
405	0	1
406	0	1
407	0	1
408	0	1
410	0	1
414	0	1
			==> MISSING_ELSE
420	0	1
434	0	1
435	0	1
436	0	1
			==> MISSING_ELSE
476	0	3
479	0	1
480	0	1
481	0	1
482	0	1
483	0	1
484	0	1
485	0	1
486	0	1
488	0	1
489	0	1
492	0	1
493	0	1
494	0	1
			==> MISSING_ELSE
496	0	1
497	0	1
			==> MISSING_ELSE
499	0	1
500	0	1
501	0	1
502	0	1
			==> MISSING_ELSE
504	0	1
505	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl

	Total	Covered	Percent
Conditions	68	0	0.00
Logical	68	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION 
 Number  Term
      1  (data_state_sel == SelEncDataOut) ? enc_data_out : ((data_state_sel == SelDecDataOut) ? dec_data_out : ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelEncDataOut)
                ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       209
 SUB-EXPRESSION 
 Number  Term
      1  (data_state_sel == SelDecDataOut) ? dec_data_out : ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i)))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelDecDataOut)
                ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       209
 SUB-EXPRESSION ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i))
                 -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelDigestState)
                -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       209
 SUB-EXPRESSION ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i)
                 ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelEncDataOutXor)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDecKeyOut) ? dec_key_out : ((key_state_sel == SelEncKeyOut) ? enc_key_out : ((key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDecKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelEncKeyOut) ? enc_key_out : ((key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelEncKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDecKeyInit)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelEncKeyInit)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDigestConst)
                ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))
                 -----------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDigestChained)
                -----------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDecKeyOut) ? dec_idx_out : ((key_state_sel == SelEncKeyOut) ? enc_idx_out : ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1)))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 SUB-EXPRESSION (key_state_sel == SelDecKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 SUB-EXPRESSION ((key_state_sel == SelEncKeyOut) ? enc_idx_out : ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1))
                 ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 SUB-EXPRESSION (key_state_sel == SelEncKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 SUB-EXPRESSION ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1)
                 ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       224
 SUB-EXPRESSION (key_state_sel == SelDecKeyInit)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       231
 EXPRESSION (digest_init ? otp_digest_iv_mux : enc_data_out_xor)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       234
 EXPRESSION (valid_q ? data_state_q : 0)
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       341
 EXPRESSION (digest_mode_q == ChainedMode)
            ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       350
 EXPRESSION ((digest_mode_q == ChainedMode) ? SelDigestChained : SelDigestInput)
             ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       350
 SUB-EXPRESSION (digest_mode_q == ChainedMode)
                ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       379
 EXPRESSION (cnt == LastPresentRound)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       392
 EXPRESSION (cnt == LastPresentRound)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       406
 EXPRESSION (cnt == LastPresentRound)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	10	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DecryptSt	329	Not Covered
DigestSt	348	Not Covered
EncryptSt	335	Not Covered
ErrorSt	435	Not Covered
IdleSt	380	Not Covered

transitions	Line No.	Covered	Tests
DecryptSt->ErrorSt	435	Not Covered
DecryptSt->IdleSt	380	Not Covered
DigestSt->ErrorSt	435	Not Covered
DigestSt->IdleSt	407	Not Covered
EncryptSt->ErrorSt	435	Not Covered
EncryptSt->IdleSt	393	Not Covered
IdleSt->DecryptSt	329	Not Covered
IdleSt->DigestSt	348	Not Covered
IdleSt->EncryptSt	335	Not Covered
IdleSt->ErrorSt	435	Not Covered

---

Branch Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl

	Line No.	Total	Covered	Percent
Branches		51	0	0.00
TERNARY	209	5	0	0.00
TERNARY	215	7	0	0.00
TERNARY	224	4	0	0.00
TERNARY	231	2	0	0.00
TERNARY	234	2	0	0.00
CASE	318	17	0	0.00
IF	434	2	0	0.00
IF	476	2	0	0.00
IF	479	10	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	209	((data_state_sel == SelEncDataOut)) ? 
-2-:	209	((data_state_sel == SelDecDataOut)) ? 
-3-:	209	((data_state_sel == SelDigestState)) ? 
-4-:	209	((data_state_sel == SelEncDataOutXor)) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	215	((key_state_sel == SelDecKeyOut)) ? 
-2-:	215	((key_state_sel == SelEncKeyOut)) ? 
-3-:	215	((key_state_sel == SelDecKeyInit)) ? 
-4-:	215	((key_state_sel == SelEncKeyInit)) ? 
-5-:	215	((key_state_sel == SelDigestConst)) ? 
-6-:	215	((key_state_sel == SelDigestChained)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Not Covered
0	1	-	-	-	-	Not Covered
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Not Covered
0	0	0	0	1	-	Not Covered
0	0	0	0	0	1	Not Covered
0	0	0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	224	((key_state_sel == SelDecKeyOut)) ? 
-2-:	224	((key_state_sel == SelEncKeyOut)) ? 
-3-:	224	((key_state_sel == SelDecKeyInit)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	231	(digest_init) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	234	(valid_q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	318	case (state_q)
-2-:	326	if (valid_i)
-3-:	327	case (cmd_i)
-4-:	341	if ((digest_mode_q == ChainedMode))
-5-:	350	((digest_mode_q == ChainedMode)) ? 
-6-:	379	if ((cnt == LastPresentRound))
-7-:	392	if ((cnt == LastPresentRound))
-8-:	406	if ((cnt == LastPresentRound))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	Decrypt	-	-	-	-	-	Not Covered
IdleSt	1	Encrypt	-	-	-	-	-	Not Covered
IdleSt	1	LoadShadow	1	-	-	-	-	Not Covered
IdleSt	1	LoadShadow	0	-	-	-	-	Not Covered
IdleSt	1	Digest	-	1	-	-	-	Not Covered
IdleSt	1	Digest	-	0	-	-	-	Not Covered
IdleSt	1	DigestInit	-	-	-	-	-	Not Covered
IdleSt	1	DigestFinalize	-	-	-	-	-	Not Covered
IdleSt	1	default	-	-	-	-	-	Excluded		VC_COV_UNR
IdleSt	0	-	-	-	-	-	-	Not Covered
DecryptSt	-	-	-	-	1	-	-	Not Covered
DecryptSt	-	-	-	-	0	-	-	Not Covered
EncryptSt	-	-	-	-	-	1	-	Not Covered
EncryptSt	-	-	-	-	-	0	-	Not Covered
DigestSt	-	-	-	-	-	-	1	Not Covered
DigestSt	-	-	-	-	-	-	0	Not Covered
ErrorSt	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	434	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	476	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	479	if ((!rst_ni))
-2-:	492	if (key_state_en)
-3-:	496	if (data_state_en)
-4-:	499	if (data_shadow_copy)
-5-:	501	if (data_shadow_load)
-6-:	504	if (digest_state_en)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Not Covered
0	1	-	-	-	-	Not Covered
0	0	-	-	-	-	Not Covered
0	-	1	-	-	-	Not Covered
0	-	0	-	-	-	Not Covered
0	-	-	1	-	-	Not Covered
0	-	-	0	1	-	Not Covered
0	-	-	0	0	-	Not Covered
0	-	-	-	-	1	Not Covered
0	-	-	-	-	0	Not Covered