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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A	0	0	472167808	471243012	0	3429
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A	0	0	1143	1143	0	0
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.OutputsKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	472167808	471243012	0	3429
tb.dut.u_prim_lc_sync_dft_en.NumCopiesMustBeGreaterZero_A	0	0	1143	1143	0	0
tb.dut.u_prim_lc_sync_dft_en.OutputsKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A	0	0	472167808	471243012	0	3429
tb.dut.u_prim_lc_sync_escalate_en.NumCopiesMustBeGreaterZero_A	0	0	1143	1143	0	0
tb.dut.u_prim_lc_sync_escalate_en.OutputsKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A	0	0	472167808	471243012	0	3429
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A	0	0	1143	1143	0	0
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.OutputsKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	472167808	471243012	0	3429
tb.dut.u_prim_lc_sync_seed_hw_rd_en.NumCopiesMustBeGreaterZero_A	0	0	1143	1143	0	0
tb.dut.u_prim_lc_sync_seed_hw_rd_en.OutputsKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A	0	0	472167808	471243012	0	3429
tb.dut.u_reg_core.en2addrHit	0	0	475093535	9082400	0	0
tb.dut.u_reg_core.reAfterRv	0	0	475093535	9082400	0	0
tb.dut.u_reg_core.rePulse	0	0	475093535	7266520	0	0
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck	0	0	1318	1318	0	0
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A	0	0	1318	1318	0	0
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert	0	0	1318	1318	0	0
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A	0	0	1318	1318	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1318	1318	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1318	1318	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A	0	0	1318	1318	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1318	1318	0	0
tb.dut.u_reg_core.u_socket.NotOverflowed_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	475093535	60944159	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1318	1318	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	475093535	52649202	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1318	1318	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	475093535	25696270	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1318	1318	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	475093535	19110974	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1318	1318	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	475093535	25650360	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1318	1318	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	475093535	33538228	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	475093535	474161771	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1318	1318	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	1318	1318	0	0
tb.dut.u_reg_core.wePulse	0	0	475093535	1815880	0	0
tb.dut.u_scrmbl_mtx.CheckHotOne_A	0	0	472167808	471284346	0	0
tb.dut.u_scrmbl_mtx.CheckNGreaterZero_A	0	0	1143	1143	0	0
tb.dut.u_scrmbl_mtx.GrantKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_scrmbl_mtx.IdxKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_scrmbl_mtx.NoReadyValidNoGrant_A	0	0	472167808	407300034	0	0
tb.dut.u_scrmbl_mtx.ReqImpliesValid_A	0	0	472167808	63984312	0	0
tb.dut.u_scrmbl_mtx.ValidKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.AddrOutKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.DataIntgOptions_A	0	0	1143	1143	0	0
tb.dut.u_tlul_adapter_sram.ReqOutKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.SramDwHasByteGranularity_A	0	0	1143	1143	0	0
tb.dut.u_tlul_adapter_sram.SramDwIsMultipleOfTlulWidth_A	0	0	1143	1143	0	0
tb.dut.u_tlul_adapter_sram.TlOutKnownIfFifoKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.TlOutValidKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.WdataOutKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.WeOutKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.WmaskOutKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.adapterNoReadOrWrite	0	0	1143	1143	0	0
tb.dut.u_tlul_adapter_sram.rvalidHighReqFifoEmpty	0	0	472167808	100012	0	0
tb.dut.u_tlul_adapter_sram.rvalidHighWhenRspFifoFull	0	0	472167808	100012	0	0
tb.dut.u_tlul_adapter_sram.u_err.dataWidthOnly32_A	0	0	1143	1143	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.DataKnown_A	0	0	472167808	19641658	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.DepthKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.RvalidKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.WreadyKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	472167808	19641658	0	0
tb.dut.u_tlul_adapter_sram.u_rsp_gen.DataWidthCheck_A	0	0	1143	1143	0	0
tb.dut.u_tlul_adapter_sram.u_rsp_gen.PayLoadWidthCheck	0	0	1143	1143	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.DataKnown_A	0	0	472167808	235265	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.DepthKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.RvalidKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.WreadyKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	472167808	235265	0	0
tb.dut.u_tlul_adapter_sram.u_sram_byte.SramReadbackAndIntg	0	0	1143	1143	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DataKnown_A	0	0	472167808	652035	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DepthKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.RvalidKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.WreadyKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	472167808	652035	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1143	1143	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.OutputsKnown_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_lc_gate.u_state_regs.AssertConnected_A	0	0	1143	1143	0	0
tb.dut.u_tlul_lc_gate.u_state_regs_A	0	0	472167808	471284346	0	0
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1143	1143	0	0
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1143	1143	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_arb.RoundRobin_A	0	0	472167808	0	0	1143
tb.dut.u_otp_arb.RoundRobin_A	0	0	472167808	0	0	1143
tb.dut.u_otp_ctrl_kdi.u_req_arb.RoundRobin_A	0	0	472167808	0	0	1143
tb.dut.u_prim_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	472167808	0	0	1143
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A	0	0	472167808	471243012	0	3429
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	472167808	471243012	0	3429
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A	0	0	472167808	471243012	0	3429
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A	0	0	472167808	471243012	0	3429
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	472167808	471243012	0	3429
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A	0	0	472167808	471243012	0	3429
tb.dut.u_scrmbl_mtx.RoundRobin_A	0	0	472167808	0	0	1143

Assertions Without Attempts:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	475094457	921	921	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	475094457	365	365	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	475094457	367	367	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	475094457	247	247	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	475094457	40	40	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	475094457	186	186	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	475094457	113	113	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	475094457	3709	3709	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	475094457	6183	6183	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	475094457	3453594	3453594	1226
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	475094457	318	318	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	475094457	150	150	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	475094457	156	156	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	475094457	112	112	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	475094457	13	13	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	475094457	92	92	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	475094457	88	88	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	475094457	987	987	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	475094457	2013	2013	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	475094457	53514	53514	58

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	475094457	921	921	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	475094457	365	365	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	475094457	367	367	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	475094457	247	247	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	475094457	40	40	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	475094457	186	186	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	475094457	113	113	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	475094457	3709	3709	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	475094457	6183	6183	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	475094457	3453594	3453594	1226
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	475094457	318	318	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	475094457	150	150	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	475094457	156	156	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	475094457	112	112	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	475094457	13	13	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	475094457	92	92	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	475094457	88	88	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	475094457	987	987	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	475094457	2013	2013	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	475094457	53514	53514	58