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Module Instance : tb.dut.u_otp_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.25 98.07 97.16 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.25 98.07 97.16 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.19 94.16 96.15 97.04 96.43 97.18 dut


Subtrees :
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Module Instances:
tb.dut.u_otp_arb
Line Coverage for Instance : tb.dut.u_otp_arb
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61 logic unused_req_chk; 62 1/1 assign unused_req_chk = req_chk_i; Tests: T1 T2 T3  63 64 `ASSERT_INIT(CheckNGreaterZero_A, N > 0) 65 66 // this case is basically just a bypass 67 if (N == 1) begin : gen_degenerate_case 68 69 assign valid_o = req_i[0]; 70 assign data_o = data_i[0]; 71 assign gnt_o[0] = valid_o & ready_i; 72 assign idx_o = '0; 73 74 end else begin : gen_normal_case 75 76 // align to powers of 2 for simplicity 77 // a full binary tree with N levels has 2**N + 2**N-1 nodes 78 logic [2**(IdxW+1)-2:0] req_tree; 79 logic [2**(IdxW+1)-2:0] prio_tree; 80 logic [2**(IdxW+1)-2:0] sel_tree; 81 logic [2**(IdxW+1)-2:0] mask_tree; 82 logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree; 83 logic [2**(IdxW+1)-2:0][DW-1:0] data_tree; 84 logic [N-1:0] prio_mask_d, prio_mask_q; 85 86 for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree 87 // 88 // level+1 C0 C1 <- "Base1" points to the first node on "level+1", 89 // \ / these nodes are the children of the nodes one level below 90 // level Pa <- "Base0", points to the first node on "level", 91 // these nodes are the parents of the nodes one level above 92 // 93 // hence we have the following indices for the Pa, C0, C1 nodes: 94 // Pa = 2**level - 1 + offset = Base0 + offset 95 // C0 = 2**(level+1) - 1 + 2*offset = Base1 + 2*offset 96 // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1 97 // 98 localparam int Base0 = (2**level)-1; 99 localparam int Base1 = (2**(level+1))-1; 100 101 for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level 102 localparam int Pa = Base0 + offset; 103 localparam int C0 = Base1 + 2*offset; 104 localparam int C1 = Base1 + 2*offset + 1; 105 106 // this assigns the gated interrupt source signals, their 107 // corresponding IDs and priorities to the tree leafs 108 if (level == IdxW) begin : gen_leafs 109 if (offset < N) begin : gen_assign 110 // forward path (requests and data) 111 // all requests inputs are assigned to the request tree 112 13/14 ==> assign req_tree[Pa] = req_i[offset]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  113 // we basically split the incoming request vector into two halves with the following 114 // priority assignment. the prio_mask_q register contains a prefix sum that has been 115 // computed using the last winning index, and hence masks out all requests at offsets 116 // lower or equal the previously granted index. hence, all higher indices are considered 117 // first in the arbitration tree nodes below, before considering the lower indices. 118 14/14 assign prio_tree[Pa] = req_i[offset] & prio_mask_q[offset]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  119 // input for the index muxes (used to compute the winner index) 120 assign idx_tree[Pa] = offset; 121 // input for the data muxes 122 13/14 ==> assign data_tree[Pa] = data_i[offset]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  123 124 // backward path (grants and prefix sum) 125 // grant if selected, ready and request asserted 126 14/14 assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  127 // only update mask if there is a valid request 128 14/14 assign prio_mask_d[offset] = (|req_i) ? Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  129 mask_tree[Pa] | sel_tree[Pa] & ~ready_i : 130 prio_mask_q[offset]; 131 end else begin : gen_tie_off 132 // forward path 133 assign req_tree[Pa] = '0; 134 assign prio_tree[Pa] = '0; 135 assign idx_tree[Pa] = '0; 136 assign data_tree[Pa] = '0; 137 logic unused_sigs; 138 2/2 assign unused_sigs = ^{mask_tree[Pa], Tests: T1 T2 T3  | T1 T2 T3  139 sel_tree[Pa]}; 140 end 141 // this creates the node assignments 142 end else begin : gen_nodes 143 // local helper variable 144 logic sel; 145 146 // forward path (requests and data) 147 // each node looks at its two children, and selects the one with higher priority 148 14/14(1 unreachable) assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  149 // propagate requests 150 14/14(1 unreachable) assign req_tree[Pa] = req_tree[C0] | req_tree[C1]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  151 14/14(1 unreachable) assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  152 // data and index muxes 153 // Note: these ternaries have triggered a synthesis bug in Vivado versions older 154 // than 2020.2. If the problem resurfaces again, have a look at issue #1408. 155 14/15 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  156 14/15 ==> assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  157 158 // backward path (grants and prefix sum) 159 // this propagates the selction index back and computes a hot one mask 160 14/14(1 unreachable) assign sel_tree[C0] = sel_tree[Pa] & ~sel; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  161 15/15 assign sel_tree[C1] = sel_tree[Pa] & sel; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  162 // this performs a prefix sum for masking the input requests in the next cycle 163 11/11(4 unreachable) assign mask_tree[C0] = mask_tree[Pa]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  164 15/15 assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  165 end 166 end : gen_level 167 end : gen_tree 168 169 // the results can be found at the tree root 170 if (EnDataPort) begin : gen_data_port 171 1/1 assign data_o = data_tree[0]; Tests: T1 T2 T3  172 end else begin : gen_no_dataport 173 logic [DW-1:0] unused_data; 174 assign unused_data = data_tree[0]; 175 assign data_o = '1; 176 end 177 178 // This index is unused. 179 logic unused_prio_tree; 180 1/1 assign unused_prio_tree = prio_tree[0]; Tests: T1 T2 T3  181 182 1/1 assign idx_o = idx_tree[0]; Tests: T1 T2 T3  183 1/1 assign valid_o = req_tree[0]; Tests: T1 T2 T3  184 185 // the select tree computes a hot one signal that indicates which request is currently selected 186 assign sel_tree[0] = 1'b1; 187 // the mask tree is basically a prefix sum of the hot one select signal computed above 188 assign mask_tree[0] = 1'b0; 189 190 always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg 191 1/1 if (!rst_ni) begin Tests: T1 T2 T3  192 1/1 prio_mask_q <= '0; Tests: T1 T2 T3  193 end else begin 194 1/1 prio_mask_q <= prio_mask_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_otp_arb
TotalCoveredPercent
Conditions52951497.16
Logical52951497.16
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
118-15196.13
151-16498.63

Branch Coverage for Instance : tb.dut.u_otp_arb
Line No.TotalCoveredPercent
Branches 88 88 100.00
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IF 191 2 2 100.00


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
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1 Covered T1,T2,T3
0 Covered T1,T2,T3


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
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1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
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1 Covered T1,T2,T3
0 Covered T1,T2,T3


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
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1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
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1 Covered T1,T2,T3
0 Covered T1,T2,T3


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
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1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
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1 Covered T1,T2,T3
0 Covered T1,T2,T3


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
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1 Covered T1,T2,T3
0 Covered T1,T2,T3


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
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1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==> (Unreachable)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==> (Unreachable)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


191 if (!rst_ni) begin -1- 192 prio_mask_q <= '0; ==> 193 end else begin 194 prio_mask_q <= prio_mask_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_otp_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 472167808 471284346 0 0
CheckNGreaterZero_A 1143 1143 0 0
GntImpliesReady_A 472167808 2284935 0 0
GntImpliesValid_A 472167808 2284935 0 0
GrantKnown_A 472167808 471284346 0 0
IdxKnown_A 472167808 471284346 0 0
IndexIsCorrect_A 472167808 2284935 0 0
LockArbDecision_A 472167808 6961741 0 0
NoReadyValidNoGrant_A 472167808 12325386 0 0
ReadyAndValidImplyGrant_A 472167808 2284935 0 0
ReqAndReadyImplyGrant_A 472167808 2284935 0 0
ReqImpliesValid_A 472167808 9248158 0 0
ReqStaysHighUntilGranted0_M 472167808 6961741 0 0
RoundRobin_A 472167808 0 0 1143
ValidKnown_A 472167808 471284346 0 0
gen_data_port_assertion.DataFlow_A 472167808 2284935 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 472167808 471284346 0 0
T1 22574 22128 0 0
T2 4421 4340 0 0
T3 8781 8578 0 0
T4 44585 44107 0 0
T5 27055 26504 0 0
T6 24416 24094 0 0
T10 5255 5171 0 0
T11 41583 40923 0 0
T12 28247 27926 0 0
T13 70439 70364 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1143 1143 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 472167808 2284935 0 0
T1 22574 290 0 0
T2 4421 111 0 0
T3 8781 144 0 0
T4 44585 485 0 0
T5 27055 560 0 0
T6 24416 373 0 0
T10 5255 55 0 0
T11 41583 863 0 0
T12 28247 284 0 0
T13 70439 1356 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 472167808 2284935 0 0
T1 22574 290 0 0
T2 4421 111 0 0
T3 8781 144 0 0
T4 44585 485 0 0
T5 27055 560 0 0
T6 24416 373 0 0
T10 5255 55 0 0
T11 41583 863 0 0
T12 28247 284 0 0
T13 70439 1356 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 472167808 471284346 0 0
T1 22574 22128 0 0
T2 4421 4340 0 0
T3 8781 8578 0 0
T4 44585 44107 0 0
T5 27055 26504 0 0
T6 24416 24094 0 0
T10 5255 5171 0 0
T11 41583 40923 0 0
T12 28247 27926 0 0
T13 70439 70364 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 472167808 471284346 0 0
T1 22574 22128 0 0
T2 4421 4340 0 0
T3 8781 8578 0 0
T4 44585 44107 0 0
T5 27055 26504 0 0
T6 24416 24094 0 0
T10 5255 5171 0 0
T11 41583 40923 0 0
T12 28247 27926 0 0
T13 70439 70364 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 472167808 2284935 0 0
T1 22574 290 0 0
T2 4421 111 0 0
T3 8781 144 0 0
T4 44585 485 0 0
T5 27055 560 0 0
T6 24416 373 0 0
T10 5255 55 0 0
T11 41583 863 0 0
T12 28247 284 0 0
T13 70439 1356 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 472167808 6961741 0 0
T1 22574 2592 0 0
T2 4421 624 0 0
T3 8781 676 0 0
T4 44585 3744 0 0
T5 27055 2925 0 0
T6 24416 2435 0 0
T10 5255 624 0 0
T11 41583 6167 0 0
T12 28247 2593 0 0
T13 70439 624 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 472167808 12325386 0 0
T1 22574 1724 0 0
T2 4421 768 0 0
T3 8781 1247 0 0
T4 44585 3010 0 0
T5 27055 3816 0 0
T6 24416 2298 0 0
T10 5255 242 0 0
T11 41583 4778 0 0
T12 28247 1771 0 0
T13 70439 12034 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 472167808 2284935 0 0
T1 22574 290 0 0
T2 4421 111 0 0
T3 8781 144 0 0
T4 44585 485 0 0
T5 27055 560 0 0
T6 24416 373 0 0
T10 5255 55 0 0
T11 41583 863 0 0
T12 28247 284 0 0
T13 70439 1356 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 472167808 2284935 0 0
T1 22574 290 0 0
T2 4421 111 0 0
T3 8781 144 0 0
T4 44585 485 0 0
T5 27055 560 0 0
T6 24416 373 0 0
T10 5255 55 0 0
T11 41583 863 0 0
T12 28247 284 0 0
T13 70439 1356 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 472167808 9248158 0 0
T1 22574 2882 0 0
T2 4421 735 0 0
T3 8781 822 0 0
T4 44585 4229 0 0
T5 27055 3486 0 0
T6 24416 2809 0 0
T10 5255 679 0 0
T11 41583 7034 0 0
T12 28247 2879 0 0
T13 70439 1980 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 472167808 6961741 0 0
T1 22574 2592 0 0
T2 4421 624 0 0
T3 8781 676 0 0
T4 44585 3744 0 0
T5 27055 2925 0 0
T6 24416 2435 0 0
T10 5255 624 0 0
T11 41583 6167 0 0
T12 28247 2593 0 0
T13 70439 624 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 472167808 0 0 1143

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 472167808 471284346 0 0
T1 22574 22128 0 0
T2 4421 4340 0 0
T3 8781 8578 0 0
T4 44585 44107 0 0
T5 27055 26504 0 0
T6 24416 24094 0 0
T10 5255 5171 0 0
T11 41583 40923 0 0
T12 28247 27926 0 0
T13 70439 70364 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 472167808 2284935 0 0
T1 22574 290 0 0
T2 4421 111 0 0
T3 8781 144 0 0
T4 44585 485 0 0
T5 27055 560 0 0
T6 24416 373 0 0
T10 5255 55 0 0
T11 41583 863 0 0
T12 28247 284 0 0
T13 70439 1356 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%