Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_unbuf_access_lock_cg_wrap::unbuf_access_lock_cg

Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_access_lock_cg_wrap::unbuf_access_lock_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

5 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
buf_err_code_cg_wrap[CreatorSwCfgIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[OwnerSwCfgIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[RotCreatorAuthStateIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[VendorTestIdx]	100.00	1	100	1	64	64

---

Group Instance : buf_err_code_cg_wrap[CreatorSwCfgIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OwnerSwCfgIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[VendorTestIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

21699

1

T2

6

T3

16

T4

1

write_op

5244

1

T2

2

T3

1

T4

1

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10466

1

T2

8

T3

1

T4

2

auto[1]

16477

1

T3

16

T6

2

T7

7

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19136

1

T2

8

T3

17

T4

2

auto[1]

7807

1

T7

7

T26

15

T18

21

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	4900	1			T2	6		T4	1		T5	2
auto[0]	auto[0]	write_op	2692	1			T2	2		T3	1		T4	1
auto[0]	auto[1]	read_op	2209	1			T7	5		T18	5		T48	3
auto[0]	auto[1]	write_op	665	1			T7	2		T48	2		T65	8
auto[1]	auto[0]	read_op	10387	1			T3	16		T6	2		T7	5
auto[1]	auto[0]	write_op	1157	1			T7	2		T48	1		T9	2
auto[1]	auto[1]	read_op	4203	1			T26	13		T18	13		T48	2
auto[1]	auto[1]	write_op	730	1			T26	2		T18	3		T65	2

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

22262

1

T2

6

T3

12

T5

10

write_op

5214

1

T2

3

T3

1

T4

1

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10628

1

T2

9

T3

1

T4

1

auto[1]

16848

1

T3

12

T6

2

T7

4

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22835

1

T2

9

T3

13

T4

1

auto[1]

4641

1

T17

1

T26

7

T38

4

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	5859	1			T2	6		T5	10		T6	1
auto[0]	auto[0]	write_op	2956	1			T2	3		T3	1		T4	1
auto[0]	auto[1]	read_op	1366	1			T26	1		T48	6		T65	11
auto[0]	auto[1]	write_op	447	1			T17	1		T26	1		T48	2
auto[1]	auto[0]	read_op	12666	1			T3	12		T6	2		T7	4
auto[1]	auto[0]	write_op	1354	1			T17	1		T48	2		T9	1
auto[1]	auto[1]	read_op	2371	1			T26	3		T38	3		T65	15
auto[1]	auto[1]	write_op	457	1			T26	2		T38	1		T65	3

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

22373

1

T2

8

T3

21

T4

2

write_op

5571

1

T2

3

T3

2

T4

1

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10941

1

T2

11

T3

3

T4

3

auto[1]

17003

1

T3

20

T13

20

T17

2

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20259

1

T2

11

T3

23

T4

3

auto[1]

7685

1

T7

2

T17

4

T26

4

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	5039	1			T2	8		T3	1		T4	2
auto[0]	auto[0]	write_op	2765	1			T2	3		T3	2		T4	1
auto[0]	auto[1]	read_op	2314	1			T7	1		T17	2		T26	4
auto[0]	auto[1]	write_op	823	1			T7	1		T17	2		T18	3
auto[1]	auto[0]	read_op	11174	1			T3	20		T13	20		T17	1
auto[1]	auto[0]	write_op	1281	1			T17	1		T48	2		T9	2
auto[1]	auto[1]	read_op	3846	1			T18	3		T65	11		T84	5
auto[1]	auto[1]	write_op	702	1			T18	1		T65	3		T90	2

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

21121

1

T2

8

T3

4

T4

2

write_op

4020

1

T2

4

T3

1

T4

1

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9666

1

T2

12

T3

1

T4

3

auto[1]

15475

1

T3

4

T6

2

T13

8

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22298

1

T2

12

T3

5

T4

3

auto[1]

2843

1

T18

6

T59

7

T39

18

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	6154	1			T2	8		T4	2		T5	10
auto[0]	auto[0]	write_op	2469	1			T2	4		T3	1		T4	1
auto[0]	auto[1]	read_op	859	1			T18	4		T59	5		T39	3
auto[0]	auto[1]	write_op	184	1			T39	1		T96	1		T80	1
auto[1]	auto[0]	read_op	12492	1			T3	4		T6	2		T13	8
auto[1]	auto[0]	write_op	1183	1			T26	1		T18	2		T9	1
auto[1]	auto[1]	read_op	1616	1			T18	2		T59	2		T39	13
auto[1]	auto[1]	write_op	184	1			T39	1		T96	1		T97	1

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

21657

1

T2

14

T3

6

T4

2

write_op

4981

1

T2

6

T3

1

T4

1

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10254

1

T2

20

T3

1

T4

3

auto[1]

16384

1

T3

6

T7

11

T13

20

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18660

1

T2

20

T3

7

T4

3

auto[1]

7978

1

T26

1

T38

1

T18

8

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	4711	1			T2	14		T4	2		T5	6
auto[0]	auto[0]	write_op	2477	1			T2	6		T3	1		T4	1
auto[0]	auto[1]	read_op	2393	1			T26	1		T18	3		T48	3
auto[0]	auto[1]	write_op	673	1			T18	2		T48	2		T65	4
auto[1]	auto[0]	read_op	10282	1			T3	6		T7	8		T13	20
auto[1]	auto[0]	write_op	1190	1			T7	3		T17	1		T8	3
auto[1]	auto[1]	read_op	4271	1			T38	1		T18	2		T48	2
auto[1]	auto[1]	write_op	641	1			T18	1		T48	1		T65	2