Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6970992	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6820886

1

T1

731

T2

257

T3

169

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8148584	1			T1	2138		T2	1528		T3	980
values[0x0]	2163143	1			T1	142		T2	36		T3	91
values[0x1]	3480151	1			T1	131		T2	33		T3	85

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4565515	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9226363

1

T1

1223

T2

667

T3

446

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	46652	1			T1	4		T2	11		T3	6
valid_sources[0x01]	52669	1			T1	8		T2	3		T3	8
valid_sources[0x02]	50955	1			T1	13		T2	9		T3	9
valid_sources[0x03]	61873	1			T1	13		T2	12		T3	3
valid_sources[0x04]	48925	1			T1	9		T2	9		T3	3
valid_sources[0x05]	48123	1			T1	11		T2	10		T3	3
valid_sources[0x06]	63302	1			T1	20		T2	10		T3	1
valid_sources[0x07]	51249	1			T1	8		T2	7		T4	718
valid_sources[0x08]	49764	1			T1	4		T2	10		T3	10
valid_sources[0x09]	48197	1			T1	2		T2	2		T3	8
valid_sources[0x0a]	52245	1			T1	9		T2	5		T3	4
valid_sources[0x0b]	56800	1			T1	9		T2	11		T3	8
valid_sources[0x0c]	47785	1			T1	5		T2	10		T3	6
valid_sources[0x0d]	48917	1			T1	14		T2	4		T3	3
valid_sources[0x0e]	53560	1			T1	12		T2	4		T3	6
valid_sources[0x0f]	48011	1			T1	5		T2	1		T3	5
valid_sources[0x10]	47421	1			T1	16		T2	5		T3	5
valid_sources[0x11]	46919	1			T1	10		T2	5		T3	4
valid_sources[0x12]	47465	1			T1	12		T2	10		T3	3
valid_sources[0x13]	55149	1			T1	6		T2	5		T3	6
valid_sources[0x14]	55095	1			T1	3		T2	4		T3	4
valid_sources[0x15]	57834	1			T1	9		T2	5		T3	1
valid_sources[0x16]	52086	1			T1	11		T2	8		T3	7
valid_sources[0x17]	48994	1			T1	7		T2	5		T3	6
valid_sources[0x18]	57511	1			T1	16		T2	5		T3	2
valid_sources[0x19]	48234	1			T1	11		T2	5		T3	6
valid_sources[0x1a]	60332	1			T1	8		T2	3		T3	6
valid_sources[0x1b]	56503	1			T1	13		T2	7		T3	7
valid_sources[0x1c]	66555	1			T1	2		T2	6		T3	5
valid_sources[0x1d]	48747	1			T1	12		T2	5		T3	6
valid_sources[0x1e]	48754	1			T1	8		T2	7		T3	4
valid_sources[0x1f]	50483	1			T1	7		T2	6		T3	1
valid_sources[0x20]	47480	1			T1	12		T2	3		T3	5
valid_sources[0x21]	49049	1			T1	9		T2	4		T3	6
valid_sources[0x22]	51609	1			T1	4		T2	8		T3	7
valid_sources[0x23]	54684	1			T1	7		T2	17		T3	3
valid_sources[0x24]	47236	1			T1	8		T2	6		T3	6
valid_sources[0x25]	83583	1			T1	9		T2	6		T3	4
valid_sources[0x26]	47117	1			T1	13		T2	16		T3	5
valid_sources[0x27]	49323	1			T1	7		T2	5		T3	5
valid_sources[0x28]	48398	1			T1	15		T2	7		T3	7
valid_sources[0x29]	49444	1			T1	5		T2	8		T3	6
valid_sources[0x2a]	121975	1			T1	17		T2	2		T3	4
valid_sources[0x2b]	60009	1			T1	3		T2	1		T3	3
valid_sources[0x2c]	47845	1			T1	11		T2	5		T3	3
valid_sources[0x2d]	50799	1			T1	10		T2	2		T3	4
valid_sources[0x2e]	59981	1			T1	14		T2	13		T3	4
valid_sources[0x2f]	56468	1			T1	11		T2	14		T3	10
valid_sources[0x30]	50052	1			T1	11		T2	2		T3	4
valid_sources[0x31]	52035	1			T1	10		T2	4		T3	5
valid_sources[0x32]	50010	1			T1	13		T2	2		T3	5
valid_sources[0x33]	45432	1			T1	7		T2	7		T3	2
valid_sources[0x34]	48313	1			T1	11		T2	5		T3	1
valid_sources[0x35]	51419	1			T1	6		T2	5		T3	5
valid_sources[0x36]	71676	1			T1	8		T2	10		T3	2
valid_sources[0x37]	47721	1			T1	11		T2	9		T3	4
valid_sources[0x38]	53165	1			T1	10		T2	9		T3	3
valid_sources[0x39]	70518	1			T1	9		T2	6		T3	3
valid_sources[0x3a]	57907	1			T1	11		T2	11		T3	3
valid_sources[0x3b]	49238	1			T1	19		T2	7		T3	7
valid_sources[0x3c]	57579	1			T1	9		T2	5		T3	3
valid_sources[0x3d]	53314	1			T1	11		T2	7		T3	5
valid_sources[0x3e]	49873	1			T1	9		T2	3		T3	2
valid_sources[0x3f]	57020	1			T1	10		T2	6		T3	3
valid_sources[0x40]	50551	1			T1	8		T2	4		T3	3
valid_sources[0x41]	52810	1			T1	10		T2	8		T3	4
valid_sources[0x42]	57621	1			T1	7		T2	3		T3	5
valid_sources[0x43]	50836	1			T1	11		T2	3		T3	7
valid_sources[0x44]	86444	1			T1	9		T3	5		T4	637
valid_sources[0x45]	55877	1			T1	12		T2	9		T3	7
valid_sources[0x46]	60057	1			T1	7		T2	3		T3	1
valid_sources[0x47]	46774	1			T1	9		T2	8		T3	7
valid_sources[0x48]	51727	1			T1	5		T2	10		T3	4
valid_sources[0x49]	48255	1			T1	5		T2	4		T3	5
valid_sources[0x4a]	48845	1			T1	3		T2	5		T3	3
valid_sources[0x4b]	63123	1			T1	9		T2	7		T3	3
valid_sources[0x4c]	47793	1			T1	8		T2	6		T3	10
valid_sources[0x4d]	50814	1			T1	10		T2	2		T4	755
valid_sources[0x4e]	50835	1			T1	18		T2	4		T3	6
valid_sources[0x4f]	51668	1			T1	19		T2	8		T3	5
valid_sources[0x50]	52003	1			T1	16		T2	10		T3	5
valid_sources[0x51]	47806	1			T1	11		T2	6		T3	3
valid_sources[0x52]	50112	1			T1	15		T2	5		T3	9
valid_sources[0x53]	48024	1			T1	9		T2	13		T3	4
valid_sources[0x54]	51073	1			T1	5		T2	4		T3	7
valid_sources[0x55]	55611	1			T1	9		T2	7		T3	4
valid_sources[0x56]	50875	1			T1	10		T2	5		T3	5
valid_sources[0x57]	50173	1			T1	11		T2	5		T3	3
valid_sources[0x58]	51318	1			T1	8		T2	9		T3	4
valid_sources[0x59]	49731	1			T1	10		T2	9		T3	8
valid_sources[0x5a]	55073	1			T1	8		T2	6		T3	3
valid_sources[0x5b]	58967	1			T1	5		T2	3		T3	4
valid_sources[0x5c]	60741	1			T1	11		T2	10		T3	4
valid_sources[0x5d]	49934	1			T1	6		T2	15		T3	7
valid_sources[0x5e]	69968	1			T1	8		T2	5		T3	5
valid_sources[0x5f]	50025	1			T1	6		T2	3		T3	5
valid_sources[0x60]	48495	1			T1	10		T2	8		T3	5
valid_sources[0x61]	50271	1			T1	2		T2	2		T3	7
valid_sources[0x62]	47266	1			T1	9		T2	6		T3	2
valid_sources[0x63]	49004	1			T1	9		T2	14		T3	3
valid_sources[0x64]	57269	1			T1	10		T2	20		T3	4
valid_sources[0x65]	48231	1			T1	12		T2	5		T3	8
valid_sources[0x66]	50628	1			T1	9		T2	5		T3	5
valid_sources[0x67]	49884	1			T1	13		T2	7		T3	8
valid_sources[0x68]	51105	1			T1	9		T2	8		T3	9
valid_sources[0x69]	46154	1			T1	7		T2	5		T3	5
valid_sources[0x6a]	58088	1			T1	5		T2	16		T3	3
valid_sources[0x6b]	87702	1			T1	6		T2	17		T3	4
valid_sources[0x6c]	48019	1			T1	11		T2	5		T3	1
valid_sources[0x6d]	50065	1			T1	12		T2	8		T3	8
valid_sources[0x6e]	60212	1			T1	6		T2	6		T4	628
valid_sources[0x6f]	48333	1			T1	7		T2	5		T3	1
valid_sources[0x70]	57316	1			T1	14		T2	12		T3	1
valid_sources[0x71]	52416	1			T1	12		T2	11		T3	5
valid_sources[0x72]	55080	1			T1	6		T2	11		T3	3
valid_sources[0x73]	90373	1			T1	13		T2	8		T3	4
valid_sources[0x74]	46324	1			T1	7		T2	13		T3	2
valid_sources[0x75]	51952	1			T1	8		T2	6		T3	4
valid_sources[0x76]	53103	1			T1	19		T2	10		T3	7
valid_sources[0x77]	48352	1			T1	6		T2	12		T3	5
valid_sources[0x78]	134484	1			T1	9		T2	11		T3	3
valid_sources[0x79]	47801	1			T1	3		T2	5		T3	8
valid_sources[0x7a]	45699	1			T1	14		T2	10		T3	6
valid_sources[0x7b]	70907	1			T1	5		T2	4		T3	4
valid_sources[0x7c]	61117	1			T1	7		T2	9		T3	4
valid_sources[0x7d]	52820	1			T1	11		T2	8		T3	3
valid_sources[0x7e]	94367	1			T1	10		T2	6		T3	2
valid_sources[0x7f]	82962	1			T1	9		T2	16		T3	6
valid_sources[0x80]	60832	1			T1	6		T2	4		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3349563

1

T1

620

T2

230

T3

88

values[0x0]

all_enables

biggest_size

1775463

1

T1

76

T2

12

T3

49

values[0x1]

all_enables

biggest_size

1695860

1

T1

35

T2

15

T3

32

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	229175	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8154480

1

T1

160

T2

20

T4

167029

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2091512	1			T1	80		T2	10		T4	42092
values[0x0]	3053251	1			T1	51		T2	6		T4	62578
values[0x1]	3238892	1			T1	29		T2	4		T4	66940

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	83750	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8299905

1

T1

160

T2

20

T4

170054

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	33530	1			T1	1		T4	670		T6	152
valid_sources[0x01]	33381	1			T4	682		T6	227		T7	102
valid_sources[0x02]	30915	1			T1	1		T4	592		T6	168
valid_sources[0x03]	32486	1			T4	613		T6	167		T7	354
valid_sources[0x04]	32438	1			T4	658		T6	132		T7	163
valid_sources[0x05]	32375	1			T4	698		T6	119		T14	2
valid_sources[0x06]	35688	1			T1	4		T4	693		T6	151
valid_sources[0x07]	32453	1			T4	687		T6	143		T7	193
valid_sources[0x08]	32494	1			T4	655		T6	178		T7	287
valid_sources[0x09]	32466	1			T1	1		T4	743		T6	202
valid_sources[0x0a]	31905	1			T4	732		T6	153		T7	103
valid_sources[0x0b]	32892	1			T1	1		T4	691		T6	122
valid_sources[0x0c]	32707	1			T4	682		T5	2		T6	212
valid_sources[0x0d]	33013	1			T4	594		T6	193		T14	1
valid_sources[0x0e]	33544	1			T4	707		T6	125		T7	87
valid_sources[0x0f]	31303	1			T1	8		T4	695		T5	2
valid_sources[0x10]	30671	1			T4	671		T6	186		T7	134
valid_sources[0x11]	32929	1			T4	592		T5	1		T6	174
valid_sources[0x12]	31623	1			T1	1		T4	664		T5	1
valid_sources[0x13]	33268	1			T4	688		T5	2		T6	140
valid_sources[0x14]	32190	1			T4	630		T5	1		T6	127
valid_sources[0x15]	31296	1			T4	719		T5	5		T6	140
valid_sources[0x16]	31611	1			T4	708		T6	167		T14	1
valid_sources[0x17]	33356	1			T4	656		T6	139		T14	3
valid_sources[0x18]	33226	1			T1	5		T4	677		T6	170
valid_sources[0x19]	32220	1			T4	651		T6	166		T7	62
valid_sources[0x1a]	32355	1			T4	654		T6	176		T7	170
valid_sources[0x1b]	31852	1			T1	1		T4	660		T6	153
valid_sources[0x1c]	33255	1			T4	657		T6	164		T7	186
valid_sources[0x1d]	33598	1			T4	702		T6	129		T7	367
valid_sources[0x1e]	33688	1			T4	679		T6	162		T102	1
valid_sources[0x1f]	33779	1			T4	610		T6	160		T14	1
valid_sources[0x20]	34146	1			T4	621		T6	106		T7	507
valid_sources[0x21]	33615	1			T4	709		T6	149		T7	330
valid_sources[0x22]	33253	1			T4	639		T6	191		T7	202
valid_sources[0x23]	30834	1			T4	710		T5	1		T6	128
valid_sources[0x24]	33234	1			T4	633		T6	159		T103	1
valid_sources[0x25]	34156	1			T4	656		T6	154		T14	2
valid_sources[0x26]	32192	1			T4	739		T6	170		T102	2
valid_sources[0x27]	31782	1			T4	684		T6	177		T14	6
valid_sources[0x28]	33039	1			T4	658		T6	92		T102	1
valid_sources[0x29]	34293	1			T4	725		T5	1		T6	148
valid_sources[0x2a]	32139	1			T4	784		T6	137		T7	314
valid_sources[0x2b]	31324	1			T4	671		T6	140		T7	232
valid_sources[0x2c]	32342	1			T1	1		T4	644		T6	128
valid_sources[0x2d]	31380	1			T4	723		T6	159		T102	1
valid_sources[0x2e]	33563	1			T1	11		T4	621		T6	162
valid_sources[0x2f]	31850	1			T4	750		T6	190		T14	2
valid_sources[0x30]	31769	1			T4	638		T5	1		T6	199
valid_sources[0x31]	34572	1			T4	691		T6	179		T14	1
valid_sources[0x32]	33405	1			T4	698		T6	92		T7	128
valid_sources[0x33]	32315	1			T4	670		T5	3		T6	136
valid_sources[0x34]	31702	1			T4	690		T6	221		T103	1
valid_sources[0x35]	31096	1			T1	1		T4	728		T6	171
valid_sources[0x36]	33519	1			T4	643		T5	1		T6	119
valid_sources[0x37]	32772	1			T4	730		T6	130		T14	1
valid_sources[0x38]	32186	1			T4	704		T5	1		T6	137
valid_sources[0x39]	32943	1			T4	739		T6	106		T7	369
valid_sources[0x3a]	31377	1			T4	702		T6	182		T14	1
valid_sources[0x3b]	32412	1			T4	625		T6	164		T14	1
valid_sources[0x3c]	34812	1			T4	678		T5	1		T6	128
valid_sources[0x3d]	32224	1			T4	656		T5	1		T6	184
valid_sources[0x3e]	33578	1			T4	650		T5	1		T6	139
valid_sources[0x3f]	33319	1			T4	658		T6	178		T7	622
valid_sources[0x40]	33498	1			T4	811		T6	139		T102	1
valid_sources[0x41]	33223	1			T4	647		T6	164		T14	1
valid_sources[0x42]	35298	1			T4	687		T6	158		T103	1
valid_sources[0x43]	33146	1			T1	3		T4	748		T6	118
valid_sources[0x44]	33434	1			T4	747		T6	197		T102	1
valid_sources[0x45]	34089	1			T1	7		T4	581		T6	155
valid_sources[0x46]	32064	1			T4	668		T5	1		T6	171
valid_sources[0x47]	33079	1			T4	659		T6	180		T102	1
valid_sources[0x48]	32090	1			T4	617		T5	1		T6	147
valid_sources[0x49]	33467	1			T1	2		T4	579		T6	138
valid_sources[0x4a]	33436	1			T4	706		T6	169		T7	374
valid_sources[0x4b]	31079	1			T4	678		T6	174		T7	445
valid_sources[0x4c]	33391	1			T4	670		T6	111		T102	2
valid_sources[0x4d]	32612	1			T1	4		T4	777		T5	2
valid_sources[0x4e]	31886	1			T1	10		T4	604		T6	169
valid_sources[0x4f]	32852	1			T4	620		T6	158		T103	1
valid_sources[0x50]	30707	1			T4	745		T5	5		T6	170
valid_sources[0x51]	32813	1			T1	2		T4	655		T6	214
valid_sources[0x52]	33348	1			T4	671		T5	2		T6	135
valid_sources[0x53]	32103	1			T4	725		T6	188		T14	2
valid_sources[0x54]	32552	1			T4	706		T6	141		T7	208
valid_sources[0x55]	31735	1			T4	661		T6	149		T7	370
valid_sources[0x56]	33014	1			T1	3		T4	618		T6	119
valid_sources[0x57]	32700	1			T1	2		T4	731		T5	3
valid_sources[0x58]	32383	1			T4	657		T5	1		T6	158
valid_sources[0x59]	34111	1			T4	708		T6	210		T103	1
valid_sources[0x5a]	30733	1			T4	616		T6	139		T14	1
valid_sources[0x5b]	31214	1			T4	667		T5	1		T6	121
valid_sources[0x5c]	32328	1			T4	620		T6	144		T14	1
valid_sources[0x5d]	35109	1			T4	745		T6	167		T103	1
valid_sources[0x5e]	33578	1			T4	609		T6	150		T103	1
valid_sources[0x5f]	32047	1			T4	617		T5	5		T6	189
valid_sources[0x60]	33011	1			T4	641		T5	2		T6	116
valid_sources[0x61]	31543	1			T4	688		T6	136		T14	1
valid_sources[0x62]	33017	1			T4	734		T5	1		T6	166
valid_sources[0x63]	33449	1			T4	679		T6	104		T7	223
valid_sources[0x64]	34014	1			T4	698		T6	152		T102	1
valid_sources[0x65]	31085	1			T4	657		T6	156		T7	209
valid_sources[0x66]	33226	1			T4	748		T6	142		T14	3
valid_sources[0x67]	34736	1			T4	633		T6	133		T7	448
valid_sources[0x68]	31227	1			T4	701		T6	147		T14	1
valid_sources[0x69]	31151	1			T4	751		T6	126		T103	1
valid_sources[0x6a]	33735	1			T4	631		T6	190		T103	1
valid_sources[0x6b]	32509	1			T4	682		T5	2		T6	134
valid_sources[0x6c]	32469	1			T4	685		T6	163		T102	1
valid_sources[0x6d]	32531	1			T4	659		T6	187		T7	71
valid_sources[0x6e]	32906	1			T4	601		T5	1		T6	186
valid_sources[0x6f]	33202	1			T1	2		T4	730		T6	166
valid_sources[0x70]	32135	1			T4	746		T6	199		T14	2
valid_sources[0x71]	32426	1			T4	688		T6	177		T14	1
valid_sources[0x72]	33784	1			T4	644		T5	2		T6	147
valid_sources[0x73]	33236	1			T1	7		T4	589		T6	191
valid_sources[0x74]	35028	1			T4	774		T6	156		T14	1
valid_sources[0x75]	33632	1			T4	621		T5	1		T6	161
valid_sources[0x76]	32899	1			T4	658		T5	4		T6	206
valid_sources[0x77]	34142	1			T4	625		T5	3		T6	176
valid_sources[0x78]	33101	1			T4	592		T6	145		T103	1
valid_sources[0x79]	32436	1			T1	7		T4	622		T6	141
valid_sources[0x7a]	34108	1			T4	579		T6	151		T14	2
valid_sources[0x7b]	31446	1			T4	647		T6	141		T14	1
valid_sources[0x7c]	32414	1			T4	680		T5	5		T6	166
valid_sources[0x7d]	32800	1			T4	624		T6	160		T103	1
valid_sources[0x7e]	32324	1			T4	742		T6	150		T14	1
valid_sources[0x7f]	32247	1			T4	713		T5	1		T6	170
valid_sources[0x80]	32719	1			T4	630		T6	163		T7	253

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2077368

1

T1

80

T2

10

T4

42055

values[0x0]

all_enables

biggest_size

3037367

1

T1

51

T2

6

T4

62269

values[0x1]

all_enables

biggest_size

3039745

1

T1

29

T2

4

T4

62705