Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4406865	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2515722

1

T1

6

T2

292

T3

374

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5777774	1			T1	4		T2	1048		T3	563
values[0x0]	534008	1			T1	7		T2	149		T3	154
values[0x1]	610805	1			T1	8		T2	167		T3	198

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3241878	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3680709

1

T1

8

T2

613

T3

507

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	34893	1			T4	16		T6	6		T7	7
valid_sources[0x01]	23206	1			T11	1		T4	4		T6	4
valid_sources[0x02]	21539	1			T11	1		T4	5		T6	7
valid_sources[0x03]	25598	1			T4	7		T6	4		T7	8
valid_sources[0x04]	21633	1			T4	3		T6	4		T7	1
valid_sources[0x05]	21312	1			T11	1		T4	8		T6	1
valid_sources[0x06]	19713	1			T4	3		T6	4		T7	2
valid_sources[0x07]	19300	1			T4	1		T6	3		T7	39
valid_sources[0x08]	28422	1			T4	11		T6	4		T7	2
valid_sources[0x09]	25120	1			T4	8		T7	20		T12	12
valid_sources[0x0a]	21050	1			T4	7		T6	2		T7	8
valid_sources[0x0b]	20114	1			T4	6		T6	4		T7	8
valid_sources[0x0c]	22357	1			T4	3		T6	5		T12	7
valid_sources[0x0d]	25057	1			T11	1		T4	3		T6	4
valid_sources[0x0e]	23592	1			T4	6		T6	2		T7	17
valid_sources[0x0f]	28587	1			T4	3		T6	5		T7	3
valid_sources[0x10]	19250	1			T4	2		T6	4		T7	6
valid_sources[0x11]	31614	1			T4	9		T7	7		T12	21
valid_sources[0x12]	19843	1			T1	1		T4	5		T6	3
valid_sources[0x13]	32416	1			T4	3		T6	4		T7	8
valid_sources[0x14]	19422	1			T4	2		T6	5		T7	1
valid_sources[0x15]	24310	1			T11	1		T4	4		T6	2
valid_sources[0x16]	22172	1			T4	2		T7	8		T12	8
valid_sources[0x17]	19494	1			T4	13		T6	10		T7	6
valid_sources[0x18]	23098	1			T4	7		T6	3		T7	8
valid_sources[0x19]	21417	1			T4	3		T6	5		T7	2
valid_sources[0x1a]	22002	1			T4	4		T6	4		T12	22
valid_sources[0x1b]	24928	1			T4	4		T6	16		T7	7
valid_sources[0x1c]	22051	1			T11	1		T4	4		T5	830
valid_sources[0x1d]	35182	1			T4	4		T6	1		T7	36
valid_sources[0x1e]	22136	1			T4	4		T6	4		T7	4
valid_sources[0x1f]	19805	1			T4	4		T6	5		T12	33
valid_sources[0x20]	22484	1			T4	2		T6	3		T7	1
valid_sources[0x21]	19707	1			T4	7		T6	1		T12	19
valid_sources[0x22]	29679	1			T6	1		T7	11		T12	9
valid_sources[0x23]	22541	1			T11	1		T4	4		T6	2
valid_sources[0x24]	22785	1			T4	3		T6	2		T7	8
valid_sources[0x25]	31917	1			T4	3		T6	3		T7	3
valid_sources[0x26]	20530	1			T4	2		T6	3		T7	3
valid_sources[0x27]	78408	1			T6	1		T7	19		T12	12
valid_sources[0x28]	24799	1			T4	6		T6	2		T7	8
valid_sources[0x29]	22593	1			T4	13		T6	3		T12	20
valid_sources[0x2a]	34181	1			T4	3		T6	3		T12	9
valid_sources[0x2b]	19400	1			T11	1		T4	7		T6	2
valid_sources[0x2c]	24871	1			T11	1		T4	3		T6	8
valid_sources[0x2d]	23470	1			T4	5		T6	10		T12	31
valid_sources[0x2e]	25499	1			T6	8		T12	12		T13	10
valid_sources[0x2f]	73836	1			T4	2		T7	31		T12	38
valid_sources[0x30]	22351	1			T4	1		T6	3		T7	17
valid_sources[0x31]	19355	1			T4	2		T6	3		T7	12
valid_sources[0x32]	67688	1			T4	6		T7	1		T12	16
valid_sources[0x33]	25430	1			T4	4		T6	4		T12	19
valid_sources[0x34]	19701	1			T11	1		T4	3		T12	17
valid_sources[0x35]	25569	1			T4	2		T6	3		T7	27
valid_sources[0x36]	23029	1			T2	1364		T4	3		T7	4
valid_sources[0x37]	19130	1			T4	7		T6	7		T7	12
valid_sources[0x38]	19613	1			T4	1		T6	11		T7	10
valid_sources[0x39]	25828	1			T4	5		T6	4		T7	16
valid_sources[0x3a]	21100	1			T4	4		T6	6		T7	18
valid_sources[0x3b]	31833	1			T4	13		T6	1		T7	2
valid_sources[0x3c]	23200	1			T1	1		T11	1		T4	6
valid_sources[0x3d]	29614	1			T4	6		T7	9		T12	11
valid_sources[0x3e]	31552	1			T11	1		T4	6		T6	3
valid_sources[0x3f]	22395	1			T11	1		T4	1		T6	2
valid_sources[0x40]	19697	1			T4	7		T6	3		T7	2
valid_sources[0x41]	111817	1			T4	10		T6	7		T7	3
valid_sources[0x42]	28255	1			T4	2		T6	7		T7	10
valid_sources[0x43]	21738	1			T4	4		T6	4		T12	7
valid_sources[0x44]	37871	1			T4	6		T6	3		T12	7
valid_sources[0x45]	19543	1			T11	1		T4	4		T7	6
valid_sources[0x46]	19809	1			T1	2		T4	2		T7	24
valid_sources[0x47]	24888	1			T11	1		T4	3		T7	11
valid_sources[0x48]	21353	1			T6	12		T7	25		T12	10
valid_sources[0x49]	91159	1			T11	1		T4	1		T6	6
valid_sources[0x4a]	21016	1			T4	11		T6	5		T7	7
valid_sources[0x4b]	24699	1			T6	14		T7	2		T12	27
valid_sources[0x4c]	22311	1			T4	3		T6	2		T7	17
valid_sources[0x4d]	23325	1			T7	1		T12	18		T13	22
valid_sources[0x4e]	25056	1			T4	8		T6	12		T7	11
valid_sources[0x4f]	28410	1			T4	3		T7	7		T12	21
valid_sources[0x50]	20765	1			T1	1		T4	3		T7	2
valid_sources[0x51]	62548	1			T4	4		T6	2		T7	23
valid_sources[0x52]	30058	1			T11	1		T4	9		T6	2
valid_sources[0x53]	21404	1			T6	2		T12	12		T13	12
valid_sources[0x54]	31614	1			T4	3		T6	1		T7	11
valid_sources[0x55]	21452	1			T11	1		T4	7		T6	2
valid_sources[0x56]	85013	1			T4	3		T6	8		T7	5
valid_sources[0x57]	22272	1			T4	5		T6	11		T7	4
valid_sources[0x58]	22398	1			T4	2		T6	1		T7	19
valid_sources[0x59]	22776	1			T4	5		T6	3		T12	10
valid_sources[0x5a]	19646	1			T6	2		T7	5		T12	16
valid_sources[0x5b]	23281	1			T4	3		T6	3		T7	16
valid_sources[0x5c]	31725	1			T4	8		T6	12		T7	26
valid_sources[0x5d]	19618	1			T4	8		T6	4		T7	12
valid_sources[0x5e]	20453	1			T4	5		T6	2		T12	25
valid_sources[0x5f]	23884	1			T1	1		T4	2		T6	6
valid_sources[0x60]	32344	1			T4	4		T6	1		T7	27
valid_sources[0x61]	24763	1			T4	2		T6	1		T7	19
valid_sources[0x62]	24052	1			T4	2		T6	2		T7	12
valid_sources[0x63]	22294	1			T4	5		T7	8		T12	7
valid_sources[0x64]	19460	1			T11	1		T4	5		T6	1
valid_sources[0x65]	33373	1			T4	3		T6	3		T7	1
valid_sources[0x66]	22014	1			T4	2		T7	3		T12	14
valid_sources[0x67]	21561	1			T4	2		T6	3		T7	10
valid_sources[0x68]	37403	1			T4	2		T6	4		T12	20
valid_sources[0x69]	23977	1			T11	1		T4	1		T6	1
valid_sources[0x6a]	27255	1			T4	2		T6	2		T7	6
valid_sources[0x6b]	25319	1			T4	4		T6	3		T12	18
valid_sources[0x6c]	19729	1			T4	2		T7	5		T12	7
valid_sources[0x6d]	35581	1			T4	2		T7	2		T12	22
valid_sources[0x6e]	22758	1			T11	1		T4	6		T6	2
valid_sources[0x6f]	24199	1			T4	21		T6	10		T7	19
valid_sources[0x70]	20840	1			T4	4		T6	13		T7	1
valid_sources[0x71]	19613	1			T4	1		T6	9		T7	5
valid_sources[0x72]	20999	1			T4	3		T6	3		T7	8
valid_sources[0x73]	29506	1			T6	2		T7	3		T12	21
valid_sources[0x74]	23026	1			T4	2		T6	11		T12	13
valid_sources[0x75]	44068	1			T4	5		T7	7		T12	16
valid_sources[0x76]	20369	1			T1	1		T11	2		T4	3
valid_sources[0x77]	19930	1			T4	2		T6	5		T12	27
valid_sources[0x78]	27549	1			T4	2		T6	2		T7	4
valid_sources[0x79]	26373	1			T7	17		T12	26		T13	7
valid_sources[0x7a]	33826	1			T11	1		T4	2		T6	1
valid_sources[0x7b]	30285	1			T4	5		T7	2		T12	4
valid_sources[0x7c]	24475	1			T4	2		T6	6		T7	15
valid_sources[0x7d]	25116	1			T11	1		T4	1		T6	2
valid_sources[0x7e]	42029	1			T11	1		T4	6		T6	5
valid_sources[0x7f]	34941	1			T4	3		T6	10		T7	5
valid_sources[0x80]	37499	1			T4	7		T6	1		T7	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1960944

1

T1

2

T2

157

T3

213

values[0x0]

all_enables

biggest_size

308672

1

T1

1

T2

71

T3

89

values[0x1]

all_enables

biggest_size

246106

1

T1

3

T2

64

T3

72

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28131	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

602359

1

T3

80

T4

20

T6

60

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	194771	1			T3	40		T4	10		T6	30
values[0x0]	212430	1			T3	19		T4	6		T6	14
values[0x1]	223289	1			T3	21		T4	4		T6	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14929	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

615561

1

T3

80

T4

20

T6

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2290	1			T6	2		T17	2		T88	1
valid_sources[0x01]	2353	1			T3	1		T6	3		T26	1
valid_sources[0x02]	2144	1			T6	2		T17	1		T65	4
valid_sources[0x03]	2191	1			T17	1		T84	4		T28	4
valid_sources[0x04]	2351	1			T101	1		T65	7		T192	1
valid_sources[0x05]	2698	1			T73	1		T27	2		T59	2
valid_sources[0x06]	2402	1			T3	1		T27	2		T97	1
valid_sources[0x07]	2482	1			T102	1		T59	2		T49	2
valid_sources[0x08]	2669	1			T13	33		T26	1		T27	1
valid_sources[0x09]	2210	1			T88	3		T198	3		T28	7
valid_sources[0x0a]	2063	1			T6	1		T17	2		T27	1
valid_sources[0x0b]	2312	1			T17	2		T28	2		T94	9
valid_sources[0x0c]	2402	1			T3	2		T17	3		T26	1
valid_sources[0x0d]	2435	1			T4	1		T26	1		T90	1
valid_sources[0x0e]	2508	1			T85	9		T27	1		T90	1
valid_sources[0x0f]	2757	1			T26	1		T102	1		T27	1
valid_sources[0x10]	2836	1			T198	1		T28	2		T39	2
valid_sources[0x11]	2592	1			T17	2		T84	1		T90	2
valid_sources[0x12]	2183	1			T3	1		T7	1		T28	2
valid_sources[0x13]	2610	1			T73	1		T88	1		T198	4
valid_sources[0x14]	3320	1			T3	1		T88	2		T28	2
valid_sources[0x15]	2332	1			T88	1		T90	1		T28	1
valid_sources[0x16]	2369	1			T3	2		T7	1		T90	1
valid_sources[0x17]	2692	1			T51	2		T91	1		T95	5
valid_sources[0x18]	2312	1			T102	1		T88	2		T198	1
valid_sources[0x19]	2219	1			T27	3		T59	2		T88	2
valid_sources[0x1a]	2595	1			T17	1		T26	2		T65	1
valid_sources[0x1b]	2355	1			T192	3		T94	1		T14	15
valid_sources[0x1c]	2574	1			T17	1		T26	1		T59	4
valid_sources[0x1d]	2958	1			T17	1		T51	2		T90	1
valid_sources[0x1e]	2282	1			T7	4		T13	19		T27	2
valid_sources[0x1f]	2346	1			T65	1		T84	1		T198	1
valid_sources[0x20]	2282	1			T102	1		T27	3		T84	1
valid_sources[0x21]	2486	1			T91	1		T28	2		T95	2
valid_sources[0x22]	2568	1			T6	2		T17	1		T26	1
valid_sources[0x23]	2110	1			T26	1		T65	2		T198	1
valid_sources[0x24]	2344	1			T102	1		T90	2		T91	1
valid_sources[0x25]	2268	1			T26	1		T102	1		T27	1
valid_sources[0x26]	3183	1			T4	1		T27	1		T198	5
valid_sources[0x27]	2296	1			T6	1		T7	1		T17	1
valid_sources[0x28]	2508	1			T4	1		T84	1		T198	1
valid_sources[0x29]	2194	1			T17	1		T26	1		T27	1
valid_sources[0x2a]	2254	1			T3	1		T73	1		T26	1
valid_sources[0x2b]	2686	1			T101	2		T198	4		T51	3
valid_sources[0x2c]	2256	1			T6	3		T59	1		T95	1
valid_sources[0x2d]	2463	1			T4	1		T17	1		T27	1
valid_sources[0x2e]	2348	1			T6	1		T90	1		T91	1
valid_sources[0x2f]	2566	1			T17	1		T48	160		T27	1
valid_sources[0x30]	2483	1			T26	1		T9	5		T88	1
valid_sources[0x31]	2296	1			T85	1		T9	1		T65	3
valid_sources[0x32]	2250	1			T3	1		T6	3		T26	1
valid_sources[0x33]	2304	1			T27	1		T59	3		T65	4
valid_sources[0x34]	2968	1			T17	3		T59	2		T88	2
valid_sources[0x35]	2507	1			T88	2		T198	1		T472	1
valid_sources[0x36]	2267	1			T7	2		T198	3		T90	1
valid_sources[0x37]	2114	1			T73	2		T17	5		T59	1
valid_sources[0x38]	2497	1			T3	2		T17	3		T9	1
valid_sources[0x39]	2349	1			T3	1		T4	1		T17	1
valid_sources[0x3a]	2467	1			T4	1		T27	2		T65	10
valid_sources[0x3b]	2520	1			T17	1		T101	1		T102	3
valid_sources[0x3c]	2958	1			T7	4		T27	1		T90	1
valid_sources[0x3d]	2285	1			T6	1		T7	2		T101	1
valid_sources[0x3e]	2147	1			T4	1		T26	1		T90	1
valid_sources[0x3f]	2408	1			T17	1		T65	4		T91	1
valid_sources[0x40]	2118	1			T26	1		T27	1		T84	3
valid_sources[0x41]	2724	1			T28	1		T92	1		T79	1
valid_sources[0x42]	2698	1			T26	1		T9	1		T65	1
valid_sources[0x43]	2509	1			T59	2		T65	3		T198	1
valid_sources[0x44]	2510	1			T102	2		T198	2		T28	1
valid_sources[0x45]	2168	1			T6	1		T51	2		T97	1
valid_sources[0x46]	2717	1			T17	1		T89	49		T28	1
valid_sources[0x47]	2686	1			T17	1		T102	2		T27	1
valid_sources[0x48]	2721	1			T65	7		T198	1		T90	1
valid_sources[0x49]	2229	1			T3	2		T27	1		T84	1
valid_sources[0x4a]	2492	1			T17	1		T85	1		T90	2
valid_sources[0x4b]	2776	1			T26	1		T9	1		T198	2
valid_sources[0x4c]	1992	1			T4	1		T7	3		T59	1
valid_sources[0x4d]	2542	1			T26	1		T88	1		T51	1
valid_sources[0x4e]	2181	1			T17	1		T198	1		T91	1
valid_sources[0x4f]	1965	1			T26	1		T262	1		T14	16
valid_sources[0x50]	2895	1			T27	2		T97	3		T262	4
valid_sources[0x51]	2277	1			T90	1		T91	1		T28	1
valid_sources[0x52]	2503	1			T4	1		T17	2		T27	2
valid_sources[0x53]	2475	1			T3	1		T97	1		T14	25
valid_sources[0x54]	2211	1			T26	1		T101	1		T27	2
valid_sources[0x55]	2361	1			T18	100		T27	1		T65	3
valid_sources[0x56]	2662	1			T6	1		T102	2		T27	1
valid_sources[0x57]	2350	1			T26	1		T27	1		T51	1
valid_sources[0x58]	2402	1			T6	1		T73	1		T27	1
valid_sources[0x59]	2409	1			T17	4		T102	1		T28	3
valid_sources[0x5a]	2454	1			T27	1		T65	7		T92	1
valid_sources[0x5b]	2242	1			T27	1		T51	1		T28	1
valid_sources[0x5c]	2208	1			T90	2		T91	1		T92	1
valid_sources[0x5d]	2180	1			T27	1		T91	5		T28	1
valid_sources[0x5e]	2091	1			T73	6		T17	2		T94	5
valid_sources[0x5f]	2478	1			T17	1		T101	1		T84	1
valid_sources[0x60]	2298	1			T3	1		T90	2		T93	2
valid_sources[0x61]	2435	1			T3	1		T4	1		T27	2
valid_sources[0x62]	2264	1			T3	3		T13	6		T17	1
valid_sources[0x63]	2192	1			T7	2		T17	1		T26	1
valid_sources[0x64]	2653	1			T26	2		T28	3		T92	1
valid_sources[0x65]	2305	1			T3	1		T9	1		T65	4
valid_sources[0x66]	2031	1			T4	1		T6	1		T97	2
valid_sources[0x67]	2177	1			T9	1		T198	4		T28	1
valid_sources[0x68]	2351	1			T84	1		T198	1		T90	2
valid_sources[0x69]	2134	1			T90	1		T192	1		T14	24
valid_sources[0x6a]	2263	1			T27	2		T91	1		T28	1
valid_sources[0x6b]	2683	1			T3	1		T7	2		T26	1
valid_sources[0x6c]	2306	1			T3	1		T6	1		T88	1
valid_sources[0x6d]	2861	1			T3	2		T17	3		T90	1
valid_sources[0x6e]	2385	1			T6	1		T65	6		T88	1
valid_sources[0x6f]	2528	1			T17	2		T84	2		T88	2
valid_sources[0x70]	3106	1			T26	1		T65	2		T88	1
valid_sources[0x71]	2515	1			T27	1		T88	5		T198	5
valid_sources[0x72]	2259	1			T84	1		T79	1		T80	3
valid_sources[0x73]	3882	1			T4	1		T65	2		T88	5
valid_sources[0x74]	2752	1			T88	1		T91	1		T49	1
valid_sources[0x75]	2568	1			T27	1		T90	1		T28	1
valid_sources[0x76]	2337	1			T3	3		T6	1		T75	6
valid_sources[0x77]	2472	1			T6	1		T59	1		T65	3
valid_sources[0x78]	2399	1			T73	2		T17	1		T91	1
valid_sources[0x79]	2480	1			T13	37		T27	1		T84	1
valid_sources[0x7a]	2301	1			T7	2		T17	2		T26	2
valid_sources[0x7b]	2510	1			T17	1		T85	2		T101	1
valid_sources[0x7c]	2432	1			T6	3		T51	1		T90	1
valid_sources[0x7d]	2271	1			T65	4		T198	1		T91	1
valid_sources[0x7e]	2588	1			T6	3		T88	1		T91	1
valid_sources[0x7f]	2603	1			T6	1		T13	27		T27	1
valid_sources[0x80]	2689	1			T26	1		T59	3		T84	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

181903

1

T3

40

T4

10

T6

30

values[0x0]

all_enables

biggest_size

210862

1

T3

19

T4

6

T6

14

values[0x1]

all_enables

biggest_size

209594

1

T3

21

T4

4

T6

16