Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7306460	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6903070

1

T1

1556

T2

5

T3

218

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8415713	1			T1	3119		T2	4		T3	943
values[0x0]	2209368	1			T1	420		T2	5		T3	117
values[0x1]	3584449	1			T1	376		T2	10		T3	135

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4758363	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9451167

1

T1

2096

T2

5

T3

518

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53431	1			T1	7		T3	25		T4	4
valid_sources[0x01]	49002	1			T1	12		T4	11		T6	5
valid_sources[0x02]	50642	1			T1	11		T3	7		T4	10
valid_sources[0x03]	56636	1			T1	19		T4	9		T11	31
valid_sources[0x04]	51726	1			T1	17		T3	5		T4	6
valid_sources[0x05]	49558	1			T1	16		T3	4		T4	7
valid_sources[0x06]	62513	1			T1	17		T3	3		T4	10
valid_sources[0x07]	59261	1			T1	13		T3	9		T6	21
valid_sources[0x08]	57020	1			T1	12		T3	1		T4	6
valid_sources[0x09]	51055	1			T1	11		T3	2		T4	6
valid_sources[0x0a]	52711	1			T1	11		T3	14		T4	5
valid_sources[0x0b]	58988	1			T1	8		T4	7		T6	58
valid_sources[0x0c]	64428	1			T1	19		T3	5		T4	2
valid_sources[0x0d]	51046	1			T1	15		T3	1		T4	14
valid_sources[0x0e]	54005	1			T1	18		T3	3		T4	7
valid_sources[0x0f]	53715	1			T1	14		T3	3		T4	8
valid_sources[0x10]	60785	1			T1	17		T4	6		T11	31
valid_sources[0x11]	60766	1			T1	14		T3	17		T4	8
valid_sources[0x12]	46981	1			T1	11		T3	4		T4	6
valid_sources[0x13]	49130	1			T1	15		T4	9		T11	13
valid_sources[0x14]	53014	1			T1	19		T3	6		T4	5
valid_sources[0x15]	47514	1			T1	12		T3	7		T4	11
valid_sources[0x16]	52653	1			T1	19		T4	1		T6	4
valid_sources[0x17]	50462	1			T1	24		T3	2		T4	2
valid_sources[0x18]	53569	1			T1	15		T3	3		T4	9
valid_sources[0x19]	48282	1			T1	11		T3	1		T4	14
valid_sources[0x1a]	53958	1			T1	12		T3	3		T4	5
valid_sources[0x1b]	52821	1			T1	8		T4	5		T6	26
valid_sources[0x1c]	49313	1			T1	26		T3	3		T4	5
valid_sources[0x1d]	53865	1			T1	13		T4	3		T6	16
valid_sources[0x1e]	58334	1			T1	13		T4	15		T11	9
valid_sources[0x1f]	66478	1			T1	14		T4	9		T11	4
valid_sources[0x20]	48958	1			T1	27		T4	3		T6	36
valid_sources[0x21]	52890	1			T1	21		T3	5		T4	5
valid_sources[0x22]	49893	1			T1	22		T4	3		T6	7
valid_sources[0x23]	50332	1			T1	12		T3	5		T4	14
valid_sources[0x24]	50730	1			T1	12		T4	12		T6	3
valid_sources[0x25]	94769	1			T1	13		T3	7		T4	18
valid_sources[0x26]	51090	1			T1	19		T3	12		T4	7
valid_sources[0x27]	50622	1			T1	16		T3	20		T4	11
valid_sources[0x28]	48271	1			T1	9		T3	12		T4	6
valid_sources[0x29]	50175	1			T1	7		T3	2		T4	2
valid_sources[0x2a]	55390	1			T1	14		T4	12		T6	28
valid_sources[0x2b]	64312	1			T1	7		T3	2		T4	5
valid_sources[0x2c]	57314	1			T1	21		T3	4		T4	2
valid_sources[0x2d]	53032	1			T1	14		T3	4		T4	9
valid_sources[0x2e]	50284	1			T1	10		T4	8		T6	25
valid_sources[0x2f]	51917	1			T1	7		T3	5		T4	3
valid_sources[0x30]	52673	1			T1	9		T3	8		T4	6
valid_sources[0x31]	58095	1			T1	12		T3	9		T4	6
valid_sources[0x32]	51117	1			T1	12		T3	9		T4	7
valid_sources[0x33]	145919	1			T1	12		T4	2		T6	16
valid_sources[0x34]	57142	1			T1	28		T3	3		T4	6
valid_sources[0x35]	54881	1			T1	17		T3	3		T4	11
valid_sources[0x36]	63545	1			T1	14		T3	3		T4	10
valid_sources[0x37]	50936	1			T1	20		T3	9		T4	3
valid_sources[0x38]	50520	1			T1	19		T3	1		T4	12
valid_sources[0x39]	52892	1			T1	21		T3	2		T4	8
valid_sources[0x3a]	53751	1			T1	16		T3	5		T6	29
valid_sources[0x3b]	48146	1			T1	16		T4	16		T6	9
valid_sources[0x3c]	49595	1			T1	13		T3	6		T4	5
valid_sources[0x3d]	51771	1			T1	17		T4	7		T11	23
valid_sources[0x3e]	55639	1			T1	14		T3	1		T6	15
valid_sources[0x3f]	54027	1			T1	10		T3	10		T4	11
valid_sources[0x40]	51585	1			T1	13		T3	11		T4	1
valid_sources[0x41]	54190	1			T1	19		T4	13		T11	31
valid_sources[0x42]	51109	1			T1	19		T3	2		T4	7
valid_sources[0x43]	54783	1			T1	13		T4	1		T6	19
valid_sources[0x44]	267404	1			T1	5		T3	3		T4	7
valid_sources[0x45]	64300	1			T1	19		T3	1		T4	5
valid_sources[0x46]	50745	1			T1	17		T4	9		T6	6
valid_sources[0x47]	67411	1			T1	9		T3	3		T4	9
valid_sources[0x48]	49056	1			T1	14		T3	21		T4	4
valid_sources[0x49]	48973	1			T1	19		T3	5		T4	3
valid_sources[0x4a]	56084	1			T1	17		T3	4		T4	6
valid_sources[0x4b]	51227	1			T1	24		T3	6		T11	35
valid_sources[0x4c]	74623	1			T1	9		T4	3		T6	6
valid_sources[0x4d]	48674	1			T1	16		T4	3		T6	19
valid_sources[0x4e]	52371	1			T1	13		T4	2		T6	32
valid_sources[0x4f]	62157	1			T1	12		T3	8		T4	23
valid_sources[0x50]	51597	1			T1	12		T4	3		T6	9
valid_sources[0x51]	57066	1			T1	12		T4	11		T6	12
valid_sources[0x52]	49231	1			T1	15		T3	1		T4	12
valid_sources[0x53]	52777	1			T1	12		T4	6		T6	12
valid_sources[0x54]	51620	1			T1	16		T3	10		T4	2
valid_sources[0x55]	51068	1			T1	13		T3	17		T4	7
valid_sources[0x56]	54446	1			T1	17		T3	4		T4	7
valid_sources[0x57]	49430	1			T1	17		T3	8		T4	7
valid_sources[0x58]	50310	1			T1	10		T3	28		T4	12
valid_sources[0x59]	48898	1			T1	12		T3	5		T4	6
valid_sources[0x5a]	49884	1			T1	14		T4	11		T6	3
valid_sources[0x5b]	52843	1			T1	13		T3	2		T4	12
valid_sources[0x5c]	49791	1			T1	13		T4	5		T6	14
valid_sources[0x5d]	49830	1			T1	20		T3	8		T4	4
valid_sources[0x5e]	114822	1			T1	14		T3	3		T4	4
valid_sources[0x5f]	55183	1			T1	16		T4	3		T6	16
valid_sources[0x60]	58103	1			T1	7		T3	6		T4	14
valid_sources[0x61]	51924	1			T1	10		T4	9		T11	63
valid_sources[0x62]	54855	1			T1	24		T3	1		T4	5
valid_sources[0x63]	48593	1			T1	8		T4	7		T11	10
valid_sources[0x64]	69640	1			T1	16		T3	4		T4	13
valid_sources[0x65]	52198	1			T1	17		T4	4		T11	8
valid_sources[0x66]	64698	1			T1	15		T3	2		T4	6
valid_sources[0x67]	50552	1			T1	15		T4	6		T6	22
valid_sources[0x68]	50114	1			T1	15		T4	9		T6	10
valid_sources[0x69]	54985	1			T1	14		T3	2		T4	7
valid_sources[0x6a]	67463	1			T1	21		T3	8		T4	10
valid_sources[0x6b]	49353	1			T1	10		T3	4		T4	7
valid_sources[0x6c]	53498	1			T1	19		T4	4		T6	12
valid_sources[0x6d]	49722	1			T1	13		T3	3		T4	2
valid_sources[0x6e]	48663	1			T1	19		T4	5		T11	13
valid_sources[0x6f]	58481	1			T1	15		T4	9		T6	12
valid_sources[0x70]	50264	1			T1	18		T3	5		T4	14
valid_sources[0x71]	49213	1			T1	21		T3	16		T4	9
valid_sources[0x72]	50494	1			T1	17		T3	2		T4	17
valid_sources[0x73]	53798	1			T1	21		T4	19		T6	28
valid_sources[0x74]	49875	1			T1	11		T3	21		T4	14
valid_sources[0x75]	49699	1			T1	23		T3	7		T4	17
valid_sources[0x76]	49602	1			T1	18		T4	1		T6	10
valid_sources[0x77]	55723	1			T1	16		T3	10		T4	13
valid_sources[0x78]	50048	1			T1	16		T3	14		T4	13
valid_sources[0x79]	51510	1			T1	14		T3	11		T4	8
valid_sources[0x7a]	57374	1			T1	22		T4	6		T6	33
valid_sources[0x7b]	51728	1			T1	18		T3	14		T4	11
valid_sources[0x7c]	52434	1			T1	10		T3	3		T4	14
valid_sources[0x7d]	60470	1			T1	10		T3	3		T4	16
valid_sources[0x7e]	52148	1			T1	16		T3	2		T4	19
valid_sources[0x7f]	55022	1			T1	23		T4	30		T11	37
valid_sources[0x80]	63719	1			T1	20		T4	9		T6	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3333119

1

T1

1248

T2

1

T3

103

values[0x0]

all_enables

biggest_size

1823346

1

T1

185

T2

2

T3

62

values[0x1]

all_enables

biggest_size

1746605

1

T1

123

T2

2

T3

53

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	234597	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8496384

1

T1

140

T4

40

T5

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2173661	1			T1	70		T4	20		T5	20
values[0x0]	3185912	1			T1	38		T4	11		T5	11
values[0x1]	3371408	1			T1	32		T4	9		T5	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	84871	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8646110

1

T1

140

T4

40

T5

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	34053	1			T134	1		T97	3		T95	2
valid_sources[0x01]	34786	1			T1	2		T12	1		T133	1
valid_sources[0x02]	33256	1			T6	1		T11	1		T12	1
valid_sources[0x03]	33130	1			T1	5		T12	1		T97	1
valid_sources[0x04]	33641	1			T11	1		T97	4		T265	1
valid_sources[0x05]	34934	1			T11	1		T95	1		T265	1
valid_sources[0x06]	36100	1			T12	1		T132	1		T266	1
valid_sources[0x07]	33374	1			T11	1		T12	1		T97	1
valid_sources[0x08]	33845	1			T99	1		T265	3		T129	1
valid_sources[0x09]	35014	1			T103	1		T51	1		T265	1
valid_sources[0x0a]	33485	1			T99	2		T96	1		T124	3
valid_sources[0x0b]	34454	1			T6	1		T127	1		T265	1
valid_sources[0x0c]	35045	1			T12	2		T135	1		T97	2
valid_sources[0x0d]	35360	1			T6	1		T11	1		T12	1
valid_sources[0x0e]	33845	1			T1	6		T51	1		T265	1
valid_sources[0x0f]	33656	1			T6	1		T132	2		T94	3
valid_sources[0x10]	34586	1			T94	2		T95	1		T51	1
valid_sources[0x11]	33718	1			T12	1		T135	1		T97	1
valid_sources[0x12]	32466	1			T134	1		T51	1		T19	1
valid_sources[0x13]	34320	1			T1	3		T6	1		T12	2
valid_sources[0x14]	34053	1			T12	3		T97	1		T127	1
valid_sources[0x15]	33728	1			T5	2		T99	1		T97	1
valid_sources[0x16]	34418	1			T12	2		T95	2		T141	1
valid_sources[0x17]	35367	1			T99	1		T134	1		T95	1
valid_sources[0x18]	33879	1			T12	1		T134	1		T95	1
valid_sources[0x19]	33330	1			T4	1		T12	1		T133	1
valid_sources[0x1a]	34537	1			T11	1		T12	1		T96	1
valid_sources[0x1b]	34120	1			T12	1		T127	1		T141	2
valid_sources[0x1c]	32355	1			T1	7		T132	1		T97	1
valid_sources[0x1d]	34221	1			T129	1		T233	1		T177	1
valid_sources[0x1e]	32465	1			T1	1		T12	1		T99	1
valid_sources[0x1f]	33107	1			T1	1		T12	1		T94	10
valid_sources[0x20]	33805	1			T12	2		T97	3		T127	2
valid_sources[0x21]	34596	1			T4	1		T12	4		T99	1
valid_sources[0x22]	34983	1			T12	1		T99	2		T96	1
valid_sources[0x23]	35182	1			T4	1		T11	1		T12	2
valid_sources[0x24]	34771	1			T4	1		T6	1		T12	1
valid_sources[0x25]	35397	1			T99	1		T134	1		T96	7
valid_sources[0x26]	35111	1			T1	4		T12	1		T95	3
valid_sources[0x27]	33657	1			T6	1		T12	3		T99	1
valid_sources[0x28]	33613	1			T6	2		T11	1		T12	1
valid_sources[0x29]	33544	1			T12	1		T96	2		T129	2
valid_sources[0x2a]	34211	1			T12	1		T99	1		T95	2
valid_sources[0x2b]	34151	1			T11	1		T12	1		T134	1
valid_sources[0x2c]	34605	1			T12	2		T99	1		T97	1
valid_sources[0x2d]	34006	1			T6	1		T132	1		T95	1
valid_sources[0x2e]	33195	1			T99	1		T133	1		T95	1
valid_sources[0x2f]	34707	1			T1	6		T12	1		T99	1
valid_sources[0x30]	33568	1			T11	2		T132	1		T97	8
valid_sources[0x31]	34202	1			T6	1		T11	2		T12	1
valid_sources[0x32]	33949	1			T5	2		T97	3		T51	1
valid_sources[0x33]	34195	1			T1	5		T134	1		T97	1
valid_sources[0x34]	35163	1			T12	1		T134	1		T95	2
valid_sources[0x35]	32684	1			T100	1		T133	1		T97	5
valid_sources[0x36]	33788	1			T12	2		T99	1		T51	2
valid_sources[0x37]	33859	1			T12	2		T95	1		T96	2
valid_sources[0x38]	33341	1			T5	1		T12	2		T99	1
valid_sources[0x39]	33461	1			T5	1		T12	1		T100	2
valid_sources[0x3a]	34417	1			T99	1		T96	1		T129	1
valid_sources[0x3b]	35823	1			T99	1		T132	2		T96	1
valid_sources[0x3c]	35105	1			T12	1		T99	2		T127	3
valid_sources[0x3d]	32972	1			T134	1		T95	2		T231	1
valid_sources[0x3e]	33872	1			T1	1		T135	1		T97	1
valid_sources[0x3f]	33739	1			T6	1		T12	1		T132	1
valid_sources[0x40]	34247	1			T12	2		T97	1		T129	3
valid_sources[0x41]	34179	1			T12	1		T133	3		T134	1
valid_sources[0x42]	35204	1			T12	1		T133	1		T97	2
valid_sources[0x43]	34232	1			T11	5		T133	4		T97	1
valid_sources[0x44]	34079	1			T99	3		T124	1		T51	1
valid_sources[0x45]	32927	1			T1	1		T100	1		T7	1
valid_sources[0x46]	33999	1			T12	2		T127	1		T238	1
valid_sources[0x47]	34504	1			T6	1		T12	3		T100	1
valid_sources[0x48]	34763	1			T1	1		T12	1		T95	1
valid_sources[0x49]	33696	1			T1	2		T12	2		T95	1
valid_sources[0x4a]	35712	1			T11	2		T12	1		T95	1
valid_sources[0x4b]	33931	1			T1	7		T99	1		T132	1
valid_sources[0x4c]	33782	1			T12	3		T99	1		T134	2
valid_sources[0x4d]	34365	1			T5	2		T99	1		T133	1
valid_sources[0x4e]	33187	1			T99	1		T96	2		T265	1
valid_sources[0x4f]	34156	1			T5	1		T99	1		T96	1
valid_sources[0x50]	33583	1			T1	2		T4	1		T11	1
valid_sources[0x51]	34212	1			T6	1		T11	1		T12	1
valid_sources[0x52]	34660	1			T12	2		T96	1		T51	1
valid_sources[0x53]	34473	1			T1	4		T12	2		T94	10
valid_sources[0x54]	33667	1			T6	1		T133	2		T152	20
valid_sources[0x55]	33193	1			T5	1		T12	3		T99	1
valid_sources[0x56]	33745	1			T5	2		T51	1		T266	2
valid_sources[0x57]	35167	1			T11	1		T99	1		T96	3
valid_sources[0x58]	33692	1			T12	1		T133	3		T95	1
valid_sources[0x59]	34157	1			T12	1		T97	1		T127	1
valid_sources[0x5a]	34232	1			T12	1		T135	1		T124	3
valid_sources[0x5b]	34650	1			T6	1		T12	1		T99	1
valid_sources[0x5c]	33514	1			T99	2		T132	1		T133	4
valid_sources[0x5d]	33350	1			T4	2		T12	3		T132	2
valid_sources[0x5e]	33911	1			T1	3		T12	3		T99	1
valid_sources[0x5f]	33746	1			T5	3		T11	1		T12	1
valid_sources[0x60]	34759	1			T5	1		T12	1		T99	1
valid_sources[0x61]	34068	1			T12	1		T99	2		T132	1
valid_sources[0x62]	34452	1			T12	1		T97	4		T127	2
valid_sources[0x63]	33664	1			T99	1		T132	1		T51	1
valid_sources[0x64]	34320	1			T100	2		T132	2		T95	1
valid_sources[0x65]	34656	1			T99	1		T96	2		T231	1
valid_sources[0x66]	33468	1			T12	1		T132	1		T124	1
valid_sources[0x67]	35707	1			T6	2		T12	1		T133	2
valid_sources[0x68]	33826	1			T4	1		T99	1		T95	3
valid_sources[0x69]	32637	1			T1	5		T11	1		T132	2
valid_sources[0x6a]	34071	1			T12	1		T265	2		T232	1
valid_sources[0x6b]	34689	1			T134	1		T135	1		T141	1
valid_sources[0x6c]	33710	1			T11	3		T12	2		T133	2
valid_sources[0x6d]	33748	1			T1	3		T11	3		T12	1
valid_sources[0x6e]	33072	1			T11	1		T12	1		T99	1
valid_sources[0x6f]	33670	1			T5	1		T12	1		T134	1
valid_sources[0x70]	34781	1			T5	1		T11	1		T12	2
valid_sources[0x71]	33434	1			T99	1		T95	3		T231	1
valid_sources[0x72]	34684	1			T11	5		T12	1		T99	1
valid_sources[0x73]	33797	1			T99	1		T94	13		T95	2
valid_sources[0x74]	34469	1			T12	1		T135	1		T127	1
valid_sources[0x75]	35411	1			T11	1		T7	1		T127	1
valid_sources[0x76]	34968	1			T5	1		T12	1		T99	3
valid_sources[0x77]	33610	1			T99	2		T127	1		T238	1
valid_sources[0x78]	33720	1			T4	1		T12	2		T132	2
valid_sources[0x79]	35154	1			T133	2		T97	2		T51	2
valid_sources[0x7a]	35823	1			T96	1		T127	1		T129	1
valid_sources[0x7b]	34521	1			T4	1		T124	1		T265	1
valid_sources[0x7c]	35189	1			T12	2		T99	1		T94	8
valid_sources[0x7d]	34289	1			T12	2		T99	1		T95	1
valid_sources[0x7e]	33541	1			T5	1		T132	1		T134	1
valid_sources[0x7f]	33889	1			T12	1		T99	1		T231	1
valid_sources[0x80]	35084	1			T12	2		T132	2		T95	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2161278

1

T1

70

T4

20

T5

20

values[0x0]

all_enables

biggest_size

3169719

1

T1

38

T4

11

T5

11

values[0x1]

all_enables

biggest_size

3165387

1

T1

32

T4

9

T5

9